arch/arm/dts/uniphier-pxs3.dtsi

   1 /*
   2  * Device Tree Source for UniPhier PXs3 SoC
   3  *
   4  * Copyright (C) 2017 Socionext Inc.
   5  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   6  *
   7  * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   8  */
   9
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/gpio/uniphier-gpio.h>
  12
  13 /memreserve/ 0x80000000 0x02000000;
  14
  15 / {
  16         compatible = "socionext,uniphier-pxs3";
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19         interrupt-parent = <&gic>;
  20
  21         cpus {
  22                 #address-cells = <2>;
  23                 #size-cells = <0>;
  24
  25                 cpu-map {
  26                         cluster0 {
  27                                 core0 {
  28                                         cpu = <&cpu0>;
  29                                 };
  30                                 core1 {
  31                                         cpu = <&cpu1>;
  32                                 };
  33                                 core2 {
  34                                         cpu = <&cpu2>;
  35                                 };
  36                                 core3 {
  37                                         cpu = <&cpu3>;
  38                                 };
  39                         };
  40                 };
  41
  42                 cpu0: cpu@0 {
  43                         device_type = "cpu";
  44                         compatible = "arm,cortex-a53", "arm,armv8";
  45                         reg = <0 0x000>;
  46                         clocks = <&sys_clk 33>;
  47                         enable-method = "psci";
  48                         operating-points-v2 = <&cluster0_opp>;
  49                 };
  50
  51                 cpu1: cpu@1 {
  52                         device_type = "cpu";
  53                         compatible = "arm,cortex-a53", "arm,armv8";
  54                         reg = <0 0x001>;
  55                         clocks = <&sys_clk 33>;
  56                         enable-method = "psci";
  57                         operating-points-v2 = <&cluster0_opp>;
  58                 };
  59
  60                 cpu2: cpu@2 {
  61                         device_type = "cpu";
  62                         compatible = "arm,cortex-a53", "arm,armv8";
  63                         reg = <0 0x002>;
  64                         clocks = <&sys_clk 33>;
  65                         enable-method = "psci";
  66                         operating-points-v2 = <&cluster0_opp>;
  67                 };
  68
  69                 cpu3: cpu@3 {
  70                         device_type = "cpu";
  71                         compatible = "arm,cortex-a53", "arm,armv8";
  72                         reg = <0 0x003>;
  73                         clocks = <&sys_clk 33>;
  74                         enable-method = "psci";
  75                         operating-points-v2 = <&cluster0_opp>;
  76                 };
  77         };
  78
  79         cluster0_opp: opp-table {
  80                 compatible = "operating-points-v2";
  81                 opp-shared;
  82
  83                 opp-250000000 {
  84                         opp-hz = /bits/ 64 <250000000>;
  85                         clock-latency-ns = <300>;
  86                 };
  87                 opp-325000000 {
  88                         opp-hz = /bits/ 64 <325000000>;
  89                         clock-latency-ns = <300>;
  90                 };
  91                 opp-500000000 {
  92                         opp-hz = /bits/ 64 <500000000>;
  93                         clock-latency-ns = <300>;
  94                 };
  95                 opp-650000000 {
  96                         opp-hz = /bits/ 64 <650000000>;
  97                         clock-latency-ns = <300>;
  98                 };
  99                 opp-666667000 {
 100                         opp-hz = /bits/ 64 <666667000>;
 101                         clock-latency-ns = <300>;
 102                 };
 103                 opp-866667000 {
 104                         opp-hz = /bits/ 64 <866667000>;
 105                         clock-latency-ns = <300>;
 106                 };
 107                 opp-1000000000 {
 108                         opp-hz = /bits/ 64 <1000000000>;
 109                         clock-latency-ns = <300>;
 110                 };
 111                 opp-1300000000 {
 112                         opp-hz = /bits/ 64 <1300000000>;
 113                         clock-latency-ns = <300>;
 114                 };
 115         };
 116
 117         psci {
 118                 compatible = "arm,psci-1.0";
 119                 method = "smc";
 120         };
 121
 122         clocks {
 123                 refclk: ref {
 124                         compatible = "fixed-clock";
 125                         #clock-cells = <0>;
 126                         clock-frequency = <25000000>;
 127                 };
 128         };
 129
 130         emmc_pwrseq: emmc-pwrseq {
 131                 compatible = "mmc-pwrseq-emmc";
 132                 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(5, 7) GPIO_ACTIVE_LOW>;
 133         };
 134
 135         timer {
 136                 compatible = "arm,armv8-timer";
 137                 interrupts = <1 13 4>,
 138                              <1 14 4>,
 139                              <1 11 4>,
 140                              <1 10 4>;
 141         };
 142
 143         soc@0 {
 144                 compatible = "simple-bus";
 145                 #address-cells = <1>;
 146                 #size-cells = <1>;
 147                 ranges = <0 0 0 0xffffffff>;
 148
 149                 serial0: serial@54006800 {
 150                         compatible = "socionext,uniphier-uart";
 151                         status = "disabled";
 152                         reg = <0x54006800 0x40>;
 153                         interrupts = <0 33 4>;
 154                         pinctrl-names = "default";
 155                         pinctrl-0 = <&pinctrl_uart0>;
 156                         clocks = <&peri_clk 0>;
 157                         clock-frequency = <58820000>;
 158                         resets = <&peri_rst 0>;
 159                 };
 160
 161                 serial1: serial@54006900 {
 162                         compatible = "socionext,uniphier-uart";
 163                         status = "disabled";
 164                         reg = <0x54006900 0x40>;
 165                         interrupts = <0 35 4>;
 166                         pinctrl-names = "default";
 167                         pinctrl-0 = <&pinctrl_uart1>;
 168                         clocks = <&peri_clk 1>;
 169                         clock-frequency = <58820000>;
 170                         resets = <&peri_rst 1>;
 171                 };
 172
 173                 serial2: serial@54006a00 {
 174                         compatible = "socionext,uniphier-uart";
 175                         status = "disabled";
 176                         reg = <0x54006a00 0x40>;
 177                         interrupts = <0 37 4>;
 178                         pinctrl-names = "default";
 179                         pinctrl-0 = <&pinctrl_uart2>;
 180                         clocks = <&peri_clk 2>;
 181                         clock-frequency = <58820000>;
 182                         resets = <&peri_rst 2>;
 183                 };
 184
 185                 serial3: serial@54006b00 {
 186                         compatible = "socionext,uniphier-uart";
 187                         status = "disabled";
 188                         reg = <0x54006b00 0x40>;
 189                         interrupts = <0 177 4>;
 190                         pinctrl-names = "default";
 191                         pinctrl-0 = <&pinctrl_uart3>;
 192                         clocks = <&peri_clk 3>;
 193                         clock-frequency = <58820000>;
 194                         resets = <&peri_rst 3>;
 195                 };
 196
 197                 gpio: gpio@55000000 {
 198                         compatible = "socionext,uniphier-gpio";
 199                         reg = <0x55000000 0x200>;
 200                         interrupt-parent = <&aidet>;
 201                         interrupt-controller;
 202                         #interrupt-cells = <2>;
 203                         gpio-controller;
 204                         #gpio-cells = <2>;
 205                         gpio-ranges = <&pinctrl 0 0 0>,
 206                                       <&pinctrl 96 0 0>,
 207                                       <&pinctrl 160 0 0>;
 208                         gpio-ranges-group-names = "gpio_range0",
 209                                                   "gpio_range1",
 210                                                   "gpio_range2";
 211                         ngpios = <286>;
 212                         socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
 213                                                      <21 217 3>;
 214                 };
 215
 216                 i2c0: i2c@58780000 {
 217                         compatible = "socionext,uniphier-fi2c";
 218                         status = "disabled";
 219                         reg = <0x58780000 0x80>;
 220                         #address-cells = <1>;
 221                         #size-cells = <0>;
 222                         interrupts = <0 41 4>;
 223                         pinctrl-names = "default";
 224                         pinctrl-0 = <&pinctrl_i2c0>;
 225                         clocks = <&peri_clk 4>;
 226                         resets = <&peri_rst 4>;
 227                         clock-frequency = <100000>;
 228                 };
 229
 230                 i2c1: i2c@58781000 {
 231                         compatible = "socionext,uniphier-fi2c";
 232                         status = "disabled";
 233                         reg = <0x58781000 0x80>;
 234                         #address-cells = <1>;
 235                         #size-cells = <0>;
 236                         interrupts = <0 42 4>;
 237                         pinctrl-names = "default";
 238                         pinctrl-0 = <&pinctrl_i2c1>;
 239                         clocks = <&peri_clk 5>;
 240                         resets = <&peri_rst 5>;
 241                         clock-frequency = <100000>;
 242                 };
 243
 244                 i2c2: i2c@58782000 {
 245                         compatible = "socionext,uniphier-fi2c";
 246                         status = "disabled";
 247                         reg = <0x58782000 0x80>;
 248                         #address-cells = <1>;
 249                         #size-cells = <0>;
 250                         interrupts = <0 43 4>;
 251                         pinctrl-names = "default";
 252                         pinctrl-0 = <&pinctrl_i2c2>;
 253                         clocks = <&peri_clk 6>;
 254                         resets = <&peri_rst 6>;
 255                         clock-frequency = <100000>;
 256                 };
 257
 258                 i2c3: i2c@58783000 {
 259                         compatible = "socionext,uniphier-fi2c";
 260                         status = "disabled";
 261                         reg = <0x58783000 0x80>;
 262                         #address-cells = <1>;
 263                         #size-cells = <0>;
 264                         interrupts = <0 44 4>;
 265                         pinctrl-names = "default";
 266                         pinctrl-0 = <&pinctrl_i2c3>;
 267                         clocks = <&peri_clk 7>;
 268                         resets = <&peri_rst 7>;
 269                         clock-frequency = <100000>;
 270                 };
 271
 272                 /* chip-internal connection for HDMI */
 273                 i2c6: i2c@58786000 {
 274                         compatible = "socionext,uniphier-fi2c";
 275                         reg = <0x58786000 0x80>;
 276                         #address-cells = <1>;
 277                         #size-cells = <0>;
 278                         interrupts = <0 26 4>;
 279                         clocks = <&peri_clk 10>;
 280                         resets = <&peri_rst 10>;
 281                         clock-frequency = <400000>;
 282                 };
 283
 284                 system_bus: system-bus@58c00000 {
 285                         compatible = "socionext,uniphier-system-bus";
 286                         status = "disabled";
 287                         reg = <0x58c00000 0x400>;
 288                         #address-cells = <2>;
 289                         #size-cells = <1>;
 290                         pinctrl-names = "default";
 291                         pinctrl-0 = <&pinctrl_system_bus>;
 292                 };
 293
 294                 smpctrl@59801000 {
 295                         compatible = "socionext,uniphier-smpctrl";
 296                         reg = <0x59801000 0x400>;
 297                 };
 298
 299                 sdctrl@59810000 {
 300                         compatible = "socionext,uniphier-pxs3-sdctrl",
 301                                      "simple-mfd", "syscon";
 302                         reg = <0x59810000 0x400>;
 303
 304                         sd_clk: clock {
 305                                 compatible = "socionext,uniphier-pxs3-sd-clock";
 306                                 #clock-cells = <1>;
 307                         };
 308
 309                         sd_rst: reset {
 310                                 compatible = "socionext,uniphier-pxs3-sd-reset";
 311                                 #reset-cells = <1>;
 312                         };
 313                 };
 314
 315                 perictrl@59820000 {
 316                         compatible = "socionext,uniphier-pxs3-perictrl",
 317                                      "simple-mfd", "syscon";
 318                         reg = <0x59820000 0x200>;
 319
 320                         peri_clk: clock {
 321                                 compatible = "socionext,uniphier-pxs3-peri-clock";
 322                                 #clock-cells = <1>;
 323                         };
 324
 325                         peri_rst: reset {
 326                                 compatible = "socionext,uniphier-pxs3-peri-reset";
 327                                 #reset-cells = <1>;
 328                         };
 329                 };
 330
 331                 emmc: sdhc@5a000000 {
 332                         compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
 333                         reg = <0x5a000000 0x400>;
 334                         interrupts = <0 78 4>;
 335                         pinctrl-names = "default";
 336                         pinctrl-0 = <&pinctrl_emmc_1v8>;
 337                         clocks = <&sys_clk 4>;
 338                         resets = <&sys_rst 4>;
 339                         bus-width = <8>;
 340                         mmc-ddr-1_8v;
 341                         mmc-hs200-1_8v;
 342                         mmc-pwrseq = <&emmc_pwrseq>;
 343                         cdns,phy-input-delay-legacy = <4>;
 344                         cdns,phy-input-delay-mmc-highspeed = <2>;
 345                         cdns,phy-input-delay-mmc-ddr = <3>;
 346                         cdns,phy-dll-delay-sdclk = <21>;
 347                         cdns,phy-dll-delay-sdclk-hsmmc = <21>;
 348                 };
 349
 350                 sd: sdhc@5a400000 {
 351                         compatible = "socionext,uniphier-sdhc";
 352                         status = "disabled";
 353                         reg = <0x5a400000 0x800>;
 354                         interrupts = <0 76 4>;
 355                         pinctrl-names = "default";
 356                         pinctrl-0 = <&pinctrl_sd>;
 357                         clocks = <&sd_clk 0>;
 358                         reset-names = "host";
 359                         resets = <&sd_rst 0>;
 360                         bus-width = <4>;
 361                         cap-sd-highspeed;
 362                 };
 363
 364                 soc-glue@5f800000 {
 365                         compatible = "socionext,uniphier-pxs3-soc-glue",
 366                                      "simple-mfd", "syscon";
 367                         reg = <0x5f800000 0x2000>;
 368
 369                         pinctrl: pinctrl {
 370                                 compatible = "socionext,uniphier-pxs3-pinctrl";
 371                         };
 372                 };
 373
 374                 soc-glue@5f900000 {
 375                         compatible = "socionext,uniphier-pxs3-soc-glue-debug",
 376                                      "simple-mfd";
 377                         #address-cells = <1>;
 378                         #size-cells = <1>;
 379                         ranges = <0 0x5f900000 0x2000>;
 380
 381                         efuse@100 {
 382                                 compatible = "socionext,uniphier-efuse";
 383                                 reg = <0x100 0x28>;
 384                         };
 385
 386                         efuse@200 {
 387                                 compatible = "socionext,uniphier-efuse";
 388                                 reg = <0x200 0x68>;
 389                         };
 390                 };
 391
 392                 aidet: aidet@5fc20000 {
 393                         compatible = "socionext,uniphier-pxs3-aidet";
 394                         reg = <0x5fc20000 0x200>;
 395                         interrupt-controller;
 396                         #interrupt-cells = <2>;
 397                 };
 398
 399                 gic: interrupt-controller@5fe00000 {
 400                         compatible = "arm,gic-v3";
 401                         reg = <0x5fe00000 0x10000>,     /* GICD */
 402                               <0x5fe80000 0x80000>;     /* GICR */
 403                         interrupt-controller;
 404                         #interrupt-cells = <3>;
 405                         interrupts = <1 9 4>;
 406                 };
 407
 408                 sysctrl@61840000 {
 409                         compatible = "socionext,uniphier-pxs3-sysctrl",
 410                                      "simple-mfd", "syscon";
 411                         reg = <0x61840000 0x10000>;
 412
 413                         sys_clk: clock {
 414                                 compatible = "socionext,uniphier-pxs3-clock";
 415                                 #clock-cells = <1>;
 416                         };
 417
 418                         sys_rst: reset {
 419                                 compatible = "socionext,uniphier-pxs3-reset";
 420                                 #reset-cells = <1>;
 421                         };
 422
 423                         watchdog {
 424                                 compatible = "socionext,uniphier-wdt";
 425                         };
 426                 };
 427
 428                 usb0: usb@65b00000 {
 429                         compatible = "socionext,uniphier-pxs3-dwc3";
 430                         status = "disabled";
 431                         reg = <0x65b00000 0x1000>;
 432                         #address-cells = <1>;
 433                         #size-cells = <1>;
 434                         ranges;
 435                         pinctrl-names = "default";
 436                         pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
 437                         dwc3@65a00000 {
 438                                 compatible = "snps,dwc3";
 439                                 reg = <0x65a00000 0x10000>;
 440                                 interrupts = <0 134 4>;
 441                                 dr_mode = "host";
 442                                 tx-fifo-resize;
 443                         };
 444                 };
 445
 446                 usb1: usb@65d00000 {
 447                         compatible = "socionext,uniphier-pxs3-dwc3";
 448                         status = "disabled";
 449                         reg = <0x65d00000 0x1000>;
 450                         #address-cells = <1>;
 451                         #size-cells = <1>;
 452                         ranges;
 453                         pinctrl-names = "default";
 454                         pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
 455                         dwc3@65c00000 {
 456                                 compatible = "snps,dwc3";
 457                                 reg = <0x65c00000 0x10000>;
 458                                 interrupts = <0 137 4>;
 459                                 dr_mode = "host";
 460                                 tx-fifo-resize;
 461                         };
 462                 };
 463
 464                 nand: nand@68000000 {
 465                         compatible = "socionext,uniphier-denali-nand-v5b";
 466                         status = "disabled";
 467                         reg-names = "nand_data", "denali_reg";
 468                         reg = <0x68000000 0x20>, <0x68100000 0x1000>;
 469                         interrupts = <0 65 4>;
 470                         pinctrl-names = "default";
 471                         pinctrl-0 = <&pinctrl_nand>;
 472                         clocks = <&sys_clk 2>;
 473                         resets = <&sys_rst 2>;
 474                 };
 475         };
 476 };
 477
 478 #include "uniphier-pinctrl.dtsi"