arch/arm/dts/uniphier-pro5.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
   2 //
   3 // Device Tree Source for UniPhier Pro5 SoC
   4 //
   5 // Copyright (C) 2015-2016 Socionext Inc.
   6 //   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   7
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9
  10 / {
  11         compatible = "socionext,uniphier-pro5";
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu@0 {
  20                         device_type = "cpu";
  21                         compatible = "arm,cortex-a9";
  22                         reg = <0>;
  23                         clocks = <&sys_clk 32>;
  24                         enable-method = "psci";
  25                         next-level-cache = <&l2>;
  26                         operating-points-v2 = <&cpu_opp>;
  27                 };
  28
  29                 cpu@1 {
  30                         device_type = "cpu";
  31                         compatible = "arm,cortex-a9";
  32                         reg = <1>;
  33                         clocks = <&sys_clk 32>;
  34                         enable-method = "psci";
  35                         next-level-cache = <&l2>;
  36                         operating-points-v2 = <&cpu_opp>;
  37                 };
  38         };
  39
  40         cpu_opp: opp-table {
  41                 compatible = "operating-points-v2";
  42                 opp-shared;
  43
  44                 opp-100000000 {
  45                         opp-hz = /bits/ 64 <100000000>;
  46                         clock-latency-ns = <300>;
  47                 };
  48                 opp-116667000 {
  49                         opp-hz = /bits/ 64 <116667000>;
  50                         clock-latency-ns = <300>;
  51                 };
  52                 opp-150000000 {
  53                         opp-hz = /bits/ 64 <150000000>;
  54                         clock-latency-ns = <300>;
  55                 };
  56                 opp-175000000 {
  57                         opp-hz = /bits/ 64 <175000000>;
  58                         clock-latency-ns = <300>;
  59                 };
  60                 opp-200000000 {
  61                         opp-hz = /bits/ 64 <200000000>;
  62                         clock-latency-ns = <300>;
  63                 };
  64                 opp-233334000 {
  65                         opp-hz = /bits/ 64 <233334000>;
  66                         clock-latency-ns = <300>;
  67                 };
  68                 opp-300000000 {
  69                         opp-hz = /bits/ 64 <300000000>;
  70                         clock-latency-ns = <300>;
  71                 };
  72                 opp-350000000 {
  73                         opp-hz = /bits/ 64 <350000000>;
  74                         clock-latency-ns = <300>;
  75                 };
  76                 opp-400000000 {
  77                         opp-hz = /bits/ 64 <400000000>;
  78                         clock-latency-ns = <300>;
  79                 };
  80                 opp-466667000 {
  81                         opp-hz = /bits/ 64 <466667000>;
  82                         clock-latency-ns = <300>;
  83                 };
  84                 opp-600000000 {
  85                         opp-hz = /bits/ 64 <600000000>;
  86                         clock-latency-ns = <300>;
  87                 };
  88                 opp-700000000 {
  89                         opp-hz = /bits/ 64 <700000000>;
  90                         clock-latency-ns = <300>;
  91                 };
  92                 opp-800000000 {
  93                         opp-hz = /bits/ 64 <800000000>;
  94                         clock-latency-ns = <300>;
  95                 };
  96                 opp-933334000 {
  97                         opp-hz = /bits/ 64 <933334000>;
  98                         clock-latency-ns = <300>;
  99                 };
 100                 opp-1200000000 {
 101                         opp-hz = /bits/ 64 <1200000000>;
 102                         clock-latency-ns = <300>;
 103                 };
 104                 opp-1400000000 {
 105                         opp-hz = /bits/ 64 <1400000000>;
 106                         clock-latency-ns = <300>;
 107                 };
 108         };
 109
 110         psci {
 111                 compatible = "arm,psci-0.2";
 112                 method = "smc";
 113         };
 114
 115         clocks {
 116                 refclk: ref {
 117                         compatible = "fixed-clock";
 118                         #clock-cells = <0>;
 119                         clock-frequency = <20000000>;
 120                 };
 121
 122                 arm_timer_clk: arm-timer {
 123                         #clock-cells = <0>;
 124                         compatible = "fixed-clock";
 125                         clock-frequency = <50000000>;
 126                 };
 127         };
 128
 129         soc {
 130                 compatible = "simple-bus";
 131                 #address-cells = <1>;
 132                 #size-cells = <1>;
 133                 ranges;
 134                 interrupt-parent = <&intc>;
 135
 136                 l2: cache-controller@500c0000 {
 137                         compatible = "socionext,uniphier-system-cache";
 138                         reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
 139                               <0x506c0000 0x400>;
 140                         interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
 141                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
 142                         cache-unified;
 143                         cache-size = <(2 * 1024 * 1024)>;
 144                         cache-sets = <512>;
 145                         cache-line-size = <128>;
 146                         cache-level = <2>;
 147                         next-level-cache = <&l3>;
 148                 };
 149
 150                 l3: cache-controller@500c8000 {
 151                         compatible = "socionext,uniphier-system-cache";
 152                         reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
 153                               <0x506c8000 0x400>;
 154                         interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
 155                                      <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
 156                         cache-unified;
 157                         cache-size = <(2 * 1024 * 1024)>;
 158                         cache-sets = <512>;
 159                         cache-line-size = <256>;
 160                         cache-level = <3>;
 161                 };
 162
 163                 spi0: spi@54006000 {
 164                         compatible = "socionext,uniphier-scssi";
 165                         status = "disabled";
 166                         reg = <0x54006000 0x100>;
 167                         #address-cells = <1>;
 168                         #size-cells = <0>;
 169                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 170                         pinctrl-names = "default";
 171                         pinctrl-0 = <&pinctrl_spi0>;
 172                         clocks = <&peri_clk 11>;
 173                         resets = <&peri_rst 11>;
 174                 };
 175
 176                 spi1: spi@54006100 {
 177                         compatible = "socionext,uniphier-scssi";
 178                         status = "disabled";
 179                         reg = <0x54006100 0x100>;
 180                         #address-cells = <1>;
 181                         #size-cells = <0>;
 182                         interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
 183                         pinctrl-names = "default";
 184                         pinctrl-0 = <&pinctrl_spi1>;
 185                         clocks = <&peri_clk 11>;        /* common with spi0 */
 186                         resets = <&peri_rst 12>;
 187                 };
 188
 189                 serial0: serial@54006800 {
 190                         compatible = "socionext,uniphier-uart";
 191                         status = "disabled";
 192                         reg = <0x54006800 0x40>;
 193                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 194                         pinctrl-names = "default";
 195                         pinctrl-0 = <&pinctrl_uart0>;
 196                         clocks = <&peri_clk 0>;
 197                         resets = <&peri_rst 0>;
 198                 };
 199
 200                 serial1: serial@54006900 {
 201                         compatible = "socionext,uniphier-uart";
 202                         status = "disabled";
 203                         reg = <0x54006900 0x40>;
 204                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 205                         pinctrl-names = "default";
 206                         pinctrl-0 = <&pinctrl_uart1>;
 207                         clocks = <&peri_clk 1>;
 208                         resets = <&peri_rst 1>;
 209                 };
 210
 211                 serial2: serial@54006a00 {
 212                         compatible = "socionext,uniphier-uart";
 213                         status = "disabled";
 214                         reg = <0x54006a00 0x40>;
 215                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 216                         pinctrl-names = "default";
 217                         pinctrl-0 = <&pinctrl_uart2>;
 218                         clocks = <&peri_clk 2>;
 219                         resets = <&peri_rst 2>;
 220                 };
 221
 222                 serial3: serial@54006b00 {
 223                         compatible = "socionext,uniphier-uart";
 224                         status = "disabled";
 225                         reg = <0x54006b00 0x40>;
 226                         interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
 227                         pinctrl-names = "default";
 228                         pinctrl-0 = <&pinctrl_uart3>;
 229                         clocks = <&peri_clk 3>;
 230                         resets = <&peri_rst 3>;
 231                 };
 232
 233                 gpio: gpio@55000000 {
 234                         compatible = "socionext,uniphier-gpio";
 235                         reg = <0x55000000 0x200>;
 236                         interrupt-parent = <&aidet>;
 237                         interrupt-controller;
 238                         #interrupt-cells = <2>;
 239                         gpio-controller;
 240                         #gpio-cells = <2>;
 241                         gpio-ranges = <&pinctrl 0 0 0>;
 242                         gpio-ranges-group-names = "gpio_range";
 243                         ngpios = <248>;
 244                         socionext,interrupt-ranges = <0 48 16>, <16 154 5>;
 245                 };
 246
 247                 i2c0: i2c@58780000 {
 248                         compatible = "socionext,uniphier-fi2c";
 249                         status = "disabled";
 250                         reg = <0x58780000 0x80>;
 251                         #address-cells = <1>;
 252                         #size-cells = <0>;
 253                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 254                         pinctrl-names = "default";
 255                         pinctrl-0 = <&pinctrl_i2c0>;
 256                         clocks = <&peri_clk 4>;
 257                         resets = <&peri_rst 4>;
 258                         clock-frequency = <100000>;
 259                 };
 260
 261                 i2c1: i2c@58781000 {
 262                         compatible = "socionext,uniphier-fi2c";
 263                         status = "disabled";
 264                         reg = <0x58781000 0x80>;
 265                         #address-cells = <1>;
 266                         #size-cells = <0>;
 267                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 268                         pinctrl-names = "default";
 269                         pinctrl-0 = <&pinctrl_i2c1>;
 270                         clocks = <&peri_clk 5>;
 271                         resets = <&peri_rst 5>;
 272                         clock-frequency = <100000>;
 273                 };
 274
 275                 i2c2: i2c@58782000 {
 276                         compatible = "socionext,uniphier-fi2c";
 277                         status = "disabled";
 278                         reg = <0x58782000 0x80>;
 279                         #address-cells = <1>;
 280                         #size-cells = <0>;
 281                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 282                         pinctrl-names = "default";
 283                         pinctrl-0 = <&pinctrl_i2c2>;
 284                         clocks = <&peri_clk 6>;
 285                         resets = <&peri_rst 6>;
 286                         clock-frequency = <100000>;
 287                 };
 288
 289                 i2c3: i2c@58783000 {
 290                         compatible = "socionext,uniphier-fi2c";
 291                         status = "disabled";
 292                         reg = <0x58783000 0x80>;
 293                         #address-cells = <1>;
 294                         #size-cells = <0>;
 295                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 296                         pinctrl-names = "default";
 297                         pinctrl-0 = <&pinctrl_i2c3>;
 298                         clocks = <&peri_clk 7>;
 299                         resets = <&peri_rst 7>;
 300                         clock-frequency = <100000>;
 301                 };
 302
 303                 /* i2c4 does not exist */
 304
 305                 /* chip-internal connection for DMD */
 306                 i2c5: i2c@58785000 {
 307                         compatible = "socionext,uniphier-fi2c";
 308                         reg = <0x58785000 0x80>;
 309                         #address-cells = <1>;
 310                         #size-cells = <0>;
 311                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 312                         clocks = <&peri_clk 9>;
 313                         resets = <&peri_rst 9>;
 314                         clock-frequency = <400000>;
 315                 };
 316
 317                 /* chip-internal connection for HDMI */
 318                 i2c6: i2c@58786000 {
 319                         compatible = "socionext,uniphier-fi2c";
 320                         reg = <0x58786000 0x80>;
 321                         #address-cells = <1>;
 322                         #size-cells = <0>;
 323                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 324                         clocks = <&peri_clk 10>;
 325                         resets = <&peri_rst 10>;
 326                         clock-frequency = <400000>;
 327                 };
 328
 329                 system_bus: system-bus@58c00000 {
 330                         compatible = "socionext,uniphier-system-bus";
 331                         status = "disabled";
 332                         reg = <0x58c00000 0x400>;
 333                         #address-cells = <2>;
 334                         #size-cells = <1>;
 335                         pinctrl-names = "default";
 336                         pinctrl-0 = <&pinctrl_system_bus>;
 337                 };
 338
 339                 smpctrl@59801000 {
 340                         compatible = "socionext,uniphier-smpctrl";
 341                         reg = <0x59801000 0x400>;
 342                 };
 343
 344                 sdctrl: syscon@59810000 {
 345                         compatible = "socionext,uniphier-pro5-sdctrl",
 346                                      "simple-mfd", "syscon";
 347                         reg = <0x59810000 0x400>;
 348
 349                         sd_clk: clock-controller {
 350                                 compatible = "socionext,uniphier-pro5-sd-clock";
 351                                 #clock-cells = <1>;
 352                         };
 353
 354                         sd_rst: reset-controller {
 355                                 compatible = "socionext,uniphier-pro5-sd-reset";
 356                                 #reset-cells = <1>;
 357                         };
 358                 };
 359
 360                 syscon@59820000 {
 361                         compatible = "socionext,uniphier-pro5-perictrl",
 362                                      "simple-mfd", "syscon";
 363                         reg = <0x59820000 0x200>;
 364
 365                         peri_clk: clock-controller {
 366                                 compatible = "socionext,uniphier-pro5-peri-clock";
 367                                 #clock-cells = <1>;
 368                         };
 369
 370                         peri_rst: reset-controller {
 371                                 compatible = "socionext,uniphier-pro5-peri-reset";
 372                                 #reset-cells = <1>;
 373                         };
 374                 };
 375
 376                 syscon@5f800000 {
 377                         compatible = "socionext,uniphier-pro5-soc-glue",
 378                                      "simple-mfd", "syscon";
 379                         reg = <0x5f800000 0x2000>;
 380
 381                         pinctrl: pinctrl {
 382                                 compatible = "socionext,uniphier-pro5-pinctrl";
 383                         };
 384                 };
 385
 386                 syscon@5f900000 {
 387                         compatible = "socionext,uniphier-pro5-soc-glue-debug",
 388                                      "simple-mfd", "syscon";
 389                         reg = <0x5f900000 0x2000>;
 390                         #address-cells = <1>;
 391                         #size-cells = <1>;
 392                         ranges = <0 0x5f900000 0x2000>;
 393
 394                         efuse@100 {
 395                                 compatible = "socionext,uniphier-efuse";
 396                                 reg = <0x100 0x28>;
 397                         };
 398
 399                         efuse@130 {
 400                                 compatible = "socionext,uniphier-efuse";
 401                                 reg = <0x130 0x8>;
 402                         };
 403
 404                         efuse@200 {
 405                                 compatible = "socionext,uniphier-efuse";
 406                                 reg = <0x200 0x28>;
 407                         };
 408
 409                         efuse@300 {
 410                                 compatible = "socionext,uniphier-efuse";
 411                                 reg = <0x300 0x14>;
 412                         };
 413
 414                         efuse@400 {
 415                                 compatible = "socionext,uniphier-efuse";
 416                                 reg = <0x400 0x8>;
 417                         };
 418                 };
 419
 420                 xdmac: dma-controller@5fc10000 {
 421                         compatible = "socionext,uniphier-xdmac";
 422                         reg = <0x5fc10000 0x5300>;
 423                         interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
 424                         dma-channels = <16>;
 425                         #dma-cells = <2>;
 426                 };
 427
 428                 aidet: interrupt-controller@5fc20000 {
 429                         compatible = "socionext,uniphier-pro5-aidet";
 430                         reg = <0x5fc20000 0x200>;
 431                         interrupt-controller;
 432                         #interrupt-cells = <2>;
 433                 };
 434
 435                 timer@60000200 {
 436                         compatible = "arm,cortex-a9-global-timer";
 437                         reg = <0x60000200 0x20>;
 438                         interrupts = <GIC_PPI 11
 439                                 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
 440                         clocks = <&arm_timer_clk>;
 441                 };
 442
 443                 timer@60000600 {
 444                         compatible = "arm,cortex-a9-twd-timer";
 445                         reg = <0x60000600 0x20>;
 446                         interrupts = <GIC_PPI 13
 447                                 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
 448                         clocks = <&arm_timer_clk>;
 449                 };
 450
 451                 intc: interrupt-controller@60001000 {
 452                         compatible = "arm,cortex-a9-gic";
 453                         reg = <0x60001000 0x1000>,
 454                               <0x60000100 0x100>;
 455                         #interrupt-cells = <3>;
 456                         interrupt-controller;
 457                 };
 458
 459                 syscon@61840000 {
 460                         compatible = "socionext,uniphier-pro5-sysctrl",
 461                                      "simple-mfd", "syscon";
 462                         reg = <0x61840000 0x10000>;
 463
 464                         sys_clk: clock-controller {
 465                                 compatible = "socionext,uniphier-pro5-clock";
 466                                 #clock-cells = <1>;
 467                         };
 468
 469                         sys_rst: reset-controller {
 470                                 compatible = "socionext,uniphier-pro5-reset";
 471                                 #reset-cells = <1>;
 472                         };
 473                 };
 474
 475                 usb0: usb@65a00000 {
 476                         compatible = "socionext,uniphier-dwc3", "snps,dwc3";
 477                         status = "disabled";
 478                         reg = <0x65a00000 0xcd00>;
 479                         interrupt-names = "host";
 480                         interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 481                         pinctrl-names = "default";
 482                         pinctrl-0 = <&pinctrl_usb0>;
 483                         clock-names = "ref", "bus_early", "suspend";
 484                         clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
 485                         resets = <&usb0_rst 15>;
 486                         phys = <&usb0_hsphy0>, <&usb0_ssphy0>;
 487                         dr_mode = "host";
 488                 };
 489
 490                 usb-controller@65b00000 {
 491                         compatible = "socionext,uniphier-pro5-dwc3-glue",
 492                                      "simple-mfd";
 493                         reg = <0x65b00000 0x400>;
 494                         #address-cells = <1>;
 495                         #size-cells = <1>;
 496                         ranges = <0 0x65b00000 0x400>;
 497
 498                         usb0_rst: reset-controller@0 {
 499                                 compatible = "socionext,uniphier-pro5-usb3-reset";
 500                                 reg = <0x0 0x4>;
 501                                 #reset-cells = <1>;
 502                                 clock-names = "gio", "link";
 503                                 clocks = <&sys_clk 12>, <&sys_clk 14>;
 504                                 reset-names = "gio", "link";
 505                                 resets = <&sys_rst 12>, <&sys_rst 14>;
 506                         };
 507
 508                         usb0_vbus0: regulator@100 {
 509                                 compatible = "socionext,uniphier-pro5-usb3-regulator";
 510                                 reg = <0x100 0x10>;
 511                                 clock-names = "gio", "link";
 512                                 clocks = <&sys_clk 12>, <&sys_clk 14>;
 513                                 reset-names = "gio", "link";
 514                                 resets = <&sys_rst 12>, <&sys_rst 14>;
 515                         };
 516
 517                         usb0_hsphy0: phy@280 {
 518                                 compatible = "socionext,uniphier-pro5-usb3-hsphy";
 519                                 reg = <0x280 0x10>;
 520                                 #phy-cells = <0>;
 521                                 clock-names = "gio", "link";
 522                                 clocks = <&sys_clk 12>, <&sys_clk 14>;
 523                                 reset-names = "gio", "link";
 524                                 resets = <&sys_rst 12>, <&sys_rst 14>;
 525                                 vbus-supply = <&usb0_vbus0>;
 526                         };
 527
 528                         usb0_ssphy0: phy@380 {
 529                                 compatible = "socionext,uniphier-pro5-usb3-ssphy";
 530                                 reg = <0x380 0x10>;
 531                                 #phy-cells = <0>;
 532                                 clock-names = "gio", "link";
 533                                 clocks = <&sys_clk 12>, <&sys_clk 14>;
 534                                 reset-names = "gio", "link";
 535                                 resets = <&sys_rst 12>, <&sys_rst 14>;
 536                                 vbus-supply = <&usb0_vbus0>;
 537                         };
 538                 };
 539
 540                 usb1: usb@65c00000 {
 541                         compatible = "socionext,uniphier-dwc3", "snps,dwc3";
 542                         status = "disabled";
 543                         reg = <0x65c00000 0xcd00>;
 544                         interrupt-names = "host";
 545                         interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
 546                         pinctrl-names = "default";
 547                         pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
 548                         clock-names = "ref", "bus_early", "suspend";
 549                         clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
 550                         resets = <&usb1_rst 15>;
 551                         phys = <&usb1_hsphy0>, <&usb1_hsphy1>, <&usb1_ssphy0>;
 552                         dr_mode = "host";
 553                 };
 554
 555                 usb-controller@65d00000 {
 556                         compatible = "socionext,uniphier-pro5-dwc3-glue",
 557                                      "simple-mfd";
 558                         reg = <0x65d00000 0x400>;
 559                         #address-cells = <1>;
 560                         #size-cells = <1>;
 561                         ranges = <0 0x65d00000 0x400>;
 562
 563                         usb1_rst: reset-controller@0 {
 564                                 compatible = "socionext,uniphier-pro5-usb3-reset";
 565                                 reg = <0x0 0x4>;
 566                                 #reset-cells = <1>;
 567                                 clock-names = "gio", "link";
 568                                 clocks = <&sys_clk 12>, <&sys_clk 15>;
 569                                 reset-names = "gio", "link";
 570                                 resets = <&sys_rst 12>, <&sys_rst 15>;
 571                         };
 572
 573                         usb1_vbus0: regulator@100 {
 574                                 compatible = "socionext,uniphier-pro5-usb3-regulator";
 575                                 reg = <0x100 0x10>;
 576                                 clock-names = "gio", "link";
 577                                 clocks = <&sys_clk 12>, <&sys_clk 15>;
 578                                 reset-names = "gio", "link";
 579                                 resets = <&sys_rst 12>, <&sys_rst 15>;
 580                         };
 581
 582                         usb1_vbus1: regulator@110 {
 583                                 compatible = "socionext,uniphier-pro5-usb3-regulator";
 584                                 reg = <0x110 0x10>;
 585                                 clock-names = "gio", "link";
 586                                 clocks = <&sys_clk 12>, <&sys_clk 15>;
 587                                 reset-names = "gio", "link";
 588                                 resets = <&sys_rst 12>, <&sys_rst 15>;
 589                         };
 590
 591                         usb1_hsphy0: phy@280 {
 592                                 compatible = "socionext,uniphier-pro5-usb3-hsphy";
 593                                 reg = <0x280 0x10>;
 594                                 #phy-cells = <0>;
 595                                 clock-names = "gio", "link";
 596                                 clocks = <&sys_clk 12>, <&sys_clk 15>;
 597                                 reset-names = "gio", "link";
 598                                 resets = <&sys_rst 12>, <&sys_rst 15>;
 599                                 vbus-supply = <&usb1_vbus0>;
 600                         };
 601
 602                         usb1_hsphy1: phy@290 {
 603                                 compatible = "socionext,uniphier-pro5-usb3-hsphy";
 604                                 reg = <0x290 0x10>;
 605                                 #phy-cells = <0>;
 606                                 clock-names = "gio", "link";
 607                                 clocks = <&sys_clk 12>, <&sys_clk 15>;
 608                                 reset-names = "gio", "link";
 609                                 resets = <&sys_rst 12>, <&sys_rst 15>;
 610                                 vbus-supply = <&usb1_vbus1>;
 611                         };
 612
 613                         usb1_ssphy0: phy@380 {
 614                                 compatible = "socionext,uniphier-pro5-usb3-ssphy";
 615                                 reg = <0x380 0x10>;
 616                                 #phy-cells = <0>;
 617                                 clock-names = "gio", "link";
 618                                 clocks = <&sys_clk 12>, <&sys_clk 15>;
 619                                 reset-names = "gio", "link";
 620                                 resets = <&sys_rst 12>, <&sys_rst 15>;
 621                                 vbus-supply = <&usb1_vbus0>;
 622                         };
 623                 };
 624
 625                 pcie_ep: pcie-ep@66000000 {
 626                         compatible = "socionext,uniphier-pro5-pcie-ep";
 627                         status = "disabled";
 628                         reg-names = "dbi", "dbi2", "link", "addr_space";
 629                         reg = <0x66000000 0x1000>, <0x66001000 0x1000>,
 630                               <0x66010000 0x10000>, <0x67000000 0x400000>;
 631                         pinctrl-names = "default";
 632                         pinctrl-0 = <&pinctrl_pcie>;
 633                         clock-names = "gio", "link";
 634                         clocks = <&sys_clk 12>, <&sys_clk 24>;
 635                         reset-names = "gio", "link";
 636                         resets = <&sys_rst 12>, <&sys_rst 24>;
 637                         num-ib-windows = <16>;
 638                         num-ob-windows = <16>;
 639                         num-lanes = <4>;
 640                         phy-names = "pcie-phy";
 641                         phys = <&pcie_phy>;
 642                 };
 643
 644                 pcie_phy: phy@66038000 {
 645                         compatible = "socionext,uniphier-pro5-pcie-phy";
 646                         reg = <0x66038000 0x4000>;
 647                         #phy-cells = <0>;
 648                         clock-names = "gio", "link";
 649                         clocks = <&sys_clk 12>, <&sys_clk 24>;
 650                         reset-names = "gio", "link";
 651                         resets = <&sys_rst 12>, <&sys_rst 24>;
 652                 };
 653
 654                 nand: nand-controller@68000000 {
 655                         compatible = "socionext,uniphier-denali-nand-v5b";
 656                         status = "disabled";
 657                         reg-names = "nand_data", "denali_reg";
 658                         reg = <0x68000000 0x20>, <0x68100000 0x1000>;
 659                         #address-cells = <1>;
 660                         #size-cells = <0>;
 661                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 662                         pinctrl-names = "default";
 663                         pinctrl-0 = <&pinctrl_nand2cs>;
 664                         clock-names = "nand", "nand_x", "ecc";
 665                         clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
 666                         reset-names = "nand", "reg";
 667                         resets = <&sys_rst 2>, <&sys_rst 2>;
 668                 };
 669
 670                 emmc: mmc@68400000 {
 671                         compatible = "socionext,uniphier-sd-v3.1";
 672                         status = "disabled";
 673                         reg = <0x68400000 0x800>;
 674                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 675                         pinctrl-names = "default";
 676                         pinctrl-0 = <&pinctrl_emmc>;
 677                         clocks = <&sd_clk 1>;
 678                         reset-names = "host", "hw";
 679                         resets = <&sd_rst 1>, <&sd_rst 6>;
 680                         bus-width = <8>;
 681                         cap-mmc-highspeed;
 682                         cap-mmc-hw-reset;
 683                         non-removable;
 684                 };
 685
 686                 sd: mmc@68800000 {
 687                         compatible = "socionext,uniphier-sd-v3.1";
 688                         status = "disabled";
 689                         reg = <0x68800000 0x800>;
 690                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 691                         pinctrl-names = "default", "uhs";
 692                         pinctrl-0 = <&pinctrl_sd>;
 693                         pinctrl-1 = <&pinctrl_sd_uhs>;
 694                         clocks = <&sd_clk 0>;
 695                         reset-names = "host";
 696                         resets = <&sd_rst 0>;
 697                         bus-width = <4>;
 698                         cap-sd-highspeed;
 699                         sd-uhs-sdr12;
 700                         sd-uhs-sdr25;
 701                         sd-uhs-sdr50;
 702                         socionext,syscon-uhs-mode = <&sdctrl 0>;
 703                 };
 704         };
 705 };
 706
 707 #include "uniphier-pinctrl.dtsi"