2 * Device Tree Source for UniPhier PH1-sLD3 SoC
4 * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
6 * SPDX-License-Identifier: GPL-2.0+ X11
9 /include/ "skeleton.dtsi"
12 compatible = "socionext,ph1-sld3";
17 enable-method = "socionext,uniphier-smp";
21 compatible = "arm,cortex-a9";
27 compatible = "arm,cortex-a9";
35 compatible = "fixed-clock";
36 clock-frequency = <24576000>;
39 arm_timer_clk: arm_timer_clk {
41 compatible = "fixed-clock";
42 clock-frequency = <50000000>;
47 compatible = "fixed-clock";
48 clock-frequency = <36864000>;
51 iobus_clk: iobus_clk {
53 compatible = "fixed-clock";
54 clock-frequency = <100000000>;
59 compatible = "simple-bus";
63 interrupt-parent = <&intc>;
67 compatible = "arm,cortex-a9-global-timer";
68 reg = <0x20000200 0x20>;
69 interrupts = <1 11 0x304>;
70 clocks = <&arm_timer_clk>;
74 compatible = "arm,cortex-a9-twd-timer";
75 reg = <0x20000600 0x20>;
76 interrupts = <1 13 0x304>;
77 clocks = <&arm_timer_clk>;
80 intc: interrupt-controller@20001000 {
81 compatible = "arm,cortex-a9-gic";
82 #interrupt-cells = <3>;
84 reg = <0x20001000 0x1000>,
88 serial0: serial@54006800 {
89 compatible = "socionext,uniphier-uart";
91 reg = <0x54006800 0x40>;
92 interrupts = <0 33 4>;
93 pinctrl-names = "default";
94 pinctrl-0 = <&pinctrl_uart0>;
96 clock-frequency = <36864000>;
99 serial1: serial@54006900 {
100 compatible = "socionext,uniphier-uart";
102 reg = <0x54006900 0x40>;
103 interrupts = <0 35 4>;
104 pinctrl-names = "default";
105 pinctrl-0 = <&pinctrl_uart1>;
106 clocks = <&uart_clk>;
107 clock-frequency = <36864000>;
110 serial2: serial@54006a00 {
111 compatible = "socionext,uniphier-uart";
113 reg = <0x54006a00 0x40>;
114 interrupts = <0 37 4>;
115 pinctrl-names = "default";
116 pinctrl-0 = <&pinctrl_uart2>;
117 clocks = <&uart_clk>;
118 clock-frequency = <36864000>;
121 port0x: gpio@55000008 {
122 compatible = "socionext,uniphier-gpio";
123 reg = <0x55000008 0x8>;
128 port1x: gpio@55000010 {
129 compatible = "socionext,uniphier-gpio";
130 reg = <0x55000010 0x8>;
135 port2x: gpio@55000018 {
136 compatible = "socionext,uniphier-gpio";
137 reg = <0x55000018 0x8>;
142 port3x: gpio@55000020 {
143 compatible = "socionext,uniphier-gpio";
144 reg = <0x55000020 0x8>;
149 port4: gpio@55000028 {
150 compatible = "socionext,uniphier-gpio";
151 reg = <0x55000028 0x8>;
156 port5x: gpio@55000030 {
157 compatible = "socionext,uniphier-gpio";
158 reg = <0x55000030 0x8>;
163 port6x: gpio@55000038 {
164 compatible = "socionext,uniphier-gpio";
165 reg = <0x55000038 0x8>;
170 port7x: gpio@55000040 {
171 compatible = "socionext,uniphier-gpio";
172 reg = <0x55000040 0x8>;
177 port8x: gpio@55000048 {
178 compatible = "socionext,uniphier-gpio";
179 reg = <0x55000048 0x8>;
184 port9x: gpio@55000050 {
185 compatible = "socionext,uniphier-gpio";
186 reg = <0x55000050 0x8>;
191 port10x: gpio@55000058 {
192 compatible = "socionext,uniphier-gpio";
193 reg = <0x55000058 0x8>;
198 port11x: gpio@55000060 {
199 compatible = "socionext,uniphier-gpio";
200 reg = <0x55000060 0x8>;
205 port12x: gpio@55000068 {
206 compatible = "socionext,uniphier-gpio";
207 reg = <0x55000068 0x8>;
212 port13x: gpio@55000070 {
213 compatible = "socionext,uniphier-gpio";
214 reg = <0x55000070 0x8>;
219 port14x: gpio@55000078 {
220 compatible = "socionext,uniphier-gpio";
221 reg = <0x55000078 0x8>;
226 port16x: gpio@55000088 {
227 compatible = "socionext,uniphier-gpio";
228 reg = <0x55000088 0x8>;
234 compatible = "socionext,uniphier-i2c";
236 reg = <0x58400000 0x40>;
237 #address-cells = <1>;
239 interrupts = <0 41 1>;
240 pinctrl-names = "default";
241 pinctrl-0 = <&pinctrl_i2c0>;
242 clocks = <&iobus_clk>;
243 clock-frequency = <100000>;
247 compatible = "socionext,uniphier-i2c";
249 reg = <0x58480000 0x40>;
250 #address-cells = <1>;
252 interrupts = <0 42 1>;
253 clocks = <&iobus_clk>;
254 clock-frequency = <100000>;
258 compatible = "socionext,uniphier-i2c";
260 reg = <0x58500000 0x40>;
261 #address-cells = <1>;
263 interrupts = <0 43 1>;
264 clocks = <&iobus_clk>;
265 clock-frequency = <100000>;
269 compatible = "socionext,uniphier-i2c";
271 reg = <0x58580000 0x40>;
272 #address-cells = <1>;
274 interrupts = <0 44 1>;
275 clocks = <&iobus_clk>;
276 clock-frequency = <100000>;
279 /* chip-internal connection for DMD */
281 compatible = "socionext,uniphier-i2c";
282 reg = <0x58600000 0x40>;
283 #address-cells = <1>;
285 interrupts = <0 45 1>;
286 clocks = <&iobus_clk>;
287 clock-frequency = <400000>;
290 system_bus: system-bus@58c00000 {
291 compatible = "socionext,uniphier-system-bus";
292 reg = <0x58c00000 0x400>;
293 #address-cells = <2>;
298 compatible = "socionext,uniphier-smpctrl";
299 reg = <0x59801000 0x400>;
302 mio: mioctrl@59810000 {
303 compatible = "socionext,ph1-sld3-mioctrl";
304 reg = <0x59810000 0x800>;
306 clock-names = "stdmac", "ehci";
307 clocks = <&sysctrl 10>, <&sysctrl 18>;
310 emmc: sdhc@5a400000 {
311 compatible = "socionext,uniphier-sdhc";
313 reg = <0x5a400000 0x200>;
314 interrupts = <0 78 4>;
315 pinctrl-names = "default", "1.8v";
316 pinctrl-0 = <&pinctrl_emmc>;
317 pinctrl-1 = <&pinctrl_emmc_1v8>;
324 compatible = "socionext,uniphier-sdhc";
326 reg = <0x5a500000 0x200>;
327 interrupts = <0 76 4>;
328 pinctrl-names = "default", "1.8v";
329 pinctrl-0 = <&pinctrl_sd>;
330 pinctrl-1 = <&pinctrl_sd_1v8>;
336 compatible = "socionext,uniphier-ehci", "generic-ehci";
338 reg = <0x5a800100 0x100>;
339 interrupts = <0 80 4>;
340 pinctrl-names = "default";
341 pinctrl-0 = <&pinctrl_usb0>;
342 clocks = <&mio 3>, <&mio 6>;
346 compatible = "socionext,uniphier-ehci", "generic-ehci";
348 reg = <0x5a810100 0x100>;
349 interrupts = <0 81 4>;
350 pinctrl-names = "default";
351 pinctrl-0 = <&pinctrl_usb1>;
352 clocks = <&mio 4>, <&mio 6>;
356 compatible = "socionext,uniphier-ehci", "generic-ehci";
358 reg = <0x5a820100 0x100>;
359 interrupts = <0 82 4>;
360 pinctrl-names = "default";
361 pinctrl-0 = <&pinctrl_usb2>;
362 clocks = <&mio 5>, <&mio 6>;
366 compatible = "socionext,uniphier-ehci", "generic-ehci";
368 reg = <0x5a830100 0x100>;
369 interrupts = <0 83 4>;
370 pinctrl-names = "default";
371 pinctrl-0 = <&pinctrl_usb3>;
372 clocks = <&mio 7>, <&mio 6>;
376 compatible = "simple-mfd", "syscon";
377 reg = <0x5f800000 0x2000>;
381 compatible = "socionext,uniphier-sld3-pinctrl";
387 compatible = "simple-mfd", "syscon";
388 reg = <0xf1830000 0x200>;
391 sysctrl: sysctrl@f1840000 {
392 compatible = "socionext,ph1-sld3-sysctrl";
393 reg = <0xf1840000 0x4000>;
399 nand: nand@f8000000 {
400 compatible = "denali,denali-nand-dt";
401 reg = <0xf8000000 0x20>, <0xf8100000 0x1000>;
402 reg-names = "nand_data", "denali_reg";
407 /include/ "uniphier-pinctrl.dtsi"