arch/arm/dts/uniphier-ld20.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
   2 //
   3 // Device Tree Source for UniPhier LD20 SoC
   4 //
   5 // Copyright (C) 2015-2016 Socionext Inc.
   6 //   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   7
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/gpio/uniphier-gpio.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/thermal/thermal.h>
  12
  13 / {
  14         compatible = "socionext,uniphier-ld20";
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17         interrupt-parent = <&gic>;
  18
  19         cpus {
  20                 #address-cells = <2>;
  21                 #size-cells = <0>;
  22
  23                 cpu-map {
  24                         cluster0 {
  25                                 core0 {
  26                                         cpu = <&cpu0>;
  27                                 };
  28                                 core1 {
  29                                         cpu = <&cpu1>;
  30                                 };
  31                         };
  32
  33                         cluster1 {
  34                                 core0 {
  35                                         cpu = <&cpu2>;
  36                                 };
  37                                 core1 {
  38                                         cpu = <&cpu3>;
  39                                 };
  40                         };
  41                 };
  42
  43                 cpu0: cpu@0 {
  44                         device_type = "cpu";
  45                         compatible = "arm,cortex-a72";
  46                         reg = <0 0x000>;
  47                         clocks = <&sys_clk 32>;
  48                         enable-method = "psci";
  49                         next-level-cache = <&a72_l2>;
  50                         operating-points-v2 = <&cluster0_opp>;
  51                         #cooling-cells = <2>;
  52                 };
  53
  54                 cpu1: cpu@1 {
  55                         device_type = "cpu";
  56                         compatible = "arm,cortex-a72";
  57                         reg = <0 0x001>;
  58                         clocks = <&sys_clk 32>;
  59                         enable-method = "psci";
  60                         next-level-cache = <&a72_l2>;
  61                         operating-points-v2 = <&cluster0_opp>;
  62                         #cooling-cells = <2>;
  63                 };
  64
  65                 cpu2: cpu@100 {
  66                         device_type = "cpu";
  67                         compatible = "arm,cortex-a53";
  68                         reg = <0 0x100>;
  69                         clocks = <&sys_clk 33>;
  70                         enable-method = "psci";
  71                         next-level-cache = <&a53_l2>;
  72                         operating-points-v2 = <&cluster1_opp>;
  73                         #cooling-cells = <2>;
  74                 };
  75
  76                 cpu3: cpu@101 {
  77                         device_type = "cpu";
  78                         compatible = "arm,cortex-a53";
  79                         reg = <0 0x101>;
  80                         clocks = <&sys_clk 33>;
  81                         enable-method = "psci";
  82                         next-level-cache = <&a53_l2>;
  83                         operating-points-v2 = <&cluster1_opp>;
  84                         #cooling-cells = <2>;
  85                 };
  86
  87                 a72_l2: l2-cache0 {
  88                         compatible = "cache";
  89                 };
  90
  91                 a53_l2: l2-cache1 {
  92                         compatible = "cache";
  93                 };
  94         };
  95
  96         cluster0_opp: opp-table-0 {
  97                 compatible = "operating-points-v2";
  98                 opp-shared;
  99
 100                 opp-250000000 {
 101                         opp-hz = /bits/ 64 <250000000>;
 102                         clock-latency-ns = <300>;
 103                 };
 104                 opp-275000000 {
 105                         opp-hz = /bits/ 64 <275000000>;
 106                         clock-latency-ns = <300>;
 107                 };
 108                 opp-500000000 {
 109                         opp-hz = /bits/ 64 <500000000>;
 110                         clock-latency-ns = <300>;
 111                 };
 112                 opp-550000000 {
 113                         opp-hz = /bits/ 64 <550000000>;
 114                         clock-latency-ns = <300>;
 115                 };
 116                 opp-666667000 {
 117                         opp-hz = /bits/ 64 <666667000>;
 118                         clock-latency-ns = <300>;
 119                 };
 120                 opp-733334000 {
 121                         opp-hz = /bits/ 64 <733334000>;
 122                         clock-latency-ns = <300>;
 123                 };
 124                 opp-1000000000 {
 125                         opp-hz = /bits/ 64 <1000000000>;
 126                         clock-latency-ns = <300>;
 127                 };
 128                 opp-1100000000 {
 129                         opp-hz = /bits/ 64 <1100000000>;
 130                         clock-latency-ns = <300>;
 131                 };
 132         };
 133
 134         cluster1_opp: opp-table-1 {
 135                 compatible = "operating-points-v2";
 136                 opp-shared;
 137
 138                 opp-250000000 {
 139                         opp-hz = /bits/ 64 <250000000>;
 140                         clock-latency-ns = <300>;
 141                 };
 142                 opp-275000000 {
 143                         opp-hz = /bits/ 64 <275000000>;
 144                         clock-latency-ns = <300>;
 145                 };
 146                 opp-500000000 {
 147                         opp-hz = /bits/ 64 <500000000>;
 148                         clock-latency-ns = <300>;
 149                 };
 150                 opp-550000000 {
 151                         opp-hz = /bits/ 64 <550000000>;
 152                         clock-latency-ns = <300>;
 153                 };
 154                 opp-666667000 {
 155                         opp-hz = /bits/ 64 <666667000>;
 156                         clock-latency-ns = <300>;
 157                 };
 158                 opp-733334000 {
 159                         opp-hz = /bits/ 64 <733334000>;
 160                         clock-latency-ns = <300>;
 161                 };
 162                 opp-1000000000 {
 163                         opp-hz = /bits/ 64 <1000000000>;
 164                         clock-latency-ns = <300>;
 165                 };
 166                 opp-1100000000 {
 167                         opp-hz = /bits/ 64 <1100000000>;
 168                         clock-latency-ns = <300>;
 169                 };
 170         };
 171
 172         psci {
 173                 compatible = "arm,psci-1.0";
 174                 method = "smc";
 175         };
 176
 177         clocks {
 178                 refclk: ref {
 179                         compatible = "fixed-clock";
 180                         #clock-cells = <0>;
 181                         clock-frequency = <25000000>;
 182                 };
 183         };
 184
 185         emmc_pwrseq: emmc-pwrseq {
 186                 compatible = "mmc-pwrseq-emmc";
 187                 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>;
 188         };
 189
 190         timer {
 191                 compatible = "arm,armv8-timer";
 192                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
 193                              <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
 194                              <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
 195                              <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
 196         };
 197
 198         thermal-zones {
 199                 cpu-thermal {
 200                         polling-delay-passive = <250>;  /* 250ms */
 201                         polling-delay = <1000>;         /* 1000ms */
 202                         thermal-sensors = <&pvtctl>;
 203
 204                         trips {
 205                                 cpu_crit: cpu-crit {
 206                                         temperature = <110000>; /* 110C */
 207                                         hysteresis = <2000>;
 208                                         type = "critical";
 209                                 };
 210                                 cpu_alert: cpu-alert {
 211                                         temperature = <100000>; /* 100C */
 212                                         hysteresis = <2000>;
 213                                         type = "passive";
 214                                 };
 215                         };
 216
 217                         cooling-maps {
 218                                 map0 {
 219                                         trip = <&cpu_alert>;
 220                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 221                                                          <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 222                                                          <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 223                                                          <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 224                                 };
 225                         };
 226                 };
 227         };
 228
 229         reserved-memory {
 230                 #address-cells = <2>;
 231                 #size-cells = <2>;
 232                 ranges;
 233
 234                 secure-memory@81000000 {
 235                         reg = <0x0 0x81000000 0x0 0x01000000>;
 236                         no-map;
 237                 };
 238         };
 239
 240         soc@0 {
 241                 compatible = "simple-bus";
 242                 #address-cells = <1>;
 243                 #size-cells = <1>;
 244                 ranges = <0 0 0 0xffffffff>;
 245
 246                 spi0: spi@54006000 {
 247                         compatible = "socionext,uniphier-scssi";
 248                         status = "disabled";
 249                         reg = <0x54006000 0x100>;
 250                         #address-cells = <1>;
 251                         #size-cells = <0>;
 252                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 253                         pinctrl-names = "default";
 254                         pinctrl-0 = <&pinctrl_spi0>;
 255                         clocks = <&peri_clk 11>;
 256                         resets = <&peri_rst 11>;
 257                 };
 258
 259                 spi1: spi@54006100 {
 260                         compatible = "socionext,uniphier-scssi";
 261                         status = "disabled";
 262                         reg = <0x54006100 0x100>;
 263                         #address-cells = <1>;
 264                         #size-cells = <0>;
 265                         interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
 266                         pinctrl-names = "default";
 267                         pinctrl-0 = <&pinctrl_spi1>;
 268                         clocks = <&peri_clk 12>;
 269                         resets = <&peri_rst 12>;
 270                 };
 271
 272                 spi2: spi@54006200 {
 273                         compatible = "socionext,uniphier-scssi";
 274                         status = "disabled";
 275                         reg = <0x54006200 0x100>;
 276                         #address-cells = <1>;
 277                         #size-cells = <0>;
 278                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
 279                         pinctrl-names = "default";
 280                         pinctrl-0 = <&pinctrl_spi2>;
 281                         clocks = <&peri_clk 13>;
 282                         resets = <&peri_rst 13>;
 283                 };
 284
 285                 spi3: spi@54006300 {
 286                         compatible = "socionext,uniphier-scssi";
 287                         status = "disabled";
 288                         reg = <0x54006300 0x100>;
 289                         #address-cells = <1>;
 290                         #size-cells = <0>;
 291                         interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
 292                         pinctrl-names = "default";
 293                         pinctrl-0 = <&pinctrl_spi3>;
 294                         clocks = <&peri_clk 14>;
 295                         resets = <&peri_rst 14>;
 296                 };
 297
 298                 serial0: serial@54006800 {
 299                         compatible = "socionext,uniphier-uart";
 300                         status = "disabled";
 301                         reg = <0x54006800 0x40>;
 302                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 303                         pinctrl-names = "default";
 304                         pinctrl-0 = <&pinctrl_uart0>;
 305                         clocks = <&peri_clk 0>;
 306                         resets = <&peri_rst 0>;
 307                 };
 308
 309                 serial1: serial@54006900 {
 310                         compatible = "socionext,uniphier-uart";
 311                         status = "disabled";
 312                         reg = <0x54006900 0x40>;
 313                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 314                         pinctrl-names = "default";
 315                         pinctrl-0 = <&pinctrl_uart1>;
 316                         clocks = <&peri_clk 1>;
 317                         resets = <&peri_rst 1>;
 318                 };
 319
 320                 serial2: serial@54006a00 {
 321                         compatible = "socionext,uniphier-uart";
 322                         status = "disabled";
 323                         reg = <0x54006a00 0x40>;
 324                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 325                         pinctrl-names = "default";
 326                         pinctrl-0 = <&pinctrl_uart2>;
 327                         clocks = <&peri_clk 2>;
 328                         resets = <&peri_rst 2>;
 329                 };
 330
 331                 serial3: serial@54006b00 {
 332                         compatible = "socionext,uniphier-uart";
 333                         status = "disabled";
 334                         reg = <0x54006b00 0x40>;
 335                         interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
 336                         pinctrl-names = "default";
 337                         pinctrl-0 = <&pinctrl_uart3>;
 338                         clocks = <&peri_clk 3>;
 339                         resets = <&peri_rst 3>;
 340                 };
 341
 342                 gpio: gpio@55000000 {
 343                         compatible = "socionext,uniphier-gpio";
 344                         reg = <0x55000000 0x200>;
 345                         interrupt-parent = <&aidet>;
 346                         interrupt-controller;
 347                         #interrupt-cells = <2>;
 348                         gpio-controller;
 349                         #gpio-cells = <2>;
 350                         gpio-ranges = <&pinctrl 0 0 0>,
 351                                       <&pinctrl 96 0 0>,
 352                                       <&pinctrl 160 0 0>;
 353                         gpio-ranges-group-names = "gpio_range0",
 354                                                   "gpio_range1",
 355                                                   "gpio_range2";
 356                         ngpios = <205>;
 357                         socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
 358                                                      <21 217 3>;
 359                 };
 360
 361                 audio@56000000 {
 362                         compatible = "socionext,uniphier-ld20-aio";
 363                         reg = <0x56000000 0x80000>;
 364                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 365                         pinctrl-names = "default";
 366                         pinctrl-0 = <&pinctrl_aout1>,
 367                                     <&pinctrl_aoutiec1>;
 368                         clock-names = "aio";
 369                         clocks = <&sys_clk 40>;
 370                         reset-names = "aio";
 371                         resets = <&sys_rst 40>;
 372                         #sound-dai-cells = <1>;
 373                         socionext,syscon = <&soc_glue>;
 374
 375                         i2s_port0: port@0 {
 376                                 i2s_hdmi: endpoint {
 377                                 };
 378                         };
 379
 380                         i2s_port1: port@1 {
 381                                 i2s_pcmin2: endpoint {
 382                                 };
 383                         };
 384
 385                         i2s_port2: port@2 {
 386                                 i2s_line: endpoint {
 387                                         dai-format = "i2s";
 388                                         remote-endpoint = <&evea_line>;
 389                                 };
 390                         };
 391
 392                         i2s_port3: port@3 {
 393                                 i2s_hpcmout1: endpoint {
 394                                 };
 395                         };
 396
 397                         i2s_port4: port@4 {
 398                                 i2s_hp: endpoint {
 399                                         dai-format = "i2s";
 400                                         remote-endpoint = <&evea_hp>;
 401                                 };
 402                         };
 403
 404                         spdif_port0: port@5 {
 405                                 spdif_hiecout1: endpoint {
 406                                 };
 407                         };
 408
 409                         src_port0: port@6 {
 410                                 i2s_epcmout2: endpoint {
 411                                 };
 412                         };
 413
 414                         src_port1: port@7 {
 415                                 i2s_epcmout3: endpoint {
 416                                 };
 417                         };
 418
 419                         comp_spdif_port0: port@8 {
 420                                 comp_spdif_hiecout1: endpoint {
 421                                 };
 422                         };
 423                 };
 424
 425                 codec@57900000 {
 426                         compatible = "socionext,uniphier-evea";
 427                         reg = <0x57900000 0x1000>;
 428                         clock-names = "evea", "exiv";
 429                         clocks = <&sys_clk 41>, <&sys_clk 42>;
 430                         reset-names = "evea", "exiv", "adamv";
 431                         resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>;
 432                         #sound-dai-cells = <1>;
 433
 434                         port@0 {
 435                                 evea_line: endpoint {
 436                                         remote-endpoint = <&i2s_line>;
 437                                 };
 438                         };
 439
 440                         port@1 {
 441                                 evea_hp: endpoint {
 442                                         remote-endpoint = <&i2s_hp>;
 443                                 };
 444                         };
 445                 };
 446
 447                 syscon@57920000 {
 448                         compatible = "socionext,uniphier-ld20-adamv",
 449                                      "simple-mfd", "syscon";
 450                         reg = <0x57920000 0x1000>;
 451
 452                         adamv_rst: reset-controller {
 453                                 compatible = "socionext,uniphier-ld20-adamv-reset";
 454                                 #reset-cells = <1>;
 455                         };
 456                 };
 457
 458                 i2c0: i2c@58780000 {
 459                         compatible = "socionext,uniphier-fi2c";
 460                         status = "disabled";
 461                         reg = <0x58780000 0x80>;
 462                         #address-cells = <1>;
 463                         #size-cells = <0>;
 464                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 465                         pinctrl-names = "default";
 466                         pinctrl-0 = <&pinctrl_i2c0>;
 467                         clocks = <&peri_clk 4>;
 468                         resets = <&peri_rst 4>;
 469                         clock-frequency = <100000>;
 470                 };
 471
 472                 i2c1: i2c@58781000 {
 473                         compatible = "socionext,uniphier-fi2c";
 474                         status = "disabled";
 475                         reg = <0x58781000 0x80>;
 476                         #address-cells = <1>;
 477                         #size-cells = <0>;
 478                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 479                         pinctrl-names = "default";
 480                         pinctrl-0 = <&pinctrl_i2c1>;
 481                         clocks = <&peri_clk 5>;
 482                         resets = <&peri_rst 5>;
 483                         clock-frequency = <100000>;
 484                 };
 485
 486                 i2c2: i2c@58782000 {
 487                         compatible = "socionext,uniphier-fi2c";
 488                         reg = <0x58782000 0x80>;
 489                         #address-cells = <1>;
 490                         #size-cells = <0>;
 491                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 492                         clocks = <&peri_clk 6>;
 493                         resets = <&peri_rst 6>;
 494                         clock-frequency = <400000>;
 495                 };
 496
 497                 i2c3: i2c@58783000 {
 498                         compatible = "socionext,uniphier-fi2c";
 499                         status = "disabled";
 500                         reg = <0x58783000 0x80>;
 501                         #address-cells = <1>;
 502                         #size-cells = <0>;
 503                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 504                         pinctrl-names = "default";
 505                         pinctrl-0 = <&pinctrl_i2c3>;
 506                         clocks = <&peri_clk 7>;
 507                         resets = <&peri_rst 7>;
 508                         clock-frequency = <100000>;
 509                 };
 510
 511                 i2c4: i2c@58784000 {
 512                         compatible = "socionext,uniphier-fi2c";
 513                         status = "disabled";
 514                         reg = <0x58784000 0x80>;
 515                         #address-cells = <1>;
 516                         #size-cells = <0>;
 517                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 518                         pinctrl-names = "default";
 519                         pinctrl-0 = <&pinctrl_i2c4>;
 520                         clocks = <&peri_clk 8>;
 521                         resets = <&peri_rst 8>;
 522                         clock-frequency = <100000>;
 523                 };
 524
 525                 i2c5: i2c@58785000 {
 526                         compatible = "socionext,uniphier-fi2c";
 527                         reg = <0x58785000 0x80>;
 528                         #address-cells = <1>;
 529                         #size-cells = <0>;
 530                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 531                         clocks = <&peri_clk 9>;
 532                         resets = <&peri_rst 9>;
 533                         clock-frequency = <400000>;
 534                 };
 535
 536                 system_bus: system-bus@58c00000 {
 537                         compatible = "socionext,uniphier-system-bus";
 538                         status = "disabled";
 539                         reg = <0x58c00000 0x400>;
 540                         #address-cells = <2>;
 541                         #size-cells = <1>;
 542                         pinctrl-names = "default";
 543                         pinctrl-0 = <&pinctrl_system_bus>;
 544                 };
 545
 546                 smpctrl@59801000 {
 547                         compatible = "socionext,uniphier-smpctrl";
 548                         reg = <0x59801000 0x400>;
 549                 };
 550
 551                 sdctrl: syscon@59810000 {
 552                         compatible = "socionext,uniphier-ld20-sdctrl",
 553                                      "simple-mfd", "syscon";
 554                         reg = <0x59810000 0x400>;
 555
 556                         sd_clk: clock-controller {
 557                                 compatible = "socionext,uniphier-ld20-sd-clock";
 558                                 #clock-cells = <1>;
 559                         };
 560
 561                         sd_rst: reset-controller {
 562                                 compatible = "socionext,uniphier-ld20-sd-reset";
 563                                 #reset-cells = <1>;
 564                         };
 565                 };
 566
 567                 syscon@59820000 {
 568                         compatible = "socionext,uniphier-ld20-perictrl",
 569                                      "simple-mfd", "syscon";
 570                         reg = <0x59820000 0x200>;
 571
 572                         peri_clk: clock-controller {
 573                                 compatible = "socionext,uniphier-ld20-peri-clock";
 574                                 #clock-cells = <1>;
 575                         };
 576
 577                         peri_rst: reset-controller {
 578                                 compatible = "socionext,uniphier-ld20-peri-reset";
 579                                 #reset-cells = <1>;
 580                         };
 581                 };
 582
 583                 emmc: mmc@5a000000 {
 584                         compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
 585                         reg = <0x5a000000 0x400>;
 586                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 587                         pinctrl-names = "default";
 588                         pinctrl-0 = <&pinctrl_emmc>;
 589                         clocks = <&sys_clk 4>;
 590                         resets = <&sys_rst 4>;
 591                         bus-width = <8>;
 592                         mmc-ddr-1_8v;
 593                         mmc-hs200-1_8v;
 594                         mmc-pwrseq = <&emmc_pwrseq>;
 595                         cdns,phy-input-delay-legacy = <9>;
 596                         cdns,phy-input-delay-mmc-highspeed = <2>;
 597                         cdns,phy-input-delay-mmc-ddr = <3>;
 598                         cdns,phy-dll-delay-sdclk = <21>;
 599                         cdns,phy-dll-delay-sdclk-hsmmc = <21>;
 600                 };
 601
 602                 sd: mmc@5a400000 {
 603                         compatible = "socionext,uniphier-sd-v3.1.1";
 604                         status = "disabled";
 605                         reg = <0x5a400000 0x800>;
 606                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 607                         pinctrl-names = "default";
 608                         pinctrl-0 = <&pinctrl_sd>;
 609                         clocks = <&sd_clk 0>;
 610                         reset-names = "host";
 611                         resets = <&sd_rst 0>;
 612                         bus-width = <4>;
 613                         cap-sd-highspeed;
 614                         socionext,syscon-uhs-mode = <&sdctrl 0>;
 615                 };
 616
 617                 soc_glue: syscon@5f800000 {
 618                         compatible = "socionext,uniphier-ld20-soc-glue",
 619                                      "simple-mfd", "syscon";
 620                         reg = <0x5f800000 0x2000>;
 621
 622                         pinctrl: pinctrl {
 623                                 compatible = "socionext,uniphier-ld20-pinctrl";
 624                         };
 625                 };
 626
 627                 syscon@5f900000 {
 628                         compatible = "socionext,uniphier-ld20-soc-glue-debug",
 629                                      "simple-mfd", "syscon";
 630                         reg = <0x5f900000 0x2000>;
 631                         #address-cells = <1>;
 632                         #size-cells = <1>;
 633                         ranges = <0 0x5f900000 0x2000>;
 634
 635                         efuse@100 {
 636                                 compatible = "socionext,uniphier-efuse";
 637                                 reg = <0x100 0x28>;
 638                         };
 639
 640                         efuse@200 {
 641                                 compatible = "socionext,uniphier-efuse";
 642                                 reg = <0x200 0x68>;
 643                                 #address-cells = <1>;
 644                                 #size-cells = <1>;
 645
 646                                 /* USB cells */
 647                                 usb_rterm0: trim@54,4 {
 648                                         reg = <0x54 1>;
 649                                         bits = <4 2>;
 650                                 };
 651                                 usb_rterm1: trim@55,4 {
 652                                         reg = <0x55 1>;
 653                                         bits = <4 2>;
 654                                 };
 655                                 usb_rterm2: trim@58,4 {
 656                                         reg = <0x58 1>;
 657                                         bits = <4 2>;
 658                                 };
 659                                 usb_rterm3: trim@59,4 {
 660                                         reg = <0x59 1>;
 661                                         bits = <4 2>;
 662                                 };
 663                                 usb_sel_t0: trim@54,0 {
 664                                         reg = <0x54 1>;
 665                                         bits = <0 4>;
 666                                 };
 667                                 usb_sel_t1: trim@55,0 {
 668                                         reg = <0x55 1>;
 669                                         bits = <0 4>;
 670                                 };
 671                                 usb_sel_t2: trim@58,0 {
 672                                         reg = <0x58 1>;
 673                                         bits = <0 4>;
 674                                 };
 675                                 usb_sel_t3: trim@59,0 {
 676                                         reg = <0x59 1>;
 677                                         bits = <0 4>;
 678                                 };
 679                                 usb_hs_i0: trim@56,0 {
 680                                         reg = <0x56 1>;
 681                                         bits = <0 4>;
 682                                 };
 683                                 usb_hs_i2: trim@5a,0 {
 684                                         reg = <0x5a 1>;
 685                                         bits = <0 4>;
 686                                 };
 687                         };
 688                 };
 689
 690                 xdmac: dma-controller@5fc10000 {
 691                         compatible = "socionext,uniphier-xdmac";
 692                         reg = <0x5fc10000 0x5300>;
 693                         interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
 694                         dma-channels = <16>;
 695                         #dma-cells = <2>;
 696                 };
 697
 698                 aidet: interrupt-controller@5fc20000 {
 699                         compatible = "socionext,uniphier-ld20-aidet";
 700                         reg = <0x5fc20000 0x200>;
 701                         interrupt-controller;
 702                         #interrupt-cells = <2>;
 703                 };
 704
 705                 gic: interrupt-controller@5fe00000 {
 706                         compatible = "arm,gic-v3";
 707                         reg = <0x5fe00000 0x10000>,     /* GICD */
 708                               <0x5fe80000 0x80000>;     /* GICR */
 709                         interrupt-controller;
 710                         #interrupt-cells = <3>;
 711                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 712                 };
 713
 714                 syscon@61840000 {
 715                         compatible = "socionext,uniphier-ld20-sysctrl",
 716                                      "simple-mfd", "syscon";
 717                         reg = <0x61840000 0x10000>;
 718
 719                         sys_clk: clock-controller {
 720                                 compatible = "socionext,uniphier-ld20-clock";
 721                                 #clock-cells = <1>;
 722                         };
 723
 724                         sys_rst: reset-controller {
 725                                 compatible = "socionext,uniphier-ld20-reset";
 726                                 #reset-cells = <1>;
 727                         };
 728
 729                         watchdog {
 730                                 compatible = "socionext,uniphier-wdt";
 731                         };
 732
 733                         pvtctl: thermal-sensor {
 734                                 compatible = "socionext,uniphier-ld20-thermal";
 735                                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 736                                 #thermal-sensor-cells = <0>;
 737                                 socionext,tmod-calibration = <0x0f22 0x68ee>;
 738                         };
 739                 };
 740
 741                 eth: ethernet@65000000 {
 742                         compatible = "socionext,uniphier-ld20-ave4";
 743                         status = "disabled";
 744                         reg = <0x65000000 0x8500>;
 745                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 746                         pinctrl-names = "default";
 747                         pinctrl-0 = <&pinctrl_ether_rgmii>;
 748                         clock-names = "ether";
 749                         clocks = <&sys_clk 6>;
 750                         reset-names = "ether";
 751                         resets = <&sys_rst 6>;
 752                         phy-mode = "rgmii-id";
 753                         local-mac-address = [00 00 00 00 00 00];
 754                         socionext,syscon-phy-mode = <&soc_glue 0>;
 755
 756                         mdio: mdio {
 757                                 #address-cells = <1>;
 758                                 #size-cells = <0>;
 759                         };
 760                 };
 761
 762                 usb: usb@65a00000 {
 763                         compatible = "socionext,uniphier-dwc3", "snps,dwc3";
 764                         status = "disabled";
 765                         reg = <0x65a00000 0xcd00>;
 766                         interrupt-names = "host";
 767                         interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 768                         pinctrl-names = "default";
 769                         pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>,
 770                                     <&pinctrl_usb2>, <&pinctrl_usb3>;
 771                         clock-names = "ref", "bus_early", "suspend";
 772                         clocks = <&sys_clk 14>, <&sys_clk 14>, <&sys_clk 14>;
 773                         resets = <&usb_rst 15>;
 774                         phys = <&usb_hsphy0>, <&usb_hsphy1>,
 775                                <&usb_hsphy2>, <&usb_hsphy3>,
 776                                <&usb_ssphy0>, <&usb_ssphy1>;
 777                         dr_mode = "host";
 778                 };
 779
 780                 usb-controller@65b00000 {
 781                         compatible = "socionext,uniphier-ld20-dwc3-glue",
 782                                      "simple-mfd";
 783                         reg = <0x65b00000 0x400>;
 784                         #address-cells = <1>;
 785                         #size-cells = <1>;
 786                         ranges = <0 0x65b00000 0x400>;
 787
 788                         usb_rst: reset-controller@0 {
 789                                 compatible = "socionext,uniphier-ld20-usb3-reset";
 790                                 reg = <0x0 0x4>;
 791                                 #reset-cells = <1>;
 792                                 clock-names = "link";
 793                                 clocks = <&sys_clk 14>;
 794                                 reset-names = "link";
 795                                 resets = <&sys_rst 14>;
 796                         };
 797
 798                         usb_vbus0: regulator@100 {
 799                                 compatible = "socionext,uniphier-ld20-usb3-regulator";
 800                                 reg = <0x100 0x10>;
 801                                 clock-names = "link";
 802                                 clocks = <&sys_clk 14>;
 803                                 reset-names = "link";
 804                                 resets = <&sys_rst 14>;
 805                         };
 806
 807                         usb_vbus1: regulator@110 {
 808                                 compatible = "socionext,uniphier-ld20-usb3-regulator";
 809                                 reg = <0x110 0x10>;
 810                                 clock-names = "link";
 811                                 clocks = <&sys_clk 14>;
 812                                 reset-names = "link";
 813                                 resets = <&sys_rst 14>;
 814                         };
 815
 816                         usb_vbus2: regulator@120 {
 817                                 compatible = "socionext,uniphier-ld20-usb3-regulator";
 818                                 reg = <0x120 0x10>;
 819                                 clock-names = "link";
 820                                 clocks = <&sys_clk 14>;
 821                                 reset-names = "link";
 822                                 resets = <&sys_rst 14>;
 823                         };
 824
 825                         usb_vbus3: regulator@130 {
 826                                 compatible = "socionext,uniphier-ld20-usb3-regulator";
 827                                 reg = <0x130 0x10>;
 828                                 clock-names = "link";
 829                                 clocks = <&sys_clk 14>;
 830                                 reset-names = "link";
 831                                 resets = <&sys_rst 14>;
 832                         };
 833
 834                         usb_hsphy0: phy@200 {
 835                                 compatible = "socionext,uniphier-ld20-usb3-hsphy";
 836                                 reg = <0x200 0x10>;
 837                                 #phy-cells = <0>;
 838                                 clock-names = "link", "phy";
 839                                 clocks = <&sys_clk 14>, <&sys_clk 16>;
 840                                 reset-names = "link", "phy";
 841                                 resets = <&sys_rst 14>, <&sys_rst 16>;
 842                                 vbus-supply = <&usb_vbus0>;
 843                                 nvmem-cell-names = "rterm", "sel_t", "hs_i";
 844                                 nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>,
 845                                               <&usb_hs_i0>;
 846                         };
 847
 848                         usb_hsphy1: phy@210 {
 849                                 compatible = "socionext,uniphier-ld20-usb3-hsphy";
 850                                 reg = <0x210 0x10>;
 851                                 #phy-cells = <0>;
 852                                 clock-names = "link", "phy";
 853                                 clocks = <&sys_clk 14>, <&sys_clk 16>;
 854                                 reset-names = "link", "phy";
 855                                 resets = <&sys_rst 14>, <&sys_rst 16>;
 856                                 vbus-supply = <&usb_vbus1>;
 857                                 nvmem-cell-names = "rterm", "sel_t", "hs_i";
 858                                 nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>,
 859                                               <&usb_hs_i0>;
 860                         };
 861
 862                         usb_hsphy2: phy@220 {
 863                                 compatible = "socionext,uniphier-ld20-usb3-hsphy";
 864                                 reg = <0x220 0x10>;
 865                                 #phy-cells = <0>;
 866                                 clock-names = "link", "phy";
 867                                 clocks = <&sys_clk 14>, <&sys_clk 17>;
 868                                 reset-names = "link", "phy";
 869                                 resets = <&sys_rst 14>, <&sys_rst 17>;
 870                                 vbus-supply = <&usb_vbus2>;
 871                                 nvmem-cell-names = "rterm", "sel_t", "hs_i";
 872                                 nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>,
 873                                               <&usb_hs_i2>;
 874                         };
 875
 876                         usb_hsphy3: phy@230 {
 877                                 compatible = "socionext,uniphier-ld20-usb3-hsphy";
 878                                 reg = <0x230 0x10>;
 879                                 #phy-cells = <0>;
 880                                 clock-names = "link", "phy";
 881                                 clocks = <&sys_clk 14>, <&sys_clk 17>;
 882                                 reset-names = "link", "phy";
 883                                 resets = <&sys_rst 14>, <&sys_rst 17>;
 884                                 vbus-supply = <&usb_vbus3>;
 885                                 nvmem-cell-names = "rterm", "sel_t", "hs_i";
 886                                 nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>,
 887                                               <&usb_hs_i2>;
 888                         };
 889
 890                         usb_ssphy0: phy@300 {
 891                                 compatible = "socionext,uniphier-ld20-usb3-ssphy";
 892                                 reg = <0x300 0x10>;
 893                                 #phy-cells = <0>;
 894                                 clock-names = "link", "phy";
 895                                 clocks = <&sys_clk 14>, <&sys_clk 18>;
 896                                 reset-names = "link", "phy";
 897                                 resets = <&sys_rst 14>, <&sys_rst 18>;
 898                                 vbus-supply = <&usb_vbus0>;
 899                         };
 900
 901                         usb_ssphy1: phy@310 {
 902                                 compatible = "socionext,uniphier-ld20-usb3-ssphy";
 903                                 reg = <0x310 0x10>;
 904                                 #phy-cells = <0>;
 905                                 clock-names = "link", "phy";
 906                                 clocks = <&sys_clk 14>, <&sys_clk 19>;
 907                                 reset-names = "link", "phy";
 908                                 resets = <&sys_rst 14>, <&sys_rst 19>;
 909                                 vbus-supply = <&usb_vbus1>;
 910                         };
 911                 };
 912
 913                 pcie: pcie@66000000 {
 914                         compatible = "socionext,uniphier-pcie";
 915                         status = "disabled";
 916                         reg-names = "dbi", "link", "config";
 917                         reg = <0x66000000 0x1000>, <0x66010000 0x10000>,
 918                               <0x2fff0000 0x10000>;
 919                         #address-cells = <3>;
 920                         #size-cells = <2>;
 921                         clocks = <&sys_clk 24>;
 922                         resets = <&sys_rst 24>;
 923                         num-lanes = <1>;
 924                         num-viewport = <1>;
 925                         bus-range = <0x0 0xff>;
 926                         device_type = "pci";
 927                         ranges =
 928                         /* downstream I/O */
 929                                 <0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>,
 930                         /* non-prefetchable memory */
 931                                 <0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>;
 932                         #interrupt-cells = <1>;
 933                         interrupt-names = "dma", "msi";
 934                         interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
 935                                      <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
 936                         interrupt-map-mask = <0 0 0 7>;
 937                         interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */
 938                                         <0 0 0 2 &pcie_intc 1>, /* INTB */
 939                                         <0 0 0 3 &pcie_intc 2>, /* INTC */
 940                                         <0 0 0 4 &pcie_intc 3>; /* INTD */
 941                         phy-names = "pcie-phy";
 942                         phys = <&pcie_phy>;
 943
 944                         pcie_intc: legacy-interrupt-controller {
 945                                 interrupt-controller;
 946                                 #interrupt-cells = <1>;
 947                                 interrupt-parent = <&gic>;
 948                                 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
 949                         };
 950                 };
 951
 952                 pcie_phy: phy@66038000 {
 953                         compatible = "socionext,uniphier-ld20-pcie-phy";
 954                         reg = <0x66038000 0x4000>;
 955                         #phy-cells = <0>;
 956                         clock-names = "link";
 957                         clocks = <&sys_clk 24>;
 958                         reset-names = "link";
 959                         resets = <&sys_rst 24>;
 960                         socionext,syscon = <&soc_glue>;
 961                 };
 962
 963                 nand: nand-controller@68000000 {
 964                         compatible = "socionext,uniphier-denali-nand-v5b";
 965                         status = "disabled";
 966                         reg-names = "nand_data", "denali_reg";
 967                         reg = <0x68000000 0x20>, <0x68100000 0x1000>;
 968                         #address-cells = <1>;
 969                         #size-cells = <0>;
 970                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 971                         pinctrl-names = "default";
 972                         pinctrl-0 = <&pinctrl_nand>;
 973                         clock-names = "nand", "nand_x", "ecc";
 974                         clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
 975                         reset-names = "nand", "reg";
 976                         resets = <&sys_rst 2>, <&sys_rst 2>;
 977                 };
 978         };
 979 };
 980
 981 #include "uniphier-pinctrl.dtsi"
 982
 983 &pinctrl_aout1 {
 984         drive-strength = <4>;   /* default: 3.5mA */
 985
 986         ao1dacck {
 987                 pins = "AO1DACCK";
 988                 drive-strength = <5>;   /* 5mA */
 989         };
 990 };
 991
 992 &pinctrl_aoutiec1 {
 993         drive-strength = <4>;   /* default: 3.5mA */
 994
 995         ao1arc {
 996                 pins = "AO1ARC";
 997                 drive-strength = <11>;  /* 11mA */
 998         };
 999 };