1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier LD20 SoC
5 // Copyright (C) 2015-2016 Socionext Inc.
6 // Author: Masahiro Yamada <yamada.masahiro@socionext.com>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
10 #include <dt-bindings/thermal/thermal.h>
12 /memreserve/ 0x80000000 0x02000000;
15 compatible = "socionext,uniphier-ld20";
18 interrupt-parent = <&gic>;
46 compatible = "arm,cortex-a72", "arm,armv8";
48 clocks = <&sys_clk 32>;
49 enable-method = "psci";
50 operating-points-v2 = <&cluster0_opp>;
56 compatible = "arm,cortex-a72", "arm,armv8";
58 clocks = <&sys_clk 32>;
59 enable-method = "psci";
60 operating-points-v2 = <&cluster0_opp>;
66 compatible = "arm,cortex-a53", "arm,armv8";
68 clocks = <&sys_clk 33>;
69 enable-method = "psci";
70 operating-points-v2 = <&cluster1_opp>;
76 compatible = "arm,cortex-a53", "arm,armv8";
78 clocks = <&sys_clk 33>;
79 enable-method = "psci";
80 operating-points-v2 = <&cluster1_opp>;
85 cluster0_opp: opp-table0 {
86 compatible = "operating-points-v2";
90 opp-hz = /bits/ 64 <250000000>;
91 clock-latency-ns = <300>;
94 opp-hz = /bits/ 64 <275000000>;
95 clock-latency-ns = <300>;
98 opp-hz = /bits/ 64 <500000000>;
99 clock-latency-ns = <300>;
102 opp-hz = /bits/ 64 <550000000>;
103 clock-latency-ns = <300>;
106 opp-hz = /bits/ 64 <666667000>;
107 clock-latency-ns = <300>;
110 opp-hz = /bits/ 64 <733334000>;
111 clock-latency-ns = <300>;
114 opp-hz = /bits/ 64 <1000000000>;
115 clock-latency-ns = <300>;
118 opp-hz = /bits/ 64 <1100000000>;
119 clock-latency-ns = <300>;
123 cluster1_opp: opp-table1 {
124 compatible = "operating-points-v2";
128 opp-hz = /bits/ 64 <250000000>;
129 clock-latency-ns = <300>;
132 opp-hz = /bits/ 64 <275000000>;
133 clock-latency-ns = <300>;
136 opp-hz = /bits/ 64 <500000000>;
137 clock-latency-ns = <300>;
140 opp-hz = /bits/ 64 <550000000>;
141 clock-latency-ns = <300>;
144 opp-hz = /bits/ 64 <666667000>;
145 clock-latency-ns = <300>;
148 opp-hz = /bits/ 64 <733334000>;
149 clock-latency-ns = <300>;
152 opp-hz = /bits/ 64 <1000000000>;
153 clock-latency-ns = <300>;
156 opp-hz = /bits/ 64 <1100000000>;
157 clock-latency-ns = <300>;
162 compatible = "arm,psci-1.0";
168 compatible = "fixed-clock";
170 clock-frequency = <25000000>;
174 emmc_pwrseq: emmc-pwrseq {
175 compatible = "mmc-pwrseq-emmc";
176 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>;
180 compatible = "arm,armv8-timer";
181 interrupts = <1 13 4>,
189 polling-delay-passive = <250>; /* 250ms */
190 polling-delay = <1000>; /* 1000ms */
191 thermal-sensors = <&pvtctl>;
195 temperature = <110000>; /* 110C */
199 cpu_alert: cpu-alert {
200 temperature = <100000>; /* 100C */
209 cooling-device = <&cpu0
210 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
214 cooling-device = <&cpu2
215 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
222 compatible = "simple-bus";
223 #address-cells = <1>;
225 ranges = <0 0 0 0xffffffff>;
228 compatible = "socionext,uniphier-scssi";
230 reg = <0x54006000 0x100>;
231 interrupts = <0 39 4>;
232 pinctrl-names = "default";
233 pinctrl-0 = <&pinctrl_spi0>;
234 clocks = <&peri_clk 11>;
235 resets = <&peri_rst 11>;
239 compatible = "socionext,uniphier-scssi";
241 reg = <0x54006100 0x100>;
242 interrupts = <0 216 4>;
243 pinctrl-names = "default";
244 pinctrl-0 = <&pinctrl_spi1>;
245 clocks = <&peri_clk 11>;
246 resets = <&peri_rst 11>;
250 compatible = "socionext,uniphier-scssi";
252 reg = <0x54006200 0x100>;
253 interrupts = <0 229 4>;
254 pinctrl-names = "default";
255 pinctrl-0 = <&pinctrl_spi2>;
256 clocks = <&peri_clk 11>;
257 resets = <&peri_rst 11>;
261 compatible = "socionext,uniphier-scssi";
263 reg = <0x54006300 0x100>;
264 interrupts = <0 230 4>;
265 pinctrl-names = "default";
266 pinctrl-0 = <&pinctrl_spi3>;
267 clocks = <&peri_clk 11>;
268 resets = <&peri_rst 11>;
271 serial0: serial@54006800 {
272 compatible = "socionext,uniphier-uart";
274 reg = <0x54006800 0x40>;
275 interrupts = <0 33 4>;
276 pinctrl-names = "default";
277 pinctrl-0 = <&pinctrl_uart0>;
278 clocks = <&peri_clk 0>;
279 resets = <&peri_rst 0>;
282 serial1: serial@54006900 {
283 compatible = "socionext,uniphier-uart";
285 reg = <0x54006900 0x40>;
286 interrupts = <0 35 4>;
287 pinctrl-names = "default";
288 pinctrl-0 = <&pinctrl_uart1>;
289 clocks = <&peri_clk 1>;
290 resets = <&peri_rst 1>;
293 serial2: serial@54006a00 {
294 compatible = "socionext,uniphier-uart";
296 reg = <0x54006a00 0x40>;
297 interrupts = <0 37 4>;
298 pinctrl-names = "default";
299 pinctrl-0 = <&pinctrl_uart2>;
300 clocks = <&peri_clk 2>;
301 resets = <&peri_rst 2>;
304 serial3: serial@54006b00 {
305 compatible = "socionext,uniphier-uart";
307 reg = <0x54006b00 0x40>;
308 interrupts = <0 177 4>;
309 pinctrl-names = "default";
310 pinctrl-0 = <&pinctrl_uart3>;
311 clocks = <&peri_clk 3>;
312 resets = <&peri_rst 3>;
315 gpio: gpio@55000000 {
316 compatible = "socionext,uniphier-gpio";
317 reg = <0x55000000 0x200>;
318 interrupt-parent = <&aidet>;
319 interrupt-controller;
320 #interrupt-cells = <2>;
323 gpio-ranges = <&pinctrl 0 0 0>,
326 gpio-ranges-group-names = "gpio_range0",
330 socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
335 compatible = "socionext,uniphier-ld20-aio";
336 reg = <0x56000000 0x80000>;
337 interrupts = <0 144 4>;
338 pinctrl-names = "default";
339 pinctrl-0 = <&pinctrl_aout1>,
342 clocks = <&sys_clk 40>;
344 resets = <&sys_rst 40>;
345 #sound-dai-cells = <1>;
346 socionext,syscon = <&soc_glue>;
354 i2s_pcmin2: endpoint {
361 remote-endpoint = <&evea_line>;
366 i2s_hpcmout1: endpoint {
373 remote-endpoint = <&evea_hp>;
377 spdif_port0: port@5 {
378 spdif_hiecout1: endpoint {
383 i2s_epcmout2: endpoint {
388 i2s_epcmout3: endpoint {
392 comp_spdif_port0: port@8 {
393 comp_spdif_hiecout1: endpoint {
399 compatible = "socionext,uniphier-evea";
400 reg = <0x57900000 0x1000>;
401 clock-names = "evea", "exiv";
402 clocks = <&sys_clk 41>, <&sys_clk 42>;
403 reset-names = "evea", "exiv", "adamv";
404 resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>;
405 #sound-dai-cells = <1>;
408 evea_line: endpoint {
409 remote-endpoint = <&i2s_line>;
415 remote-endpoint = <&i2s_hp>;
421 compatible = "socionext,uniphier-ld20-adamv",
422 "simple-mfd", "syscon";
423 reg = <0x57920000 0x1000>;
426 compatible = "socionext,uniphier-ld20-adamv-reset";
432 compatible = "socionext,uniphier-fi2c";
434 reg = <0x58780000 0x80>;
435 #address-cells = <1>;
437 interrupts = <0 41 4>;
438 pinctrl-names = "default";
439 pinctrl-0 = <&pinctrl_i2c0>;
440 clocks = <&peri_clk 4>;
441 resets = <&peri_rst 4>;
442 clock-frequency = <100000>;
446 compatible = "socionext,uniphier-fi2c";
448 reg = <0x58781000 0x80>;
449 #address-cells = <1>;
451 interrupts = <0 42 4>;
452 pinctrl-names = "default";
453 pinctrl-0 = <&pinctrl_i2c1>;
454 clocks = <&peri_clk 5>;
455 resets = <&peri_rst 5>;
456 clock-frequency = <100000>;
460 compatible = "socionext,uniphier-fi2c";
461 reg = <0x58782000 0x80>;
462 #address-cells = <1>;
464 interrupts = <0 43 4>;
465 clocks = <&peri_clk 6>;
466 resets = <&peri_rst 6>;
467 clock-frequency = <400000>;
471 compatible = "socionext,uniphier-fi2c";
473 reg = <0x58783000 0x80>;
474 #address-cells = <1>;
476 interrupts = <0 44 4>;
477 pinctrl-names = "default";
478 pinctrl-0 = <&pinctrl_i2c3>;
479 clocks = <&peri_clk 7>;
480 resets = <&peri_rst 7>;
481 clock-frequency = <100000>;
485 compatible = "socionext,uniphier-fi2c";
487 reg = <0x58784000 0x80>;
488 #address-cells = <1>;
490 interrupts = <0 45 4>;
491 pinctrl-names = "default";
492 pinctrl-0 = <&pinctrl_i2c4>;
493 clocks = <&peri_clk 8>;
494 resets = <&peri_rst 8>;
495 clock-frequency = <100000>;
499 compatible = "socionext,uniphier-fi2c";
500 reg = <0x58785000 0x80>;
501 #address-cells = <1>;
503 interrupts = <0 25 4>;
504 clocks = <&peri_clk 9>;
505 resets = <&peri_rst 9>;
506 clock-frequency = <400000>;
509 system_bus: system-bus@58c00000 {
510 compatible = "socionext,uniphier-system-bus";
512 reg = <0x58c00000 0x400>;
513 #address-cells = <2>;
515 pinctrl-names = "default";
516 pinctrl-0 = <&pinctrl_system_bus>;
520 compatible = "socionext,uniphier-smpctrl";
521 reg = <0x59801000 0x400>;
525 compatible = "socionext,uniphier-ld20-sdctrl",
526 "simple-mfd", "syscon";
527 reg = <0x59810000 0x400>;
530 compatible = "socionext,uniphier-ld20-sd-clock";
535 compatible = "socionext,uniphier-ld20-sd-reset";
541 compatible = "socionext,uniphier-ld20-perictrl",
542 "simple-mfd", "syscon";
543 reg = <0x59820000 0x200>;
546 compatible = "socionext,uniphier-ld20-peri-clock";
551 compatible = "socionext,uniphier-ld20-peri-reset";
556 emmc: sdhc@5a000000 {
557 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
558 reg = <0x5a000000 0x400>;
559 interrupts = <0 78 4>;
560 pinctrl-names = "default";
561 pinctrl-0 = <&pinctrl_emmc>;
562 clocks = <&sys_clk 4>;
563 resets = <&sys_rst 4>;
567 mmc-pwrseq = <&emmc_pwrseq>;
568 cdns,phy-input-delay-legacy = <9>;
569 cdns,phy-input-delay-mmc-highspeed = <2>;
570 cdns,phy-input-delay-mmc-ddr = <3>;
571 cdns,phy-dll-delay-sdclk = <21>;
572 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
576 compatible = "socionext,uniphier-sd-v3.1.1";
578 reg = <0x5a400000 0x800>;
579 interrupts = <0 76 4>;
580 pinctrl-names = "default";
581 pinctrl-0 = <&pinctrl_sd>;
582 clocks = <&sd_clk 0>;
583 reset-names = "host";
584 resets = <&sd_rst 0>;
589 soc_glue: soc-glue@5f800000 {
590 compatible = "socionext,uniphier-ld20-soc-glue",
591 "simple-mfd", "syscon";
592 reg = <0x5f800000 0x2000>;
595 compatible = "socionext,uniphier-ld20-pinctrl";
600 compatible = "socionext,uniphier-ld20-soc-glue-debug",
602 #address-cells = <1>;
604 ranges = <0 0x5f900000 0x2000>;
607 compatible = "socionext,uniphier-efuse";
612 compatible = "socionext,uniphier-efuse";
614 #address-cells = <1>;
618 usb_rterm0: trim@54,4 {
622 usb_rterm1: trim@55,4 {
626 usb_rterm2: trim@58,4 {
630 usb_rterm3: trim@59,4 {
634 usb_sel_t0: trim@54,0 {
638 usb_sel_t1: trim@55,0 {
642 usb_sel_t2: trim@58,0 {
646 usb_sel_t3: trim@59,0 {
650 usb_hs_i0: trim@56,0 {
654 usb_hs_i2: trim@5a,0 {
661 aidet: aidet@5fc20000 {
662 compatible = "socionext,uniphier-ld20-aidet";
663 reg = <0x5fc20000 0x200>;
664 interrupt-controller;
665 #interrupt-cells = <2>;
668 gic: interrupt-controller@5fe00000 {
669 compatible = "arm,gic-v3";
670 reg = <0x5fe00000 0x10000>, /* GICD */
671 <0x5fe80000 0x80000>; /* GICR */
672 interrupt-controller;
673 #interrupt-cells = <3>;
674 interrupts = <1 9 4>;
678 compatible = "socionext,uniphier-ld20-sysctrl",
679 "simple-mfd", "syscon";
680 reg = <0x61840000 0x10000>;
683 compatible = "socionext,uniphier-ld20-clock";
688 compatible = "socionext,uniphier-ld20-reset";
693 compatible = "socionext,uniphier-wdt";
697 compatible = "socionext,uniphier-ld20-thermal";
698 interrupts = <0 3 4>;
699 #thermal-sensor-cells = <0>;
700 socionext,tmod-calibration = <0x0f22 0x68ee>;
704 eth: ethernet@65000000 {
705 compatible = "socionext,uniphier-ld20-ave4";
707 reg = <0x65000000 0x8500>;
708 interrupts = <0 66 4>;
709 pinctrl-names = "default";
710 pinctrl-0 = <&pinctrl_ether_rgmii>;
711 clock-names = "ether";
712 clocks = <&sys_clk 6>;
713 reset-names = "ether";
714 resets = <&sys_rst 6>;
716 local-mac-address = [00 00 00 00 00 00];
717 socionext,syscon-phy-mode = <&soc_glue 0>;
720 #address-cells = <1>;
726 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
728 reg = <0x65a00000 0xcd00>;
729 interrupt-names = "host";
730 interrupts = <0 134 4>;
731 pinctrl-names = "default";
732 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>,
733 <&pinctrl_usb2>, <&pinctrl_usb3>;
734 clock-names = "ref", "bus_early", "suspend";
735 clocks = <&sys_clk 14>, <&sys_clk 14>, <&sys_clk 14>;
736 resets = <&usb_rst 15>;
737 phys = <&usb_hsphy0>, <&usb_hsphy1>,
738 <&usb_hsphy2>, <&usb_hsphy3>,
739 <&usb_ssphy0>, <&usb_ssphy1>;
744 compatible = "socionext,uniphier-ld20-dwc3-glue",
746 #address-cells = <1>;
748 ranges = <0 0x65b00000 0x400>;
751 compatible = "socionext,uniphier-ld20-usb3-reset";
754 clock-names = "link";
755 clocks = <&sys_clk 14>;
756 reset-names = "link";
757 resets = <&sys_rst 14>;
760 usb_vbus0: regulator@100 {
761 compatible = "socionext,uniphier-ld20-usb3-regulator";
763 clock-names = "link";
764 clocks = <&sys_clk 14>;
765 reset-names = "link";
766 resets = <&sys_rst 14>;
769 usb_vbus1: regulator@110 {
770 compatible = "socionext,uniphier-ld20-usb3-regulator";
772 clock-names = "link";
773 clocks = <&sys_clk 14>;
774 reset-names = "link";
775 resets = <&sys_rst 14>;
778 usb_vbus2: regulator@120 {
779 compatible = "socionext,uniphier-ld20-usb3-regulator";
781 clock-names = "link";
782 clocks = <&sys_clk 14>;
783 reset-names = "link";
784 resets = <&sys_rst 14>;
787 usb_vbus3: regulator@130 {
788 compatible = "socionext,uniphier-ld20-usb3-regulator";
790 clock-names = "link";
791 clocks = <&sys_clk 14>;
792 reset-names = "link";
793 resets = <&sys_rst 14>;
796 usb_hsphy0: hs-phy@200 {
797 compatible = "socionext,uniphier-ld20-usb3-hsphy";
800 clock-names = "link", "phy";
801 clocks = <&sys_clk 14>, <&sys_clk 16>;
802 reset-names = "link", "phy";
803 resets = <&sys_rst 14>, <&sys_rst 16>;
804 vbus-supply = <&usb_vbus0>;
805 nvmem-cell-names = "rterm", "sel_t", "hs_i";
806 nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>,
810 usb_hsphy1: hs-phy@210 {
811 compatible = "socionext,uniphier-ld20-usb3-hsphy";
814 clock-names = "link", "phy";
815 clocks = <&sys_clk 14>, <&sys_clk 16>;
816 reset-names = "link", "phy";
817 resets = <&sys_rst 14>, <&sys_rst 16>;
818 vbus-supply = <&usb_vbus1>;
819 nvmem-cell-names = "rterm", "sel_t", "hs_i";
820 nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>,
824 usb_hsphy2: hs-phy@220 {
825 compatible = "socionext,uniphier-ld20-usb3-hsphy";
828 clock-names = "link", "phy";
829 clocks = <&sys_clk 14>, <&sys_clk 17>;
830 reset-names = "link", "phy";
831 resets = <&sys_rst 14>, <&sys_rst 17>;
832 vbus-supply = <&usb_vbus2>;
833 nvmem-cell-names = "rterm", "sel_t", "hs_i";
834 nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>,
838 usb_hsphy3: hs-phy@230 {
839 compatible = "socionext,uniphier-ld20-usb3-hsphy";
842 clock-names = "link", "phy";
843 clocks = <&sys_clk 14>, <&sys_clk 17>;
844 reset-names = "link", "phy";
845 resets = <&sys_rst 14>, <&sys_rst 17>;
846 vbus-supply = <&usb_vbus3>;
847 nvmem-cell-names = "rterm", "sel_t", "hs_i";
848 nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>,
852 usb_ssphy0: ss-phy@300 {
853 compatible = "socionext,uniphier-ld20-usb3-ssphy";
856 clock-names = "link", "phy";
857 clocks = <&sys_clk 14>, <&sys_clk 18>;
858 reset-names = "link", "phy";
859 resets = <&sys_rst 14>, <&sys_rst 18>;
860 vbus-supply = <&usb_vbus0>;
863 usb_ssphy1: ss-phy@310 {
864 compatible = "socionext,uniphier-ld20-usb3-ssphy";
867 clock-names = "link", "phy";
868 clocks = <&sys_clk 14>, <&sys_clk 19>;
869 reset-names = "link", "phy";
870 resets = <&sys_rst 14>, <&sys_rst 19>;
871 vbus-supply = <&usb_vbus1>;
875 /* FIXME: U-Boot own node */
877 compatible = "socionext,uniphier-ld20-dwc3";
878 reg = <0x65b00000 0x1000>;
879 #address-cells = <1>;
882 pinctrl-names = "default";
883 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>,
884 <&pinctrl_usb2>, <&pinctrl_usb3>;
886 compatible = "snps,dwc3";
887 reg = <0x65a00000 0x10000>;
888 interrupts = <0 134 4>;
894 nand: nand@68000000 {
895 compatible = "socionext,uniphier-denali-nand-v5b";
897 reg-names = "nand_data", "denali_reg";
898 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
899 interrupts = <0 65 4>;
900 pinctrl-names = "default";
901 pinctrl-0 = <&pinctrl_nand>;
902 clock-names = "nand", "nand_x", "ecc";
903 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
904 resets = <&sys_rst 2>;
909 #include "uniphier-pinctrl.dtsi"
912 drive-strength = <4>; /* default: 3.5mA */
916 drive-strength = <5>; /* 5mA */
921 drive-strength = <4>; /* default: 3.5mA */
925 drive-strength = <11>; /* 11mA */