2 * Device Tree Source for UniPhier LD20 SoC
4 * Copyright (C) 2015-2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
17 * This file is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
46 /memreserve/ 0x80000000 0x00080000;
49 compatible = "socionext,uniphier-ld20";
52 interrupt-parent = <&gic>;
80 compatible = "arm,cortex-a72", "arm,armv8";
82 clocks = <&sys_clk 32>;
83 enable-method = "psci";
84 operating-points-v2 = <&cluster0_opp>;
89 compatible = "arm,cortex-a72", "arm,armv8";
91 clocks = <&sys_clk 32>;
92 enable-method = "psci";
93 operating-points-v2 = <&cluster0_opp>;
98 compatible = "arm,cortex-a53", "arm,armv8";
100 clocks = <&sys_clk 33>;
101 enable-method = "psci";
102 operating-points-v2 = <&cluster1_opp>;
107 compatible = "arm,cortex-a53", "arm,armv8";
109 clocks = <&sys_clk 33>;
110 enable-method = "psci";
111 operating-points-v2 = <&cluster1_opp>;
115 cluster0_opp: opp_table0 {
116 compatible = "operating-points-v2";
120 opp-hz = /bits/ 64 <250000000>;
121 clock-latency-ns = <300>;
124 opp-hz = /bits/ 64 <275000000>;
125 clock-latency-ns = <300>;
128 opp-hz = /bits/ 64 <500000000>;
129 clock-latency-ns = <300>;
132 opp-hz = /bits/ 64 <550000000>;
133 clock-latency-ns = <300>;
136 opp-hz = /bits/ 64 <666667000>;
137 clock-latency-ns = <300>;
140 opp-hz = /bits/ 64 <733334000>;
141 clock-latency-ns = <300>;
144 opp-hz = /bits/ 64 <1000000000>;
145 clock-latency-ns = <300>;
148 opp-hz = /bits/ 64 <1100000000>;
149 clock-latency-ns = <300>;
153 cluster1_opp: opp_table1 {
154 compatible = "operating-points-v2";
158 opp-hz = /bits/ 64 <250000000>;
159 clock-latency-ns = <300>;
162 opp-hz = /bits/ 64 <275000000>;
163 clock-latency-ns = <300>;
166 opp-hz = /bits/ 64 <500000000>;
167 clock-latency-ns = <300>;
170 opp-hz = /bits/ 64 <550000000>;
171 clock-latency-ns = <300>;
174 opp-hz = /bits/ 64 <666667000>;
175 clock-latency-ns = <300>;
178 opp-hz = /bits/ 64 <733334000>;
179 clock-latency-ns = <300>;
182 opp-hz = /bits/ 64 <1000000000>;
183 clock-latency-ns = <300>;
186 opp-hz = /bits/ 64 <1100000000>;
187 clock-latency-ns = <300>;
192 compatible = "arm,psci-1.0";
198 compatible = "fixed-clock";
200 clock-frequency = <25000000>;
205 compatible = "arm,armv8-timer";
206 interrupts = <1 13 4>,
213 compatible = "simple-bus";
214 #address-cells = <1>;
216 ranges = <0 0 0 0xffffffff>;
219 serial0: serial@54006800 {
220 compatible = "socionext,uniphier-uart";
222 reg = <0x54006800 0x40>;
223 interrupts = <0 33 4>;
224 pinctrl-names = "default";
225 pinctrl-0 = <&pinctrl_uart0>;
226 clocks = <&peri_clk 0>;
227 clock-frequency = <58820000>;
230 serial1: serial@54006900 {
231 compatible = "socionext,uniphier-uart";
233 reg = <0x54006900 0x40>;
234 interrupts = <0 35 4>;
235 pinctrl-names = "default";
236 pinctrl-0 = <&pinctrl_uart1>;
237 clocks = <&peri_clk 1>;
238 clock-frequency = <58820000>;
241 serial2: serial@54006a00 {
242 compatible = "socionext,uniphier-uart";
244 reg = <0x54006a00 0x40>;
245 interrupts = <0 37 4>;
246 pinctrl-names = "default";
247 pinctrl-0 = <&pinctrl_uart2>;
248 clocks = <&peri_clk 2>;
249 clock-frequency = <58820000>;
252 serial3: serial@54006b00 {
253 compatible = "socionext,uniphier-uart";
255 reg = <0x54006b00 0x40>;
256 interrupts = <0 177 4>;
257 pinctrl-names = "default";
258 pinctrl-0 = <&pinctrl_uart3>;
259 clocks = <&peri_clk 3>;
260 clock-frequency = <58820000>;
264 compatible = "socionext,uniphier-fi2c";
266 reg = <0x58780000 0x80>;
267 #address-cells = <1>;
269 interrupts = <0 41 4>;
270 pinctrl-names = "default";
271 pinctrl-0 = <&pinctrl_i2c0>;
272 clocks = <&peri_clk 4>;
273 clock-frequency = <100000>;
277 compatible = "socionext,uniphier-fi2c";
279 reg = <0x58781000 0x80>;
280 #address-cells = <1>;
282 interrupts = <0 42 4>;
283 pinctrl-names = "default";
284 pinctrl-0 = <&pinctrl_i2c1>;
285 clocks = <&peri_clk 5>;
286 clock-frequency = <100000>;
290 compatible = "socionext,uniphier-fi2c";
291 reg = <0x58782000 0x80>;
292 #address-cells = <1>;
294 interrupts = <0 43 4>;
295 clocks = <&peri_clk 6>;
296 clock-frequency = <400000>;
300 compatible = "socionext,uniphier-fi2c";
302 reg = <0x58783000 0x80>;
303 #address-cells = <1>;
305 interrupts = <0 44 4>;
306 pinctrl-names = "default";
307 pinctrl-0 = <&pinctrl_i2c3>;
308 clocks = <&peri_clk 7>;
309 clock-frequency = <100000>;
313 compatible = "socionext,uniphier-fi2c";
315 reg = <0x58784000 0x80>;
316 #address-cells = <1>;
318 interrupts = <0 45 4>;
319 pinctrl-names = "default";
320 pinctrl-0 = <&pinctrl_i2c4>;
321 clocks = <&peri_clk 8>;
322 clock-frequency = <100000>;
326 compatible = "socionext,uniphier-fi2c";
327 reg = <0x58785000 0x80>;
328 #address-cells = <1>;
330 interrupts = <0 25 4>;
331 clocks = <&peri_clk 9>;
332 clock-frequency = <400000>;
335 system_bus: system-bus@58c00000 {
336 compatible = "socionext,uniphier-system-bus";
338 reg = <0x58c00000 0x400>;
339 #address-cells = <2>;
341 pinctrl-names = "default";
342 pinctrl-0 = <&pinctrl_system_bus>;
346 compatible = "socionext,uniphier-smpctrl";
347 reg = <0x59801000 0x400>;
351 compatible = "socionext,uniphier-ld20-sdctrl",
352 "simple-mfd", "syscon";
353 reg = <0x59810000 0x800>;
356 compatible = "socionext,uniphier-ld20-sd-clock";
361 compatible = "socionext,uniphier-ld20-sd-reset";
367 compatible = "socionext,uniphier-ld20-perictrl",
368 "simple-mfd", "syscon";
369 reg = <0x59820000 0x200>;
372 compatible = "socionext,uniphier-ld20-peri-clock";
377 compatible = "socionext,uniphier-ld20-peri-reset";
382 emmc: sdhc@5a000000 {
383 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
384 reg = <0x5a000000 0x400>;
385 interrupts = <0 78 4>;
386 pinctrl-names = "default";
387 pinctrl-0 = <&pinctrl_emmc_1v8>;
388 clocks = <&sys_clk 4>;
392 cdns,phy-input-delay-legacy = <4>;
393 cdns,phy-input-delay-mmc-highspeed = <2>;
394 cdns,phy-input-delay-mmc-ddr = <3>;
395 cdns,phy-dll-delay-sdclk = <21>;
396 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
400 compatible = "socionext,uniphier-sdhc";
402 reg = <0x5a400000 0x800>;
403 interrupts = <0 76 4>;
404 pinctrl-names = "default";
405 pinctrl-0 = <&pinctrl_sd>;
406 clocks = <&sd_clk 0>;
407 reset-names = "host";
408 resets = <&sd_rst 0>;
414 compatible = "socionext,uniphier-ld20-soc-glue",
415 "simple-mfd", "syscon";
416 reg = <0x5f800000 0x2000>;
420 compatible = "socionext,uniphier-ld20-pinctrl";
426 compatible = "simple-mfd", "syscon";
427 reg = <0x5fc20000 0x200>;
430 gic: interrupt-controller@5fe00000 {
431 compatible = "arm,gic-v3";
432 reg = <0x5fe00000 0x10000>, /* GICD */
433 <0x5fe80000 0x80000>; /* GICR */
434 interrupt-controller;
435 #interrupt-cells = <3>;
436 interrupts = <1 9 4>;
440 compatible = "socionext,uniphier-ld20-sysctrl",
441 "simple-mfd", "syscon";
442 reg = <0x61840000 0x10000>;
445 compatible = "socionext,uniphier-ld20-clock";
450 compatible = "socionext,uniphier-ld20-reset";
456 compatible = "socionext,uniphier-ld20-dwc3";
457 reg = <0x65b00000 0x1000>;
458 #address-cells = <1>;
461 pinctrl-names = "default";
462 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>,
463 <&pinctrl_usb2>, <&pinctrl_usb3>;
465 compatible = "snps,dwc3";
466 reg = <0x65a00000 0x10000>;
467 interrupts = <0 134 4>;
472 nand: nand@68000000 {
473 compatible = "socionext,uniphier-denali-nand-v5b";
475 reg-names = "nand_data", "denali_reg";
476 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
477 interrupts = <0 65 4>;
478 pinctrl-names = "default";
479 pinctrl-0 = <&pinctrl_nand>;
480 clocks = <&sys_clk 2>;
481 nand-ecc-strength = <8>;
486 /include/ "uniphier-pinctrl.dtsi"