arch/arm/dts/uniphier-ld20.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
   2 //
   3 // Device Tree Source for UniPhier LD20 SoC
   4 //
   5 // Copyright (C) 2015-2016 Socionext Inc.
   6 //   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   7
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/gpio/uniphier-gpio.h>
  10 #include <dt-bindings/thermal/thermal.h>
  11
  12 /memreserve/ 0x80000000 0x02000000;
  13
  14 / {
  15         compatible = "socionext,uniphier-ld20";
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18         interrupt-parent = <&gic>;
  19
  20         cpus {
  21                 #address-cells = <2>;
  22                 #size-cells = <0>;
  23
  24                 cpu-map {
  25                         cluster0 {
  26                                 core0 {
  27                                         cpu = <&cpu0>;
  28                                 };
  29                                 core1 {
  30                                         cpu = <&cpu1>;
  31                                 };
  32                         };
  33
  34                         cluster1 {
  35                                 core0 {
  36                                         cpu = <&cpu2>;
  37                                 };
  38                                 core1 {
  39                                         cpu = <&cpu3>;
  40                                 };
  41                         };
  42                 };
  43
  44                 cpu0: cpu@0 {
  45                         device_type = "cpu";
  46                         compatible = "arm,cortex-a72", "arm,armv8";
  47                         reg = <0 0x000>;
  48                         clocks = <&sys_clk 32>;
  49                         enable-method = "psci";
  50                         operating-points-v2 = <&cluster0_opp>;
  51                         #cooling-cells = <2>;
  52                 };
  53
  54                 cpu1: cpu@1 {
  55                         device_type = "cpu";
  56                         compatible = "arm,cortex-a72", "arm,armv8";
  57                         reg = <0 0x001>;
  58                         clocks = <&sys_clk 32>;
  59                         enable-method = "psci";
  60                         operating-points-v2 = <&cluster0_opp>;
  61                 };
  62
  63                 cpu2: cpu@100 {
  64                         device_type = "cpu";
  65                         compatible = "arm,cortex-a53", "arm,armv8";
  66                         reg = <0 0x100>;
  67                         clocks = <&sys_clk 33>;
  68                         enable-method = "psci";
  69                         operating-points-v2 = <&cluster1_opp>;
  70                         #cooling-cells = <2>;
  71                 };
  72
  73                 cpu3: cpu@101 {
  74                         device_type = "cpu";
  75                         compatible = "arm,cortex-a53", "arm,armv8";
  76                         reg = <0 0x101>;
  77                         clocks = <&sys_clk 33>;
  78                         enable-method = "psci";
  79                         operating-points-v2 = <&cluster1_opp>;
  80                 };
  81         };
  82
  83         cluster0_opp: opp-table0 {
  84                 compatible = "operating-points-v2";
  85                 opp-shared;
  86
  87                 opp-250000000 {
  88                         opp-hz = /bits/ 64 <250000000>;
  89                         clock-latency-ns = <300>;
  90                 };
  91                 opp-275000000 {
  92                         opp-hz = /bits/ 64 <275000000>;
  93                         clock-latency-ns = <300>;
  94                 };
  95                 opp-500000000 {
  96                         opp-hz = /bits/ 64 <500000000>;
  97                         clock-latency-ns = <300>;
  98                 };
  99                 opp-550000000 {
 100                         opp-hz = /bits/ 64 <550000000>;
 101                         clock-latency-ns = <300>;
 102                 };
 103                 opp-666667000 {
 104                         opp-hz = /bits/ 64 <666667000>;
 105                         clock-latency-ns = <300>;
 106                 };
 107                 opp-733334000 {
 108                         opp-hz = /bits/ 64 <733334000>;
 109                         clock-latency-ns = <300>;
 110                 };
 111                 opp-1000000000 {
 112                         opp-hz = /bits/ 64 <1000000000>;
 113                         clock-latency-ns = <300>;
 114                 };
 115                 opp-1100000000 {
 116                         opp-hz = /bits/ 64 <1100000000>;
 117                         clock-latency-ns = <300>;
 118                 };
 119         };
 120
 121         cluster1_opp: opp-table1 {
 122                 compatible = "operating-points-v2";
 123                 opp-shared;
 124
 125                 opp-250000000 {
 126                         opp-hz = /bits/ 64 <250000000>;
 127                         clock-latency-ns = <300>;
 128                 };
 129                 opp-275000000 {
 130                         opp-hz = /bits/ 64 <275000000>;
 131                         clock-latency-ns = <300>;
 132                 };
 133                 opp-500000000 {
 134                         opp-hz = /bits/ 64 <500000000>;
 135                         clock-latency-ns = <300>;
 136                 };
 137                 opp-550000000 {
 138                         opp-hz = /bits/ 64 <550000000>;
 139                         clock-latency-ns = <300>;
 140                 };
 141                 opp-666667000 {
 142                         opp-hz = /bits/ 64 <666667000>;
 143                         clock-latency-ns = <300>;
 144                 };
 145                 opp-733334000 {
 146                         opp-hz = /bits/ 64 <733334000>;
 147                         clock-latency-ns = <300>;
 148                 };
 149                 opp-1000000000 {
 150                         opp-hz = /bits/ 64 <1000000000>;
 151                         clock-latency-ns = <300>;
 152                 };
 153                 opp-1100000000 {
 154                         opp-hz = /bits/ 64 <1100000000>;
 155                         clock-latency-ns = <300>;
 156                 };
 157         };
 158
 159         psci {
 160                 compatible = "arm,psci-1.0";
 161                 method = "smc";
 162         };
 163
 164         clocks {
 165                 refclk: ref {
 166                         compatible = "fixed-clock";
 167                         #clock-cells = <0>;
 168                         clock-frequency = <25000000>;
 169                 };
 170         };
 171
 172         emmc_pwrseq: emmc-pwrseq {
 173                 compatible = "mmc-pwrseq-emmc";
 174                 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>;
 175         };
 176
 177         timer {
 178                 compatible = "arm,armv8-timer";
 179                 interrupts = <1 13 4>,
 180                              <1 14 4>,
 181                              <1 11 4>,
 182                              <1 10 4>;
 183         };
 184
 185         thermal-zones {
 186                 cpu-thermal {
 187                         polling-delay-passive = <250>;  /* 250ms */
 188                         polling-delay = <1000>;         /* 1000ms */
 189                         thermal-sensors = <&pvtctl>;
 190
 191                         trips {
 192                                 cpu_crit: cpu-crit {
 193                                         temperature = <110000>; /* 110C */
 194                                         hysteresis = <2000>;
 195                                         type = "critical";
 196                                 };
 197                                 cpu_alert: cpu-alert {
 198                                         temperature = <100000>; /* 100C */
 199                                         hysteresis = <2000>;
 200                                         type = "passive";
 201                                 };
 202                         };
 203
 204                         cooling-maps {
 205                                 map0 {
 206                                         trip = <&cpu_alert>;
 207                                         cooling-device = <&cpu0
 208                                             THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 209                                 };
 210                                 map1 {
 211                                         trip = <&cpu_alert>;
 212                                         cooling-device = <&cpu2
 213                                             THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 214                                 };
 215                         };
 216                 };
 217         };
 218
 219         soc@0 {
 220                 compatible = "simple-bus";
 221                 #address-cells = <1>;
 222                 #size-cells = <1>;
 223                 ranges = <0 0 0 0xffffffff>;
 224
 225                 serial0: serial@54006800 {
 226                         compatible = "socionext,uniphier-uart";
 227                         status = "disabled";
 228                         reg = <0x54006800 0x40>;
 229                         interrupts = <0 33 4>;
 230                         pinctrl-names = "default";
 231                         pinctrl-0 = <&pinctrl_uart0>;
 232                         clocks = <&peri_clk 0>;
 233                         clock-frequency = <58820000>;
 234                         resets = <&peri_rst 0>;
 235                 };
 236
 237                 serial1: serial@54006900 {
 238                         compatible = "socionext,uniphier-uart";
 239                         status = "disabled";
 240                         reg = <0x54006900 0x40>;
 241                         interrupts = <0 35 4>;
 242                         pinctrl-names = "default";
 243                         pinctrl-0 = <&pinctrl_uart1>;
 244                         clocks = <&peri_clk 1>;
 245                         clock-frequency = <58820000>;
 246                         resets = <&peri_rst 1>;
 247                 };
 248
 249                 serial2: serial@54006a00 {
 250                         compatible = "socionext,uniphier-uart";
 251                         status = "disabled";
 252                         reg = <0x54006a00 0x40>;
 253                         interrupts = <0 37 4>;
 254                         pinctrl-names = "default";
 255                         pinctrl-0 = <&pinctrl_uart2>;
 256                         clocks = <&peri_clk 2>;
 257                         clock-frequency = <58820000>;
 258                         resets = <&peri_rst 2>;
 259                 };
 260
 261                 serial3: serial@54006b00 {
 262                         compatible = "socionext,uniphier-uart";
 263                         status = "disabled";
 264                         reg = <0x54006b00 0x40>;
 265                         interrupts = <0 177 4>;
 266                         pinctrl-names = "default";
 267                         pinctrl-0 = <&pinctrl_uart3>;
 268                         clocks = <&peri_clk 3>;
 269                         clock-frequency = <58820000>;
 270                         resets = <&peri_rst 3>;
 271                 };
 272
 273                 gpio: gpio@55000000 {
 274                         compatible = "socionext,uniphier-gpio";
 275                         reg = <0x55000000 0x200>;
 276                         interrupt-parent = <&aidet>;
 277                         interrupt-controller;
 278                         #interrupt-cells = <2>;
 279                         gpio-controller;
 280                         #gpio-cells = <2>;
 281                         gpio-ranges = <&pinctrl 0 0 0>,
 282                                       <&pinctrl 96 0 0>,
 283                                       <&pinctrl 160 0 0>;
 284                         gpio-ranges-group-names = "gpio_range0",
 285                                                   "gpio_range1",
 286                                                   "gpio_range2";
 287                         ngpios = <205>;
 288                         socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
 289                                                      <21 217 3>;
 290                 };
 291
 292                 audio@56000000 {
 293                         compatible = "socionext,uniphier-ld20-aio";
 294                         reg = <0x56000000 0x80000>;
 295                         interrupts = <0 144 4>;
 296                         pinctrl-names = "default";
 297                         pinctrl-0 = <&pinctrl_aout1>,
 298                                     <&pinctrl_aoutiec1>;
 299                         clock-names = "aio";
 300                         clocks = <&sys_clk 40>;
 301                         reset-names = "aio";
 302                         resets = <&sys_rst 40>;
 303                         #sound-dai-cells = <1>;
 304                         socionext,syscon = <&soc_glue>;
 305
 306                         i2s_port0: port@0 {
 307                                 i2s_hdmi: endpoint {
 308                                 };
 309                         };
 310
 311                         i2s_port1: port@1 {
 312                                 i2s_pcmin2: endpoint {
 313                                 };
 314                         };
 315
 316                         i2s_port2: port@2 {
 317                                 i2s_line: endpoint {
 318                                         dai-format = "i2s";
 319                                         remote-endpoint = <&evea_line>;
 320                                 };
 321                         };
 322
 323                         i2s_port3: port@3 {
 324                                 i2s_hpcmout1: endpoint {
 325                                 };
 326                         };
 327
 328                         i2s_port4: port@4 {
 329                                 i2s_hp: endpoint {
 330                                         dai-format = "i2s";
 331                                         remote-endpoint = <&evea_hp>;
 332                                 };
 333                         };
 334
 335                         spdif_port0: port@5 {
 336                                 spdif_hiecout1: endpoint {
 337                                 };
 338                         };
 339
 340                         src_port0: port@6 {
 341                                 i2s_epcmout2: endpoint {
 342                                 };
 343                         };
 344
 345                         src_port1: port@7 {
 346                                 i2s_epcmout3: endpoint {
 347                                 };
 348                         };
 349
 350                         comp_spdif_port0: port@8 {
 351                                 comp_spdif_hiecout1: endpoint {
 352                                 };
 353                         };
 354                 };
 355
 356                 codec@57900000 {
 357                         compatible = "socionext,uniphier-evea";
 358                         reg = <0x57900000 0x1000>;
 359                         clock-names = "evea", "exiv";
 360                         clocks = <&sys_clk 41>, <&sys_clk 42>;
 361                         reset-names = "evea", "exiv", "adamv";
 362                         resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>;
 363                         #sound-dai-cells = <1>;
 364
 365                         port@0 {
 366                                 evea_line: endpoint {
 367                                         remote-endpoint = <&i2s_line>;
 368                                 };
 369                         };
 370
 371                         port@1 {
 372                                 evea_hp: endpoint {
 373                                         remote-endpoint = <&i2s_hp>;
 374                                 };
 375                         };
 376                 };
 377
 378                 adamv@57920000 {
 379                         compatible = "socionext,uniphier-ld20-adamv",
 380                                      "simple-mfd", "syscon";
 381                         reg = <0x57920000 0x1000>;
 382
 383                         adamv_rst: reset {
 384                                 compatible = "socionext,uniphier-ld20-adamv-reset";
 385                                 #reset-cells = <1>;
 386                         };
 387                 };
 388
 389                 i2c0: i2c@58780000 {
 390                         compatible = "socionext,uniphier-fi2c";
 391                         status = "disabled";
 392                         reg = <0x58780000 0x80>;
 393                         #address-cells = <1>;
 394                         #size-cells = <0>;
 395                         interrupts = <0 41 4>;
 396                         pinctrl-names = "default";
 397                         pinctrl-0 = <&pinctrl_i2c0>;
 398                         clocks = <&peri_clk 4>;
 399                         resets = <&peri_rst 4>;
 400                         clock-frequency = <100000>;
 401                 };
 402
 403                 i2c1: i2c@58781000 {
 404                         compatible = "socionext,uniphier-fi2c";
 405                         status = "disabled";
 406                         reg = <0x58781000 0x80>;
 407                         #address-cells = <1>;
 408                         #size-cells = <0>;
 409                         interrupts = <0 42 4>;
 410                         pinctrl-names = "default";
 411                         pinctrl-0 = <&pinctrl_i2c1>;
 412                         clocks = <&peri_clk 5>;
 413                         resets = <&peri_rst 5>;
 414                         clock-frequency = <100000>;
 415                 };
 416
 417                 i2c2: i2c@58782000 {
 418                         compatible = "socionext,uniphier-fi2c";
 419                         reg = <0x58782000 0x80>;
 420                         #address-cells = <1>;
 421                         #size-cells = <0>;
 422                         interrupts = <0 43 4>;
 423                         clocks = <&peri_clk 6>;
 424                         resets = <&peri_rst 6>;
 425                         clock-frequency = <400000>;
 426                 };
 427
 428                 i2c3: i2c@58783000 {
 429                         compatible = "socionext,uniphier-fi2c";
 430                         status = "disabled";
 431                         reg = <0x58783000 0x80>;
 432                         #address-cells = <1>;
 433                         #size-cells = <0>;
 434                         interrupts = <0 44 4>;
 435                         pinctrl-names = "default";
 436                         pinctrl-0 = <&pinctrl_i2c3>;
 437                         clocks = <&peri_clk 7>;
 438                         resets = <&peri_rst 7>;
 439                         clock-frequency = <100000>;
 440                 };
 441
 442                 i2c4: i2c@58784000 {
 443                         compatible = "socionext,uniphier-fi2c";
 444                         status = "disabled";
 445                         reg = <0x58784000 0x80>;
 446                         #address-cells = <1>;
 447                         #size-cells = <0>;
 448                         interrupts = <0 45 4>;
 449                         pinctrl-names = "default";
 450                         pinctrl-0 = <&pinctrl_i2c4>;
 451                         clocks = <&peri_clk 8>;
 452                         resets = <&peri_rst 8>;
 453                         clock-frequency = <100000>;
 454                 };
 455
 456                 i2c5: i2c@58785000 {
 457                         compatible = "socionext,uniphier-fi2c";
 458                         reg = <0x58785000 0x80>;
 459                         #address-cells = <1>;
 460                         #size-cells = <0>;
 461                         interrupts = <0 25 4>;
 462                         clocks = <&peri_clk 9>;
 463                         resets = <&peri_rst 9>;
 464                         clock-frequency = <400000>;
 465                 };
 466
 467                 system_bus: system-bus@58c00000 {
 468                         compatible = "socionext,uniphier-system-bus";
 469                         status = "disabled";
 470                         reg = <0x58c00000 0x400>;
 471                         #address-cells = <2>;
 472                         #size-cells = <1>;
 473                         pinctrl-names = "default";
 474                         pinctrl-0 = <&pinctrl_system_bus>;
 475                 };
 476
 477                 smpctrl@59801000 {
 478                         compatible = "socionext,uniphier-smpctrl";
 479                         reg = <0x59801000 0x400>;
 480                 };
 481
 482                 sdctrl@59810000 {
 483                         compatible = "socionext,uniphier-ld20-sdctrl",
 484                                      "simple-mfd", "syscon";
 485                         reg = <0x59810000 0x400>;
 486
 487                         sd_clk: clock {
 488                                 compatible = "socionext,uniphier-ld20-sd-clock";
 489                                 #clock-cells = <1>;
 490                         };
 491
 492                         sd_rst: reset {
 493                                 compatible = "socionext,uniphier-ld20-sd-reset";
 494                                 #reset-cells = <1>;
 495                         };
 496                 };
 497
 498                 perictrl@59820000 {
 499                         compatible = "socionext,uniphier-ld20-perictrl",
 500                                      "simple-mfd", "syscon";
 501                         reg = <0x59820000 0x200>;
 502
 503                         peri_clk: clock {
 504                                 compatible = "socionext,uniphier-ld20-peri-clock";
 505                                 #clock-cells = <1>;
 506                         };
 507
 508                         peri_rst: reset {
 509                                 compatible = "socionext,uniphier-ld20-peri-reset";
 510                                 #reset-cells = <1>;
 511                         };
 512                 };
 513
 514                 emmc: sdhc@5a000000 {
 515                         compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
 516                         reg = <0x5a000000 0x400>;
 517                         interrupts = <0 78 4>;
 518                         pinctrl-names = "default";
 519                         pinctrl-0 = <&pinctrl_emmc_1v8>;
 520                         clocks = <&sys_clk 4>;
 521                         resets = <&sys_rst 4>;
 522                         bus-width = <8>;
 523                         mmc-ddr-1_8v;
 524                         mmc-hs200-1_8v;
 525                         mmc-pwrseq = <&emmc_pwrseq>;
 526                         cdns,phy-input-delay-legacy = <4>;
 527                         cdns,phy-input-delay-mmc-highspeed = <2>;
 528                         cdns,phy-input-delay-mmc-ddr = <3>;
 529                         cdns,phy-dll-delay-sdclk = <21>;
 530                         cdns,phy-dll-delay-sdclk-hsmmc = <21>;
 531                 };
 532
 533                 sd: sdhc@5a400000 {
 534                         compatible = "socionext,uniphier-sdhc";
 535                         status = "disabled";
 536                         reg = <0x5a400000 0x800>;
 537                         interrupts = <0 76 4>;
 538                         pinctrl-names = "default";
 539                         pinctrl-0 = <&pinctrl_sd>;
 540                         clocks = <&sd_clk 0>;
 541                         reset-names = "host";
 542                         resets = <&sd_rst 0>;
 543                         bus-width = <4>;
 544                         cap-sd-highspeed;
 545                 };
 546
 547                 soc_glue: soc-glue@5f800000 {
 548                         compatible = "socionext,uniphier-ld20-soc-glue",
 549                                      "simple-mfd", "syscon";
 550                         reg = <0x5f800000 0x2000>;
 551
 552                         pinctrl: pinctrl {
 553                                 compatible = "socionext,uniphier-ld20-pinctrl";
 554                         };
 555                 };
 556
 557                 soc-glue@5f900000 {
 558                         compatible = "socionext,uniphier-ld20-soc-glue-debug",
 559                                      "simple-mfd";
 560                         #address-cells = <1>;
 561                         #size-cells = <1>;
 562                         ranges = <0 0x5f900000 0x2000>;
 563
 564                         efuse@100 {
 565                                 compatible = "socionext,uniphier-efuse";
 566                                 reg = <0x100 0x28>;
 567                         };
 568
 569                         efuse@200 {
 570                                 compatible = "socionext,uniphier-efuse";
 571                                 reg = <0x200 0x68>;
 572                         };
 573                 };
 574
 575                 aidet: aidet@5fc20000 {
 576                         compatible = "socionext,uniphier-ld20-aidet";
 577                         reg = <0x5fc20000 0x200>;
 578                         interrupt-controller;
 579                         #interrupt-cells = <2>;
 580                 };
 581
 582                 gic: interrupt-controller@5fe00000 {
 583                         compatible = "arm,gic-v3";
 584                         reg = <0x5fe00000 0x10000>,     /* GICD */
 585                               <0x5fe80000 0x80000>;     /* GICR */
 586                         interrupt-controller;
 587                         #interrupt-cells = <3>;
 588                         interrupts = <1 9 4>;
 589                 };
 590
 591                 sysctrl@61840000 {
 592                         compatible = "socionext,uniphier-ld20-sysctrl",
 593                                      "simple-mfd", "syscon";
 594                         reg = <0x61840000 0x10000>;
 595
 596                         sys_clk: clock {
 597                                 compatible = "socionext,uniphier-ld20-clock";
 598                                 #clock-cells = <1>;
 599                         };
 600
 601                         sys_rst: reset {
 602                                 compatible = "socionext,uniphier-ld20-reset";
 603                                 #reset-cells = <1>;
 604                         };
 605
 606                         watchdog {
 607                                 compatible = "socionext,uniphier-wdt";
 608                         };
 609
 610                         pvtctl: pvtctl {
 611                                 compatible = "socionext,uniphier-ld20-thermal";
 612                                 interrupts = <0 3 4>;
 613                                 #thermal-sensor-cells = <0>;
 614                                 socionext,tmod-calibration = <0x0f22 0x68ee>;
 615                         };
 616                 };
 617
 618                 eth: ethernet@65000000 {
 619                         compatible = "socionext,uniphier-ld20-ave4";
 620                         status = "disabled";
 621                         reg = <0x65000000 0x8500>;
 622                         interrupts = <0 66 4>;
 623                         pinctrl-names = "default";
 624                         pinctrl-0 = <&pinctrl_ether_rgmii>;
 625                         clocks = <&sys_clk 6>;
 626                         resets = <&sys_rst 6>;
 627                         phy-mode = "rgmii";
 628                         local-mac-address = [00 00 00 00 00 00];
 629
 630                         mdio: mdio {
 631                                 #address-cells = <1>;
 632                                 #size-cells = <0>;
 633                         };
 634                 };
 635
 636                 usb: usb@65b00000 {
 637                         compatible = "socionext,uniphier-ld20-dwc3";
 638                         reg = <0x65b00000 0x1000>;
 639                         #address-cells = <1>;
 640                         #size-cells = <1>;
 641                         ranges;
 642                         pinctrl-names = "default";
 643                         pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>,
 644                                     <&pinctrl_usb2>, <&pinctrl_usb3>;
 645                         dwc3@65a00000 {
 646                                 compatible = "snps,dwc3";
 647                                 reg = <0x65a00000 0x10000>;
 648                                 interrupts = <0 134 4>;
 649                                 dr_mode = "host";
 650                                 tx-fifo-resize;
 651                         };
 652                 };
 653
 654                 nand: nand@68000000 {
 655                         compatible = "socionext,uniphier-denali-nand-v5b";
 656                         status = "disabled";
 657                         reg-names = "nand_data", "denali_reg";
 658                         reg = <0x68000000 0x20>, <0x68100000 0x1000>;
 659                         interrupts = <0 65 4>;
 660                         pinctrl-names = "default";
 661                         pinctrl-0 = <&pinctrl_nand>;
 662                         clocks = <&sys_clk 2>;
 663                         resets = <&sys_rst 2>;
 664                 };
 665         };
 666 };
 667
 668 #include "uniphier-pinctrl.dtsi"
 669
 670 &pinctrl_aout1 {
 671         drive-strength = <4>;   /* default: 3.5mA */
 672
 673         ao1dacck {
 674                 pins = "AO1DACCK";
 675                 drive-strength = <5>;   /* 5mA */
 676         };
 677 };
 678
 679 &pinctrl_aoutiec1 {
 680         drive-strength = <4>;   /* default: 3.5mA */
 681
 682         ao1arc {
 683                 pins = "AO1ARC";
 684                 drive-strength = <11>;  /* 11mA */
 685         };
 686 };