2 * Device Tree Source for the R-Car Gen3 ULCB board
4 * Copyright (C) 2016 Renesas Electronics Corp.
5 * Copyright (C) 2016 Cogent Embedded, Inc.
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/input/input.h>
16 model = "Renesas R-Car Gen3 ULCB board";
24 stdout-path = "serial0:115200n8";
28 compatible = "renesas,ulcb-cpld";
30 gpio-sck = <&gpio6 8 0>;
31 gpio-mosi = <&gpio6 7 0>;
32 gpio-miso = <&gpio6 10 0>;
33 gpio-sstbz = <&gpio2 3 0>;
36 audio_clkout: audio-clkout {
38 * This is same as <&rcar_sound 0>
39 * but needed to avoid cs2000/rcar_sound probe dead-lock
41 compatible = "fixed-clock";
43 clock-frequency = <11289600>;
47 compatible = "gpio-keys";
53 debounce-interval = <20>;
54 gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
59 compatible = "gpio-leds";
62 gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;
65 gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>;
69 reg_1p8v: regulator0 {
70 compatible = "regulator-fixed";
71 regulator-name = "fixed-1.8V";
72 regulator-min-microvolt = <1800000>;
73 regulator-max-microvolt = <1800000>;
78 reg_3p3v: regulator1 {
79 compatible = "regulator-fixed";
80 regulator-name = "fixed-3.3V";
81 regulator-min-microvolt = <3300000>;
82 regulator-max-microvolt = <3300000>;
88 compatible = "simple-audio-card";
90 simple-audio-card,format = "left_j";
91 simple-audio-card,bitclock-master = <&sndcpu>;
92 simple-audio-card,frame-master = <&sndcpu>;
94 sndcpu: simple-audio-card,cpu {
95 sound-dai = <&rcar_sound>;
98 sndcodec: simple-audio-card,codec {
99 sound-dai = <&ak4613>;
103 vcc_sdhi0: regulator-vcc-sdhi0 {
104 compatible = "regulator-fixed";
106 regulator-name = "SDHI0 Vcc";
107 regulator-min-microvolt = <3300000>;
108 regulator-max-microvolt = <3300000>;
110 gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
114 vccq_sdhi0: regulator-vccq-sdhi0 {
115 compatible = "regulator-gpio";
117 regulator-name = "SDHI0 VccQ";
118 regulator-min-microvolt = <1800000>;
119 regulator-max-microvolt = <3300000>;
121 gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
128 compatible = "fixed-clock";
130 clock-frequency = <24576000>;
135 clock-frequency = <22579200>;
139 pinctrl-0 = <&avb_pins>;
140 pinctrl-names = "default";
141 renesas,no-ether-link;
142 phy-handle = <&phy0>;
143 reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
146 phy0: ethernet-phy@0 {
147 rxc-skew-ps = <1500>;
149 interrupt-parent = <&gpio2>;
150 interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
159 clock-frequency = <16666666>;
163 clock-frequency = <32768>;
167 pinctrl-0 = <&i2c2_pins>;
168 pinctrl-names = "default";
172 clock-frequency = <100000>;
175 compatible = "asahi-kasei,ak4613";
176 #sound-dai-cells = <0>;
178 clocks = <&rcar_sound 3>;
180 asahi-kasei,in1-single-end;
181 asahi-kasei,in2-single-end;
182 asahi-kasei,out1-single-end;
183 asahi-kasei,out2-single-end;
184 asahi-kasei,out3-single-end;
185 asahi-kasei,out4-single-end;
186 asahi-kasei,out5-single-end;
187 asahi-kasei,out6-single-end;
190 cs2000: clk-multiplier@4f {
192 compatible = "cirrus,cs2000-cp";
194 clocks = <&audio_clkout>, <&x12_clk>;
195 clock-names = "clk_in", "ref_clk";
197 assigned-clocks = <&cs2000>;
198 assigned-clock-rates = <24576000>; /* 1/1 divide */
211 pinctrl-0 = <&scif_clk_pins>;
212 pinctrl-names = "default";
216 groups = "avb_link", "avb_phy_int", "avb_mdc",
223 drive-strength = <24>;
227 pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0",
228 "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3";
229 drive-strength = <12>;
239 groups = "scif2_data_a";
243 scif_clk_pins: scif_clk {
244 groups = "scif_clk_a";
245 function = "scif_clk";
249 groups = "sdhi0_data4", "sdhi0_ctrl";
251 power-source = <3300>;
254 sdhi0_pins_uhs: sd0_uhs {
255 groups = "sdhi0_data4", "sdhi0_ctrl";
257 power-source = <1800>;
261 groups = "sdhi2_data8", "sdhi2_ctrl";
263 power-source = <1800>;
266 sdhi2_pins_uhs: sd2_uhs {
267 groups = "sdhi2_data8", "sdhi2_ctrl";
269 power-source = <1800>;
273 groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
277 sound_clk_pins: sound-clk {
278 groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a",
279 "audio_clkout_a", "audio_clkout3_a";
280 function = "audio_clk";
290 pinctrl-0 = <&sound_pins &sound_clk_pins>;
291 pinctrl-names = "default";
294 #sound-dai-cells = <0>;
296 /* audio_clkout0/1/2/3 */
298 clock-frequency = <12288000 11289600>;
302 /* update <audio_clk_b> to <cs2000> */
303 clocks = <&cpg CPG_MOD 1005>,
304 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
305 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
306 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
307 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
308 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
309 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
310 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
311 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
312 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
313 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
314 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
315 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
316 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
317 <&audio_clk_a>, <&cs2000>,
319 <&cpg CPG_CORE CPG_AUDIO_CLK_I>;
323 playback = <&ssi0 &src0 &dvc0>;
324 capture = <&ssi1 &src1 &dvc1>;
330 pinctrl-0 = <&scif2_pins>;
331 pinctrl-names = "default";
337 clock-frequency = <14745600>;
341 pinctrl-0 = <&sdhi0_pins>;
342 pinctrl-1 = <&sdhi0_pins_uhs>;
343 pinctrl-names = "default", "state_uhs";
345 vmmc-supply = <&vcc_sdhi0>;
346 vqmmc-supply = <&vccq_sdhi0>;
347 cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
354 /* used for on-board 8bit eMMC */
355 pinctrl-0 = <&sdhi2_pins>;
356 pinctrl-1 = <&sdhi2_pins_uhs>;
357 pinctrl-names = "default", "state_uhs";
359 vmmc-supply = <®_3p3v>;
360 vqmmc-supply = <®_1p8v>;
372 pinctrl-0 = <&usb1_pins>;
373 pinctrl-names = "default";