3 #include "tegra30.dtsi"
6 model = "Toradex Apalis T30";
7 compatible = "toradex,apalis_t30", "nvidia,tegra30";
14 i2c0 = "/i2c@7000d000";
15 i2c1 = "/i2c@7000c000";
16 i2c2 = "/i2c@7000c500";
17 i2c3 = "/i2c@7000c700";
18 mmc0 = "/sdhci@78000600";
19 mmc1 = "/sdhci@78000400";
20 mmc2 = "/sdhci@78000000";
21 spi0 = "/spi@7000d400";
22 spi1 = "/spi@7000dc00";
23 spi2 = "/spi@7000de00";
24 spi3 = "/spi@7000da00";
25 usb0 = "/usb@7d000000";
26 usb1 = "/usb@7d004000";
27 usb2 = "/usb@7d008000";
31 device_type = "memory";
32 reg = <0x80000000 0x40000000>;
35 pcie-controller@00003000 {
37 avdd-pexa-supply = <&vdd2_reg>;
38 vdd-pexa-supply = <&vdd2_reg>;
39 avdd-pexb-supply = <&vdd2_reg>;
40 vdd-pexb-supply = <&vdd2_reg>;
41 avdd-pex-pll-supply = <&vdd2_reg>;
42 avdd-plle-supply = <&ldo6_reg>;
43 vddio-pex-ctl-supply = <&sys_3v3_reg>;
44 hvdd-pex-supply = <&sys_3v3_reg>;
46 /* Apalis Type Specific 4 Lane PCIe */
48 /* TS_DIFF1/2/3/4 left disabled */
49 nvidia,num-lanes = <4>;
54 /* PCIE1_RX/TX left disabled */
55 nvidia,num-lanes = <1>;
58 /* I210 Gigabit Ethernet Controller (On-module) */
61 nvidia,num-lanes = <1>;
66 * GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier
71 clock-frequency = <400000>;
74 /* GEN2_I2C: unused */
77 * CAM_I2C: I2C3_SDA/SCL on MXM3 pin 201/203 (e.g. camera sensor on
82 clock-frequency = <400000>;
85 /* DDC: I2C2_SDA/SCL on MXM3 pin 205/207 (e.g. display EDID) */
88 clock-frequency = <10000>;
92 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
93 * touch screen controller
97 clock-frequency = <100000>;
100 compatible = "ti,tps65911";
103 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
104 #interrupt-cells = <2>;
105 interrupt-controller;
107 ti,system-power-controller;
112 vcc1-supply = <&sys_3v3_reg>;
113 vcc2-supply = <&sys_3v3_reg>;
114 vcc3-supply = <&vio_reg>;
115 vcc4-supply = <&sys_3v3_reg>;
116 vcc5-supply = <&sys_3v3_reg>;
117 vcc6-supply = <&vio_reg>;
118 vcc7-supply = <&charge_pump_5v0_reg>;
119 vccio-supply = <&sys_3v3_reg>;
122 #address-cells = <1>;
125 /* SW1: +V1.35_VDDIO_DDR */
127 regulator-name = "vddio_ddr_1v35";
128 regulator-min-microvolt = <1350000>;
129 regulator-max-microvolt = <1350000>;
136 "vdd_pexa,vdd_pexb,vdd_sata";
137 regulator-min-microvolt = <1050000>;
138 regulator-max-microvolt = <1050000>;
141 /* SW CTRL: +V1.0_VDD_CPU */
142 vddctrl_reg: vddctrl {
143 regulator-name = "vdd_cpu,vdd_sys";
144 regulator-min-microvolt = <1150000>;
145 regulator-max-microvolt = <1150000>;
151 regulator-name = "vdd_1v8_gen";
152 regulator-min-microvolt = <1800000>;
153 regulator-max-microvolt = <1800000>;
160 * EN_+V3.3 switching via FET:
161 * +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN
162 * see also v3_3 fixed supply
165 regulator-name = "en_3v3";
166 regulator-min-microvolt = <3300000>;
167 regulator-max-microvolt = <3300000>;
174 "avdd_dsi_csi,pwrdet_mipi";
175 regulator-min-microvolt = <1200000>;
176 regulator-max-microvolt = <1200000>;
181 regulator-name = "vdd_rtc";
182 regulator-min-microvolt = <1200000>;
183 regulator-max-microvolt = <1200000>;
189 * only required for analog RGB
192 regulator-name = "avdd_vdac";
193 regulator-min-microvolt = <2800000>;
194 regulator-max-microvolt = <2800000>;
199 * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V
200 * but LDO6 can't set voltage in 50mV
204 regulator-name = "avdd_plle";
205 regulator-min-microvolt = <1100000>;
206 regulator-max-microvolt = <1100000>;
211 regulator-name = "avdd_pll";
212 regulator-min-microvolt = <1200000>;
213 regulator-max-microvolt = <1200000>;
217 /* +V1.0_VDD_DDR_HS */
219 regulator-name = "vdd_ddr_hs";
220 regulator-min-microvolt = <1000000>;
221 regulator-max-microvolt = <1000000>;
228 /* SPI1: Apalis SPI1 */
231 spi-max-frequency = <25000000>;
237 spi-max-frequency = <25000000>;
240 /* SPI5: Apalis SPI2 */
243 spi-max-frequency = <25000000>;
249 spi-max-frequency = <25000000>;
256 cd-gpios = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_LOW>;
263 cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>;
272 /* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */
277 nvidia,vbus-gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>;
280 /* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */
284 nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
287 /* EHCI instance 2: USB3_DP/N -> USBH3_DP/N */
291 nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
295 compatible = "simple-bus";
296 #address-cells = <1>;
300 compatible = "fixed-clock";
303 clock-frequency = <32768>;
306 compatible = "fixed-clock";
309 clock-frequency = <16000000>;
310 clock-output-names = "clk16m";
315 compatible = "simple-bus";
316 #address-cells = <1>;
319 sys_3v3_reg: regulator@100 {
320 compatible = "regulator-fixed";
322 regulator-name = "3v3";
323 regulator-min-microvolt = <3300000>;
324 regulator-max-microvolt = <3300000>;
328 charge_pump_5v0_reg: regulator@101 {
329 compatible = "regulator-fixed";
331 regulator-name = "5v0";
332 regulator-min-microvolt = <5000000>;
333 regulator-max-microvolt = <5000000>;