arch/arm/dts/tegra124.dtsi

   1 #include <dt-bindings/clock/tegra124-car.h>
   2 #include <dt-bindings/gpio/tegra-gpio.h>
   3 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5
   6 #include "skeleton.dtsi"
   7
   8 / {
   9         compatible = "nvidia,tegra124";
  10
  11         tegra_car: clock@60006000 {
  12                 compatible = "nvidia,tegra124-car";
  13                 reg = <0x60006000 0x1000>;
  14                 #clock-cells = <1>;
  15         };
  16
  17         apbdma: dma@60020000 {
  18                 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
  19                 reg = <0x60020000 0x1400>;
  20                 interrupts = <0 104 0x04
  21                               0 105 0x04
  22                               0 106 0x04
  23                               0 107 0x04
  24                               0 108 0x04
  25                               0 109 0x04
  26                               0 110 0x04
  27                               0 111 0x04
  28                               0 112 0x04
  29                               0 113 0x04
  30                               0 114 0x04
  31                               0 115 0x04
  32                               0 116 0x04
  33                               0 117 0x04
  34                               0 118 0x04
  35                               0 119 0x04
  36                               0 128 0x04
  37                               0 129 0x04
  38                               0 130 0x04
  39                               0 131 0x04
  40                               0 132 0x04
  41                               0 133 0x04
  42                               0 134 0x04
  43                               0 135 0x04
  44                               0 136 0x04
  45                               0 137 0x04
  46                               0 138 0x04
  47                               0 139 0x04
  48                               0 140 0x04
  49                               0 141 0x04
  50                               0 142 0x04
  51                               0 143 0x04>;
  52         };
  53
  54         gpio: gpio@6000d000 {
  55                 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
  56                 reg = <0x6000d000 0x1000>;
  57                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
  58                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
  59                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
  60                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
  61                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
  62                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
  63                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
  64                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
  65                 #gpio-cells = <2>;
  66                 gpio-controller;
  67                 #interrupt-cells = <2>;
  68                 interrupt-controller;
  69         };
  70
  71         i2c@7000c000 {
  72                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
  73                 reg = <0x7000c000 0x100>;
  74                 interrupts = <0 38 0x04>;
  75                 #address-cells = <1>;
  76                 #size-cells = <0>;
  77                 clocks = <&tegra_car 12>;
  78                 status = "disabled";
  79         };
  80
  81         i2c@7000c400 {
  82                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
  83                 reg = <0x7000c400 0x100>;
  84                 interrupts = <0 84 0x04>;
  85                 #address-cells = <1>;
  86                 #size-cells = <0>;
  87                 clocks = <&tegra_car 54>;
  88                 status = "disabled";
  89         };
  90
  91         i2c@7000c500 {
  92                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
  93                 reg = <0x7000c500 0x100>;
  94                 interrupts = <0 92 0x04>;
  95                 #address-cells = <1>;
  96                 #size-cells = <0>;
  97                 clocks = <&tegra_car 67>;
  98                 status = "disabled";
  99         };
 100
 101         i2c@7000c700 {
 102                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 103                 reg = <0x7000c700 0x100>;
 104                 interrupts = <0 120 0x04>;
 105                 #address-cells = <1>;
 106                 #size-cells = <0>;
 107                 clocks = <&tegra_car 103>;
 108                 status = "disabled";
 109         };
 110
 111         i2c@7000d000 {
 112                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 113                 reg = <0x7000d000 0x100>;
 114                 interrupts = <0 53 0x04>;
 115                 #address-cells = <1>;
 116                 #size-cells = <0>;
 117                 clocks = <&tegra_car 47>;
 118                 status = "disabled";
 119         };
 120
 121         i2c@7000d100 {
 122                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 123                 reg = <0x7000d100 0x100>;
 124                 interrupts = <0 53 0x04>;
 125                 #address-cells = <1>;
 126                 #size-cells = <0>;
 127                 clocks = <&tegra_car 47>;
 128                 status = "disabled";
 129         };
 130
 131         uarta: serial@70006000 {
 132                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 133                 reg = <0x70006000 0x40>;
 134                 reg-shift = <2>;
 135                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 136                 clocks = <&tegra_car TEGRA124_CLK_UARTA>;
 137                 resets = <&tegra_car 6>;
 138                 reset-names = "serial";
 139                 dmas = <&apbdma 8>, <&apbdma 8>;
 140                 dma-names = "rx", "tx";
 141                 status = "disabled";
 142         };
 143
 144         uartb: serial@70006040 {
 145                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 146                 reg = <0x70006040 0x40>;
 147                 reg-shift = <2>;
 148                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 149                 clocks = <&tegra_car TEGRA124_CLK_UARTB>;
 150                 resets = <&tegra_car 7>;
 151                 reset-names = "serial";
 152                 dmas = <&apbdma 9>, <&apbdma 9>;
 153                 dma-names = "rx", "tx";
 154                 status = "disabled";
 155         };
 156
 157         uartc: serial@70006200 {
 158                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 159                 reg = <0x70006200 0x40>;
 160                 reg-shift = <2>;
 161                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 162                 clocks = <&tegra_car TEGRA124_CLK_UARTC>;
 163                 resets = <&tegra_car 55>;
 164                 reset-names = "serial";
 165                 dmas = <&apbdma 10>, <&apbdma 10>;
 166                 dma-names = "rx", "tx";
 167                 status = "disabled";
 168         };
 169
 170         uartd: serial@70006300 {
 171                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 172                 reg = <0x70006300 0x40>;
 173                 reg-shift = <2>;
 174                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 175                 clocks = <&tegra_car TEGRA124_CLK_UARTD>;
 176                 resets = <&tegra_car 65>;
 177                 reset-names = "serial";
 178                 dmas = <&apbdma 19>, <&apbdma 19>;
 179                 dma-names = "rx", "tx";
 180                 status = "disabled";
 181         };
 182
 183         uarte: serial@70006400 {
 184                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 185                 reg = <0x70006400 0x40>;
 186                 reg-shift = <2>;
 187                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 188                 clocks = <&tegra_car TEGRA124_CLK_UARTE>;
 189                 resets = <&tegra_car 66>;
 190                 reset-names = "serial";
 191                 dmas = <&apbdma 20>, <&apbdma 20>;
 192                 dma-names = "rx", "tx";
 193                 status = "disabled";
 194         };
 195
 196         pwm: pwm@7000a000 {
 197                 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
 198                 reg = <0x7000a000 0x100>;
 199                 #pwm-cells = <2>;
 200                 clocks = <&tegra_car TEGRA124_CLK_PWM>;
 201                 resets = <&tegra_car 17>;
 202                 reset-names = "pwm";
 203                 status = "disabled";
 204         };
 205
 206         spi@7000d400 {
 207                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 208                 reg = <0x7000d400 0x200>;
 209                 interrupts = <0 59 0x04>;
 210                 nvidia,dma-request-selector = <&apbdma 15>;
 211                 #address-cells = <1>;
 212                 #size-cells = <0>;
 213                 status = "disabled";
 214                 clocks = <&tegra_car 41>;
 215         };
 216
 217         spi@7000d600 {
 218                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 219                 reg = <0x7000d600 0x200>;
 220                 interrupts = <0 82 0x04>;
 221                 nvidia,dma-request-selector = <&apbdma 16>;
 222                 #address-cells = <1>;
 223                 #size-cells = <0>;
 224                 status = "disabled";
 225                 clocks = <&tegra_car 44>;
 226         };
 227
 228         spi@7000d800 {
 229                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 230                 reg = <0x7000d800 0x200>;
 231                 interrupts = <0 83 0x04>;
 232                 nvidia,dma-request-selector = <&apbdma 17>;
 233                 #address-cells = <1>;
 234                 #size-cells = <0>;
 235                 status = "disabled";
 236                 clocks = <&tegra_car 46>;
 237         };
 238
 239         spi@7000da00 {
 240                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 241                 reg = <0x7000da00 0x200>;
 242                 interrupts = <0 93 0x04>;
 243                 nvidia,dma-request-selector = <&apbdma 18>;
 244                 #address-cells = <1>;
 245                 #size-cells = <0>;
 246                 status = "disabled";
 247                 clocks = <&tegra_car 68>;
 248         };
 249
 250         spi@7000dc00 {
 251                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 252                 reg = <0x7000dc00 0x200>;
 253                 interrupts = <0 94 0x04>;
 254                 nvidia,dma-request-selector = <&apbdma 27>;
 255                 #address-cells = <1>;
 256                 #size-cells = <0>;
 257                 status = "disabled";
 258                 clocks = <&tegra_car 104>;
 259         };
 260
 261         spi@7000de00 {
 262                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 263                 reg = <0x7000de00 0x200>;
 264                 interrupts = <0 79 0x04>;
 265                 nvidia,dma-request-selector = <&apbdma 28>;
 266                 #address-cells = <1>;
 267                 #size-cells = <0>;
 268                 status = "disabled";
 269                 clocks = <&tegra_car 105>;
 270         };
 271
 272         sdhci@700b0000 {
 273                 compatible = "nvidia,tegra124-sdhci";
 274                 reg = <0x700b0000 0x200>;
 275                 interrupts = <0 14 0x04>;
 276                 clocks = <&tegra_car 14>;
 277                 status = "disabled";
 278         };
 279
 280         sdhci@700b0200 {
 281                 compatible = "nvidia,tegra124-sdhci";
 282                 reg = <0x700b0200 0x200>;
 283                 interrupts = <0 15 0x04>;
 284                 clocks = <&tegra_car 9>;
 285                 status = "disabled";
 286         };
 287
 288         sdhci@700b0400 {
 289                 compatible = "nvidia,tegra124-sdhci";
 290                 reg = <0x700b0400 0x200>;
 291                 interrupts = <0 19 0x04>;
 292                 clocks = <&tegra_car 69>;
 293                 status = "disabled";
 294         };
 295
 296         sdhci@700b0600 {
 297                 compatible = "nvidia,tegra124-sdhci";
 298                 reg = <0x700b0600 0x200>;
 299                 interrupts = <0 31 0x04>;
 300                 clocks = <&tegra_car 15>;
 301                 status = "disabled";
 302         };
 303
 304         ahub@70300000 {
 305                 compatible = "nvidia,tegra124-ahub";
 306                 reg = <0x70300000 0x200>,
 307                       <0x70300800 0x800>,
 308                       <0x70300200 0x600>;
 309                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 310                 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
 311                          <&tegra_car TEGRA124_CLK_APBIF>;
 312                 clock-names = "d_audio", "apbif";
 313                 resets = <&tegra_car 106>, /* d_audio */
 314                          <&tegra_car 107>, /* apbif */
 315                          <&tegra_car 30>,  /* i2s0 */
 316                          <&tegra_car 11>,  /* i2s1 */
 317                          <&tegra_car 18>,  /* i2s2 */
 318                          <&tegra_car 101>, /* i2s3 */
 319                          <&tegra_car 102>, /* i2s4 */
 320                          <&tegra_car 108>, /* dam0 */
 321                          <&tegra_car 109>, /* dam1 */
 322                          <&tegra_car 110>, /* dam2 */
 323                          <&tegra_car 10>,  /* spdif */
 324                          <&tegra_car 153>, /* amx */
 325                          <&tegra_car 185>, /* amx1 */
 326                          <&tegra_car 154>, /* adx */
 327                          <&tegra_car 180>, /* adx1 */
 328                          <&tegra_car 186>, /* afc0 */
 329                          <&tegra_car 187>, /* afc1 */
 330                          <&tegra_car 188>, /* afc2 */
 331                          <&tegra_car 189>, /* afc3 */
 332                          <&tegra_car 190>, /* afc4 */
 333                          <&tegra_car 191>; /* afc5 */
 334                 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 335                               "i2s3", "i2s4", "dam0", "dam1", "dam2",
 336                               "spdif", "amx", "amx1", "adx", "adx1",
 337                               "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
 338                 dmas = <&apbdma 1>, <&apbdma 1>,
 339                        <&apbdma 2>, <&apbdma 2>,
 340                        <&apbdma 3>, <&apbdma 3>,
 341                        <&apbdma 4>, <&apbdma 4>,
 342                        <&apbdma 6>, <&apbdma 6>,
 343                        <&apbdma 7>, <&apbdma 7>,
 344                        <&apbdma 12>, <&apbdma 12>,
 345                        <&apbdma 13>, <&apbdma 13>,
 346                        <&apbdma 14>, <&apbdma 14>,
 347                        <&apbdma 29>, <&apbdma 29>;
 348                 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
 349                             "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
 350                             "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
 351                             "rx9", "tx9";
 352                 ranges;
 353                 #address-cells = <1>;
 354                 #size-cells = <1>;
 355
 356                 tegra_i2s0: i2s@70301000 {
 357                         compatible = "nvidia,tegra124-i2s";
 358                         reg = <0x70301000 0x100>;
 359                         nvidia,ahub-cif-ids = <4 4>;
 360                         clocks = <&tegra_car TEGRA124_CLK_I2S0>;
 361                         resets = <&tegra_car 30>;
 362                         reset-names = "i2s";
 363                         status = "disabled";
 364                 };
 365
 366                 tegra_i2s1: i2s@70301100 {
 367                         compatible = "nvidia,tegra124-i2s";
 368                         reg = <0x70301100 0x100>;
 369                         nvidia,ahub-cif-ids = <5 5>;
 370                         clocks = <&tegra_car TEGRA124_CLK_I2S1>;
 371                         resets = <&tegra_car 11>;
 372                         reset-names = "i2s";
 373                         status = "disabled";
 374                 };
 375
 376                 tegra_i2s2: i2s@70301200 {
 377                         compatible = "nvidia,tegra124-i2s";
 378                         reg = <0x70301200 0x100>;
 379                         nvidia,ahub-cif-ids = <6 6>;
 380                         clocks = <&tegra_car TEGRA124_CLK_I2S2>;
 381                         resets = <&tegra_car 18>;
 382                         reset-names = "i2s";
 383                         status = "disabled";
 384                 };
 385
 386                 tegra_i2s3: i2s@70301300 {
 387                         compatible = "nvidia,tegra124-i2s";
 388                         reg = <0x70301300 0x100>;
 389                         nvidia,ahub-cif-ids = <7 7>;
 390                         clocks = <&tegra_car TEGRA124_CLK_I2S3>;
 391                         resets = <&tegra_car 101>;
 392                         reset-names = "i2s";
 393                         status = "disabled";
 394                 };
 395
 396                 tegra_i2s4: i2s@70301400 {
 397                         compatible = "nvidia,tegra124-i2s";
 398                         reg = <0x70301400 0x100>;
 399                         nvidia,ahub-cif-ids = <8 8>;
 400                         clocks = <&tegra_car TEGRA124_CLK_I2S4>;
 401                         resets = <&tegra_car 102>;
 402                         reset-names = "i2s";
 403                         status = "disabled";
 404                 };
 405         };
 406
 407         usb@7d000000 {
 408                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
 409                 reg = <0x7d000000 0x4000>;
 410                 interrupts = < 52 >;
 411                 phy_type = "utmi";
 412                 clocks = <&tegra_car 22>;       /* PERIPH_ID_USBD */
 413                 status = "disabled";
 414         };
 415
 416         usb@7d004000 {
 417                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
 418                 reg = <0x7d004000 0x4000>;
 419                 interrupts = < 53 >;
 420                 phy_type = "hsic";
 421                 clocks = <&tegra_car 58>;       /* PERIPH_ID_USB2 */
 422                 status = "disabled";
 423         };
 424
 425         usb@7d008000 {
 426                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
 427                 reg = <0x7d008000 0x4000>;
 428                 interrupts = < 129 >;
 429                 phy_type = "utmi";
 430                 clocks = <&tegra_car 59>;       /* PERIPH_ID_USB3 */
 431                 status = "disabled";
 432         };
 433 };