2 * Copyright (c) 2017 - 2018, Linaro Limited. All rights reserved.
4 * SPDX-License-Identifier: BSD-2-Clause-Patent
7 /* These are added for U-Boot to avoid compilation error */
8 #define PcdNetsecEepromBase 0x08080000
9 #define FixedPcdGet32(n) n
14 #define IRQ_TYPE_NONE 0
15 #define IRQ_TYPE_EDGE_RISING 1
16 #define IRQ_TYPE_EDGE_FALLING 2
17 #define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
18 #define IRQ_TYPE_LEVEL_HIGH 4
19 #define IRQ_TYPE_LEVEL_LOW 8
21 #define GPIO_ACTIVE_HIGH 0
22 #define GPIO_ACTIVE_LOW 1
27 interrupt-parent = <&gic>;
35 stdout-path = "serial0:115200n8";
44 compatible = "arm,cortex-a53","arm,armv8";
46 enable-method = "psci";
47 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
51 compatible = "arm,cortex-a53","arm,armv8";
53 enable-method = "psci";
54 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
58 compatible = "arm,cortex-a53","arm,armv8";
60 enable-method = "psci";
61 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
65 compatible = "arm,cortex-a53","arm,armv8";
67 enable-method = "psci";
68 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
72 compatible = "arm,cortex-a53","arm,armv8";
74 enable-method = "psci";
75 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
79 compatible = "arm,cortex-a53","arm,armv8";
81 enable-method = "psci";
82 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
86 compatible = "arm,cortex-a53","arm,armv8";
88 enable-method = "psci";
89 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
93 compatible = "arm,cortex-a53","arm,armv8";
95 enable-method = "psci";
96 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
100 compatible = "arm,cortex-a53","arm,armv8";
102 enable-method = "psci";
103 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
107 compatible = "arm,cortex-a53","arm,armv8";
109 enable-method = "psci";
110 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
114 compatible = "arm,cortex-a53","arm,armv8";
116 enable-method = "psci";
117 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
121 compatible = "arm,cortex-a53","arm,armv8";
123 enable-method = "psci";
124 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
128 compatible = "arm,cortex-a53","arm,armv8";
130 enable-method = "psci";
131 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
135 compatible = "arm,cortex-a53","arm,armv8";
137 enable-method = "psci";
138 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
142 compatible = "arm,cortex-a53","arm,armv8";
144 enable-method = "psci";
145 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
149 compatible = "arm,cortex-a53","arm,armv8";
151 enable-method = "psci";
152 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
156 compatible = "arm,cortex-a53","arm,armv8";
158 enable-method = "psci";
159 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
163 compatible = "arm,cortex-a53","arm,armv8";
165 enable-method = "psci";
166 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
170 compatible = "arm,cortex-a53","arm,armv8";
172 enable-method = "psci";
173 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
177 compatible = "arm,cortex-a53","arm,armv8";
179 enable-method = "psci";
180 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
184 compatible = "arm,cortex-a53","arm,armv8";
186 enable-method = "psci";
187 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
191 compatible = "arm,cortex-a53","arm,armv8";
193 enable-method = "psci";
194 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
198 compatible = "arm,cortex-a53","arm,armv8";
200 enable-method = "psci";
201 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
205 compatible = "arm,cortex-a53","arm,armv8";
207 enable-method = "psci";
208 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
312 entry-method = "arm,psci";
314 CPU_SLEEP_0: cpu-sleep-0 {
315 compatible = "arm,idle-state";
316 arm,psci-suspend-param = <0x0010000>;
317 entry-latency-us = <300>;
318 exit-latency-us = <1200>;
319 min-residency-us = <2000>;
323 CLUSTER_SLEEP_0: cluster-sleep-0 {
324 compatible = "arm,idle-state";
325 arm,psci-suspend-param = <0x1010000>;
326 entry-latency-us = <400>;
327 exit-latency-us = <1200>;
328 min-residency-us = <2500>;
333 gic: interrupt-controller@30000000 {
334 compatible = "arm,gic-v3";
335 reg = <0x0 0x30000000 0x0 0x10000>, // GICD
336 <0x0 0x30400000 0x0 0x300000>, // GICR
337 <0x0 0x2c000000 0x0 0x2000>, // GICC
338 <0x0 0x2c010000 0x0 0x1000>, // GICH
339 <0x0 0x2c020000 0x0 0x10000>; // GICV
340 #interrupt-cells = <3>;
341 #address-cells = <2>;
344 interrupt-controller;
345 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
347 its: gic-its@30020000 {
348 compatible = "arm,gic-v3-its";
349 reg = <0x0 0x30020000 0x0 0x20000>;
352 socionext,synquacer-pre-its = <0x58000000 0x200000>;
357 compatible = "arm,armv8-timer";
358 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, // secure
359 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, // non-secure
360 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, // virtual
361 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; // HYP
364 mmio-timer@2a810000 {
365 compatible = "arm,armv7-timer-mem";
366 reg = <0x0 0x2a810000 0x0 0x10000>;
367 #address-cells = <2>;
372 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
373 reg = <0x0 0x2a830000 0x0 0x10000>;
378 compatible = "arm,cortex-a53-pmu";
379 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
383 compatible = "arm,psci-1.0";
387 clk_uart: refclk62500khz {
388 compatible = "fixed-clock";
390 clock-frequency = <62500000>;
391 clock-output-names = "uartclk";
394 clk_apb: refclk100mhz {
395 compatible = "fixed-clock";
397 clock-frequency = <100000000>;
398 clock-output-names = "apb_pclk";
401 soc_uart0: uart@2a400000 {
402 compatible = "arm,pl011", "arm,primecell";
403 reg = <0x0 0x2a400000 0x0 0x1000>;
404 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
405 clocks = <&clk_uart>, <&clk_apb>;
406 clock-names = "uartclk", "apb_pclk";
409 fuart: uart@51040000 {
410 compatible = "snps,dw-apb-uart";
411 reg = <0x0 0x51040000 0x0 0x1000>;
412 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
413 clocks = <&clk_uart>, <&clk_apb>;
414 clock-names = "baudclk", "apb_pclk";
419 clk_netsec: refclk250mhz {
420 compatible = "fixed-clock";
421 clock-frequency = <250000000>;
425 netsec: ethernet@522d0000 {
426 compatible = "socionext,synquacer-netsec";
427 reg = <0 0x522d0000 0x0 0x10000>,
428 <0 FixedPcdGet32 (PcdNetsecEepromBase) 0x0 0x10000>;
429 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
430 clocks = <&clk_netsec>;
431 clock-names = "phy_ref_clk";
433 max-frame-size = <9000>;
434 phy-handle = <&phy_netsec>;
438 #address-cells = <1>;
443 smmu: iommu@582c0000 {
444 compatible = "arm,mmu-500", "arm,smmu-v2";
445 reg = <0x0 0x582c0000 0x0 0x10000>;
446 #global-interrupts = <1>;
447 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
448 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
449 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
454 pcie0: pcie@60000000 {
455 compatible = "socionext,synquacer-pcie-ecam", "snps,dw-pcie-ecam";
457 reg = <0x0 0x60000000 0x0 0x7f00000>;
458 bus-range = <0x0 0x7e>;
459 #address-cells = <3>;
461 ranges = <0x1000000 0x00 0x00000000 0x00 0x67f00000 0x0 0x00010000>,
462 <0x2000000 0x00 0x68000000 0x00 0x68000000 0x0 0x08000000>,
463 <0x3000000 0x3e 0x00000000 0x3e 0x00000000 0x1 0x00000000>;
465 #interrupt-cells = <0x1>;
466 interrupt-map-mask = <0x0 0x0 0x0 0x0>;
467 interrupt-map = <0x0 0x0 0x0 0x0 &gic 0x0 0x0 GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
469 msi-map = <0x000 &its 0x0 0x7f00>;
474 pcie1: pcie@70000000 {
475 compatible = "socionext,synquacer-pcie-ecam", "snps,dw-pcie-ecam";
477 reg = <0x0 0x70000000 0x0 0x7f00000>;
478 bus-range = <0x0 0x7e>;
479 #address-cells = <3>;
481 ranges = <0x1000000 0x00 0x00000000 0x00 0x77f00000 0x0 0x00010000>,
482 <0x2000000 0x00 0x78000000 0x00 0x78000000 0x0 0x08000000>,
483 <0x3000000 0x3f 0x00000000 0x3f 0x00000000 0x1 0x00000000>;
485 #interrupt-cells = <0x1>;
486 interrupt-map-mask = <0x0 0x0 0x0 0x0>;
487 interrupt-map = <0x0 0x0 0x0 0x0 &gic 0x0 0x0 GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
489 msi-map = <0x0 &its 0x10000 0x7f00>;
494 gpio: gpio@51000000 {
495 compatible = "socionext,synquacer-gpio", "fujitsu,mb86s70-gpio";
496 reg = <0x0 0x51000000 0x0 0x100>;
503 exiu: interrupt-controller@510c0000 {
504 compatible = "socionext,synquacer-exiu";
505 reg = <0x0 0x510c0000 0x0 0x20>;
506 interrupt-controller;
507 interrupt-parent = <&gic>;
508 #interrupt-cells = <3>;
509 socionext,spi-base = <112>;
512 clk_alw_b_0: bclk200 {
513 compatible = "fixed-clock";
515 clock-frequency = <200000000>;
516 clock-output-names = "sd_bclk";
519 clk_alw_c_0: sd4clk800 {
520 compatible = "fixed-clock";
522 clock-frequency = <800000000>;
523 clock-output-names = "sd_sd4clk";
526 sdhci: sdhci@52300000 {
527 compatible = "socionext,synquacer-sdhci", "fujitsu,mb86s70-sdhci-3.0";
528 reg = <0 0x52300000 0x0 0x1000>;
529 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
530 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
533 fujitsu,cmd-dat-delay-select;
534 clocks = <&clk_alw_c_0 &clk_alw_b_0>;
535 clock-names = "core", "iface";
540 clk_alw_1_8: spi_ihclk {
541 compatible = "fixed-clock";
543 clock-frequency = <125000000>;
544 clock-output-names = "iHCLK";
548 compatible = "socionext,synquacer-spi";
549 reg = <0x0 0x54810000 0x0 0x1000>;
550 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
551 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
552 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
553 clocks = <&clk_alw_1_8>;
554 clock-names = "iHCLK";
557 #address-cells = <1>;
563 compatible = "fixed-clock";
565 clock-frequency = <62500000>;
566 clock-output-names = "pclk";
570 compatible = "socionext,synquacer-i2c";
571 reg = <0x0 0x51210000 0x0 0x1000>;
572 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
574 clock-names = "pclk";
575 clock-frequency = <400000>;
576 #address-cells = <1>;
580 tpm: tpm_tis@10000000 {
581 compatible = "socionext,synquacer-tpm-mmio";
582 reg = <0x0 0x10000000 0x0 0x5000>;
588 compatible = "linaro,optee-tz";
595 #include "synquacer-sc2a11-caches.dtsi"