arch/arm/dts/sun8i-a23.dtsi

   1 /*
   2  * Copyright 2014 Chen-Yu Tsai
   3  *
   4  * Chen-Yu Tsai <wens@csie.org>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  *     You should have received a copy of the GNU General Public
  22  *     License along with this file; if not, write to the Free
  23  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  24  *     MA 02110-1301 USA
  25  *
  26  * Or, alternatively,
  27  *
  28  *  b) Permission is hereby granted, free of charge, to any person
  29  *     obtaining a copy of this software and associated documentation
  30  *     files (the "Software"), to deal in the Software without
  31  *     restriction, including without limitation the rights to use,
  32  *     copy, modify, merge, publish, distribute, sublicense, and/or
  33  *     sell copies of the Software, and to permit persons to whom the
  34  *     Software is furnished to do so, subject to the following
  35  *     conditions:
  36  *
  37  *     The above copyright notice and this permission notice shall be
  38  *     included in all copies or substantial portions of the Software.
  39  *
  40  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  41  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  42  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  43  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  44  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  45  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  46  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  47  *     OTHER DEALINGS IN THE SOFTWARE.
  48  */
  49
  50 #include "skeleton.dtsi"
  51
  52 #include <dt-bindings/interrupt-controller/arm-gic.h>
  53
  54 #include <dt-bindings/pinctrl/sun4i-a10.h>
  55
  56 / {
  57         interrupt-parent = <&gic>;
  58
  59         chosen {
  60                 #address-cells = <1>;
  61                 #size-cells = <1>;
  62                 ranges;
  63
  64                 framebuffer@0 {
  65                         compatible = "allwinner,simple-framebuffer",
  66                                      "simple-framebuffer";
  67                         allwinner,pipeline = "de_be0-lcd0";
  68                         clocks = <&pll6 0>;
  69                         status = "disabled";
  70                 };
  71         };
  72
  73         timer {
  74                 compatible = "arm,armv7-timer";
  75                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  76                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  77                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  78                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  79                 clock-frequency = <24000000>;
  80                 arm,cpu-registers-not-fw-configured;
  81         };
  82
  83         cpus {
  84                 enable-method = "allwinner,sun8i-a23";
  85                 #address-cells = <1>;
  86                 #size-cells = <0>;
  87
  88                 cpu@0 {
  89                         compatible = "arm,cortex-a7";
  90                         device_type = "cpu";
  91                         reg = <0>;
  92                 };
  93
  94                 cpu@1 {
  95                         compatible = "arm,cortex-a7";
  96                         device_type = "cpu";
  97                         reg = <1>;
  98                 };
  99         };
 100
 101         memory {
 102                 reg = <0x40000000 0x40000000>;
 103         };
 104
 105         clocks {
 106                 #address-cells = <1>;
 107                 #size-cells = <1>;
 108                 ranges;
 109
 110                 osc24M: osc24M_clk {
 111                         #clock-cells = <0>;
 112                         compatible = "fixed-clock";
 113                         clock-frequency = <24000000>;
 114                         clock-output-names = "osc24M";
 115                 };
 116
 117                 osc32k: osc32k_clk {
 118                         #clock-cells = <0>;
 119                         compatible = "fixed-clock";
 120                         clock-frequency = <32768>;
 121                         clock-output-names = "osc32k";
 122                 };
 123
 124                 pll1: clk@01c20000 {
 125                         #clock-cells = <0>;
 126                         compatible = "allwinner,sun8i-a23-pll1-clk";
 127                         reg = <0x01c20000 0x4>;
 128                         clocks = <&osc24M>;
 129                         clock-output-names = "pll1";
 130                 };
 131
 132                 /* dummy clock until actually implemented */
 133                 pll5: pll5_clk {
 134                         #clock-cells = <0>;
 135                         compatible = "fixed-clock";
 136                         clock-frequency = <0>;
 137                         clock-output-names = "pll5";
 138                 };
 139
 140                 pll6: clk@01c20028 {
 141                         #clock-cells = <1>;
 142                         compatible = "allwinner,sun6i-a31-pll6-clk";
 143                         reg = <0x01c20028 0x4>;
 144                         clocks = <&osc24M>;
 145                         clock-output-names = "pll6", "pll6x2";
 146                 };
 147
 148                 cpu: cpu_clk@01c20050 {
 149                         #clock-cells = <0>;
 150                         compatible = "allwinner,sun4i-a10-cpu-clk";
 151                         reg = <0x01c20050 0x4>;
 152
 153                         /*
 154                          * PLL1 is listed twice here.
 155                          * While it looks suspicious, it's actually documented
 156                          * that way both in the datasheet and in the code from
 157                          * Allwinner.
 158                          */
 159                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
 160                         clock-output-names = "cpu";
 161                 };
 162
 163                 axi: axi_clk@01c20050 {
 164                         #clock-cells = <0>;
 165                         compatible = "allwinner,sun8i-a23-axi-clk";
 166                         reg = <0x01c20050 0x4>;
 167                         clocks = <&cpu>;
 168                         clock-output-names = "axi";
 169                 };
 170
 171                 ahb1: ahb1_clk@01c20054 {
 172                         #clock-cells = <0>;
 173                         compatible = "allwinner,sun6i-a31-ahb1-clk";
 174                         reg = <0x01c20054 0x4>;
 175                         clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
 176                         clock-output-names = "ahb1";
 177                 };
 178
 179                 apb1: apb1_clk@01c20054 {
 180                         #clock-cells = <0>;
 181                         compatible = "allwinner,sun4i-a10-apb0-clk";
 182                         reg = <0x01c20054 0x4>;
 183                         clocks = <&ahb1>;
 184                         clock-output-names = "apb1";
 185                 };
 186
 187                 ahb1_gates: clk@01c20060 {
 188                         #clock-cells = <1>;
 189                         compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
 190                         reg = <0x01c20060 0x8>;
 191                         clocks = <&ahb1>;
 192                         clock-output-names = "ahb1_mipidsi", "ahb1_dma",
 193                                         "ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2",
 194                                         "ahb1_nand", "ahb1_sdram",
 195                                         "ahb1_hstimer", "ahb1_spi0",
 196                                         "ahb1_spi1", "ahb1_otg", "ahb1_ehci",
 197                                         "ahb1_ohci", "ahb1_ve", "ahb1_lcd",
 198                                         "ahb1_csi", "ahb1_be",  "ahb1_fe",
 199                                         "ahb1_gpu", "ahb1_spinlock",
 200                                         "ahb1_drc";
 201                 };
 202
 203                 apb1_gates: clk@01c20068 {
 204                         #clock-cells = <1>;
 205                         compatible = "allwinner,sun8i-a23-apb1-gates-clk";
 206                         reg = <0x01c20068 0x4>;
 207                         clocks = <&apb1>;
 208                         clock-output-names = "apb1_codec", "apb1_pio",
 209                                         "apb1_daudio0", "apb1_daudio1";
 210                 };
 211
 212                 apb2: clk@01c20058 {
 213                         #clock-cells = <0>;
 214                         compatible = "allwinner,sun4i-a10-apb1-clk";
 215                         reg = <0x01c20058 0x4>;
 216                         clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
 217                         clock-output-names = "apb2";
 218                 };
 219
 220                 apb2_gates: clk@01c2006c {
 221                         #clock-cells = <1>;
 222                         compatible = "allwinner,sun8i-a23-apb2-gates-clk";
 223                         reg = <0x01c2006c 0x4>;
 224                         clocks = <&apb2>;
 225                         clock-output-names = "apb2_i2c0", "apb2_i2c1",
 226                                         "apb2_i2c2", "apb2_uart0",
 227                                         "apb2_uart1", "apb2_uart2",
 228                                         "apb2_uart3", "apb2_uart4";
 229                 };
 230
 231                 mmc0_clk: clk@01c20088 {
 232                         #clock-cells = <1>;
 233                         compatible = "allwinner,sun4i-a10-mmc-clk";
 234                         reg = <0x01c20088 0x4>;
 235                         clocks = <&osc24M>, <&pll6 0>;
 236                         clock-output-names = "mmc0",
 237                                              "mmc0_output",
 238                                              "mmc0_sample";
 239                 };
 240
 241                 mmc1_clk: clk@01c2008c {
 242                         #clock-cells = <1>;
 243                         compatible = "allwinner,sun4i-a10-mmc-clk";
 244                         reg = <0x01c2008c 0x4>;
 245                         clocks = <&osc24M>, <&pll6 0>;
 246                         clock-output-names = "mmc1",
 247                                              "mmc1_output",
 248                                              "mmc1_sample";
 249                 };
 250
 251                 mmc2_clk: clk@01c20090 {
 252                         #clock-cells = <1>;
 253                         compatible = "allwinner,sun4i-a10-mmc-clk";
 254                         reg = <0x01c20090 0x4>;
 255                         clocks = <&osc24M>, <&pll6 0>;
 256                         clock-output-names = "mmc2",
 257                                              "mmc2_output",
 258                                              "mmc2_sample";
 259                 };
 260
 261                 mbus_clk: clk@01c2015c {
 262                         #clock-cells = <0>;
 263                         compatible = "allwinner,sun8i-a23-mbus-clk";
 264                         reg = <0x01c2015c 0x4>;
 265                         clocks = <&osc24M>, <&pll6 1>, <&pll5>;
 266                         clock-output-names = "mbus";
 267                 };
 268         };
 269
 270         soc@01c00000 {
 271                 compatible = "simple-bus";
 272                 #address-cells = <1>;
 273                 #size-cells = <1>;
 274                 ranges;
 275
 276                 dma: dma-controller@01c02000 {
 277                         compatible = "allwinner,sun8i-a23-dma";
 278                         reg = <0x01c02000 0x1000>;
 279                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 280                         clocks = <&ahb1_gates 6>;
 281                         resets = <&ahb1_rst 6>;
 282                         #dma-cells = <1>;
 283                 };
 284
 285                 mmc0: mmc@01c0f000 {
 286                         compatible = "allwinner,sun5i-a13-mmc";
 287                         reg = <0x01c0f000 0x1000>;
 288                         clocks = <&ahb1_gates 8>,
 289                                  <&mmc0_clk 0>,
 290                                  <&mmc0_clk 1>,
 291                                  <&mmc0_clk 2>;
 292                         clock-names = "ahb",
 293                                       "mmc",
 294                                       "output",
 295                                       "sample";
 296                         resets = <&ahb1_rst 8>;
 297                         reset-names = "ahb";
 298                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 299                         status = "disabled";
 300                         #address-cells = <1>;
 301                         #size-cells = <0>;
 302                 };
 303
 304                 mmc1: mmc@01c10000 {
 305                         compatible = "allwinner,sun5i-a13-mmc";
 306                         reg = <0x01c10000 0x1000>;
 307                         clocks = <&ahb1_gates 9>,
 308                                  <&mmc1_clk 0>,
 309                                  <&mmc1_clk 1>,
 310                                  <&mmc1_clk 2>;
 311                         clock-names = "ahb",
 312                                       "mmc",
 313                                       "output",
 314                                       "sample";
 315                         resets = <&ahb1_rst 9>;
 316                         reset-names = "ahb";
 317                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 318                         status = "disabled";
 319                         #address-cells = <1>;
 320                         #size-cells = <0>;
 321                 };
 322
 323                 mmc2: mmc@01c11000 {
 324                         compatible = "allwinner,sun5i-a13-mmc";
 325                         reg = <0x01c11000 0x1000>;
 326                         clocks = <&ahb1_gates 10>,
 327                                  <&mmc2_clk 0>,
 328                                  <&mmc2_clk 1>,
 329                                  <&mmc2_clk 2>;
 330                         clock-names = "ahb",
 331                                       "mmc",
 332                                       "output",
 333                                       "sample";
 334                         resets = <&ahb1_rst 10>;
 335                         reset-names = "ahb";
 336                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 337                         status = "disabled";
 338                         #address-cells = <1>;
 339                         #size-cells = <0>;
 340                 };
 341
 342                 pio: pinctrl@01c20800 {
 343                         compatible = "allwinner,sun8i-a23-pinctrl";
 344                         reg = <0x01c20800 0x400>;
 345                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 346                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 347                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 348                         clocks = <&apb1_gates 5>;
 349                         gpio-controller;
 350                         interrupt-controller;
 351                         #address-cells = <1>;
 352                         #size-cells = <0>;
 353                         #gpio-cells = <3>;
 354
 355                         uart0_pins_a: uart0@0 {
 356                                 allwinner,pins = "PF2", "PF4";
 357                                 allwinner,function = "uart0";
 358                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 359                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 360                         };
 361
 362                         mmc0_pins_a: mmc0@0 {
 363                                 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
 364                                 allwinner,function = "mmc0";
 365                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 366                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 367                         };
 368
 369                         mmc1_pins_a: mmc1@0 {
 370                                 allwinner,pins = "PG0","PG1","PG2","PG3","PG4","PG5";
 371                                 allwinner,function = "mmc1";
 372                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 373                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 374                         };
 375
 376                         i2c0_pins_a: i2c0@0 {
 377                                 allwinner,pins = "PH2", "PH3";
 378                                 allwinner,function = "i2c0";
 379                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 380                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 381                         };
 382
 383                         i2c1_pins_a: i2c1@0 {
 384                                 allwinner,pins = "PH4", "PH5";
 385                                 allwinner,function = "i2c1";
 386                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 387                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 388                         };
 389
 390                         i2c2_pins_a: i2c2@0 {
 391                                 allwinner,pins = "PE12", "PE13";
 392                                 allwinner,function = "i2c2";
 393                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 394                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 395                         };
 396                 };
 397
 398                 ahb1_rst: reset@01c202c0 {
 399                         #reset-cells = <1>;
 400                         compatible = "allwinner,sun6i-a31-clock-reset";
 401                         reg = <0x01c202c0 0xc>;
 402                 };
 403
 404                 apb1_rst: reset@01c202d0 {
 405                         #reset-cells = <1>;
 406                         compatible = "allwinner,sun6i-a31-clock-reset";
 407                         reg = <0x01c202d0 0x4>;
 408                 };
 409
 410                 apb2_rst: reset@01c202d8 {
 411                         #reset-cells = <1>;
 412                         compatible = "allwinner,sun6i-a31-clock-reset";
 413                         reg = <0x01c202d8 0x4>;
 414                 };
 415
 416                 timer@01c20c00 {
 417                         compatible = "allwinner,sun4i-a10-timer";
 418                         reg = <0x01c20c00 0xa0>;
 419                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 420                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 421                         clocks = <&osc24M>;
 422                 };
 423
 424                 wdt0: watchdog@01c20ca0 {
 425                         compatible = "allwinner,sun6i-a31-wdt";
 426                         reg = <0x01c20ca0 0x20>;
 427                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 428                 };
 429
 430                 lradc: lradc@01c22800 {
 431                         compatible = "allwinner,sun4i-a10-lradc-keys";
 432                         reg = <0x01c22800 0x100>;
 433                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 434                         status = "disabled";
 435                 };
 436
 437                 uart0: serial@01c28000 {
 438                         compatible = "snps,dw-apb-uart";
 439                         reg = <0x01c28000 0x400>;
 440                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 441                         reg-shift = <2>;
 442                         reg-io-width = <4>;
 443                         clocks = <&apb2_gates 16>;
 444                         resets = <&apb2_rst 16>;
 445                         dmas = <&dma 6>, <&dma 6>;
 446                         dma-names = "rx", "tx";
 447                         status = "disabled";
 448                 };
 449
 450                 uart1: serial@01c28400 {
 451                         compatible = "snps,dw-apb-uart";
 452                         reg = <0x01c28400 0x400>;
 453                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 454                         reg-shift = <2>;
 455                         reg-io-width = <4>;
 456                         clocks = <&apb2_gates 17>;
 457                         resets = <&apb2_rst 17>;
 458                         dmas = <&dma 7>, <&dma 7>;
 459                         dma-names = "rx", "tx";
 460                         status = "disabled";
 461                 };
 462
 463                 uart2: serial@01c28800 {
 464                         compatible = "snps,dw-apb-uart";
 465                         reg = <0x01c28800 0x400>;
 466                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 467                         reg-shift = <2>;
 468                         reg-io-width = <4>;
 469                         clocks = <&apb2_gates 18>;
 470                         resets = <&apb2_rst 18>;
 471                         dmas = <&dma 8>, <&dma 8>;
 472                         dma-names = "rx", "tx";
 473                         status = "disabled";
 474                 };
 475
 476                 uart3: serial@01c28c00 {
 477                         compatible = "snps,dw-apb-uart";
 478                         reg = <0x01c28c00 0x400>;
 479                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 480                         reg-shift = <2>;
 481                         reg-io-width = <4>;
 482                         clocks = <&apb2_gates 19>;
 483                         resets = <&apb2_rst 19>;
 484                         dmas = <&dma 9>, <&dma 9>;
 485                         dma-names = "rx", "tx";
 486                         status = "disabled";
 487                 };
 488
 489                 uart4: serial@01c29000 {
 490                         compatible = "snps,dw-apb-uart";
 491                         reg = <0x01c29000 0x400>;
 492                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 493                         reg-shift = <2>;
 494                         reg-io-width = <4>;
 495                         clocks = <&apb2_gates 20>;
 496                         resets = <&apb2_rst 20>;
 497                         dmas = <&dma 10>, <&dma 10>;
 498                         dma-names = "rx", "tx";
 499                         status = "disabled";
 500                 };
 501
 502                 i2c0: i2c@01c2ac00 {
 503                         compatible = "allwinner,sun6i-a31-i2c";
 504                         reg = <0x01c2ac00 0x400>;
 505                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 506                         clocks = <&apb2_gates 0>;
 507                         resets = <&apb2_rst 0>;
 508                         status = "disabled";
 509                         #address-cells = <1>;
 510                         #size-cells = <0>;
 511                 };
 512
 513                 i2c1: i2c@01c2b000 {
 514                         compatible = "allwinner,sun6i-a31-i2c";
 515                         reg = <0x01c2b000 0x400>;
 516                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 517                         clocks = <&apb2_gates 1>;
 518                         resets = <&apb2_rst 1>;
 519                         status = "disabled";
 520                         #address-cells = <1>;
 521                         #size-cells = <0>;
 522                 };
 523
 524                 i2c2: i2c@01c2b400 {
 525                         compatible = "allwinner,sun6i-a31-i2c";
 526                         reg = <0x01c2b400 0x400>;
 527                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 528                         clocks = <&apb2_gates 2>;
 529                         resets = <&apb2_rst 2>;
 530                         status = "disabled";
 531                         #address-cells = <1>;
 532                         #size-cells = <0>;
 533                 };
 534
 535                 gic: interrupt-controller@01c81000 {
 536                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 537                         reg = <0x01c81000 0x1000>,
 538                               <0x01c82000 0x1000>,
 539                               <0x01c84000 0x2000>,
 540                               <0x01c86000 0x2000>;
 541                         interrupt-controller;
 542                         #interrupt-cells = <3>;
 543                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 544                 };
 545
 546                 rtc: rtc@01f00000 {
 547                         compatible = "allwinner,sun6i-a31-rtc";
 548                         reg = <0x01f00000 0x54>;
 549                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 550                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 551                 };
 552
 553                 prcm@01f01400 {
 554                         compatible = "allwinner,sun8i-a23-prcm";
 555                         reg = <0x01f01400 0x200>;
 556
 557                         ar100: ar100_clk {
 558                                 compatible = "fixed-factor-clock";
 559                                 #clock-cells = <0>;
 560                                 clock-div = <1>;
 561                                 clock-mult = <1>;
 562                                 clocks = <&osc24M>;
 563                                 clock-output-names = "ar100";
 564                         };
 565
 566                         ahb0: ahb0_clk {
 567                                 compatible = "fixed-factor-clock";
 568                                 #clock-cells = <0>;
 569                                 clock-div = <1>;
 570                                 clock-mult = <1>;
 571                                 clocks = <&ar100>;
 572                                 clock-output-names = "ahb0";
 573                         };
 574
 575                         apb0: apb0_clk {
 576                                 compatible = "allwinner,sun8i-a23-apb0-clk";
 577                                 #clock-cells = <0>;
 578                                 clocks = <&ahb0>;
 579                                 clock-output-names = "apb0";
 580                         };
 581
 582                         apb0_gates: apb0_gates_clk {
 583                                 compatible = "allwinner,sun8i-a23-apb0-gates-clk";
 584                                 #clock-cells = <1>;
 585                                 clocks = <&apb0>;
 586                                 clock-output-names = "apb0_pio", "apb0_timer",
 587                                                 "apb0_rsb", "apb0_uart",
 588                                                 "apb0_i2c";
 589                         };
 590
 591                         apb0_rst: apb0_rst {
 592                                 compatible = "allwinner,sun6i-a31-clock-reset";
 593                                 #reset-cells = <1>;
 594                         };
 595                 };
 596
 597                 cpucfg@01f01c00 {
 598                         compatible = "allwinner,sun8i-a23-cpuconfig";
 599                         reg = <0x01f01c00 0x300>;
 600                 };
 601
 602                 r_uart: serial@01f02800 {
 603                         compatible = "snps,dw-apb-uart";
 604                         reg = <0x01f02800 0x400>;
 605                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 606                         reg-shift = <2>;
 607                         reg-io-width = <4>;
 608                         clocks = <&apb0_gates 4>;
 609                         resets = <&apb0_rst 4>;
 610                         status = "disabled";
 611                 };
 612
 613                 r_pio: pinctrl@01f02c00 {
 614                         compatible = "allwinner,sun8i-a23-r-pinctrl";
 615                         reg = <0x01f02c00 0x400>;
 616                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 617                         clocks = <&apb0_gates 0>;
 618                         resets = <&apb0_rst 0>;
 619                         gpio-controller;
 620                         interrupt-controller;
 621                         #address-cells = <1>;
 622                         #size-cells = <0>;
 623                         #gpio-cells = <3>;
 624
 625                         r_uart_pins_a: r_uart@0 {
 626                                 allwinner,pins = "PL2", "PL3";
 627                                 allwinner,function = "s_uart";
 628                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 629                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 630                         };
 631                 };
 632         };
 633 };