2 * Copyright 2013 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/thermal/thermal.h>
48 #include <dt-bindings/clock/sun6i-a31-ccu.h>
49 #include <dt-bindings/clock/sun6i-rtc.h>
50 #include <dt-bindings/reset/sun6i-a31-ccu.h>
53 interrupt-parent = <&gic>;
66 simplefb_hdmi: framebuffer-lcd0-hdmi {
67 compatible = "allwinner,simple-framebuffer",
69 allwinner,pipeline = "de_be0-lcd0-hdmi";
70 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
71 <&ccu CLK_AHB1_HDMI>, <&ccu CLK_DRAM_BE0>,
72 <&ccu CLK_IEP_DRC0>, <&ccu CLK_BE0>,
73 <&ccu CLK_LCD0_CH1>, <&ccu CLK_HDMI>;
77 simplefb_lcd: framebuffer-lcd0 {
78 compatible = "allwinner,simple-framebuffer",
80 allwinner,pipeline = "de_be0-lcd0";
81 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
82 <&ccu CLK_DRAM_BE0>, <&ccu CLK_IEP_DRC0>,
83 <&ccu CLK_BE0>, <&ccu CLK_LCD0_CH0>;
89 compatible = "arm,armv7-timer";
90 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
91 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
92 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
93 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
94 clock-frequency = <24000000>;
95 arm,cpu-registers-not-fw-configured;
99 enable-method = "allwinner,sun6i-a31";
100 #address-cells = <1>;
104 compatible = "arm,cortex-a7";
107 clocks = <&ccu CLK_CPU>;
108 clock-latency = <244144>; /* 8 32k periods */
115 #cooling-cells = <2>;
119 compatible = "arm,cortex-a7";
122 clocks = <&ccu CLK_CPU>;
123 clock-latency = <244144>; /* 8 32k periods */
130 #cooling-cells = <2>;
134 compatible = "arm,cortex-a7";
137 clocks = <&ccu CLK_CPU>;
138 clock-latency = <244144>; /* 8 32k periods */
145 #cooling-cells = <2>;
149 compatible = "arm,cortex-a7";
152 clocks = <&ccu CLK_CPU>;
153 clock-latency = <244144>; /* 8 32k periods */
160 #cooling-cells = <2>;
167 polling-delay-passive = <250>;
168 polling-delay = <1000>;
169 thermal-sensors = <&rtp>;
173 trip = <&cpu_alert0>;
174 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
175 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
176 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
177 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
182 cpu_alert0: cpu_alert0 {
184 temperature = <70000>;
191 temperature = <100000>;
200 compatible = "arm,cortex-a7-pmu";
201 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
202 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
203 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
204 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
208 #address-cells = <1>;
214 compatible = "fixed-clock";
215 clock-frequency = <24000000>;
216 clock-accuracy = <50000>;
217 clock-output-names = "osc24M";
222 compatible = "fixed-clock";
223 clock-frequency = <32768>;
224 clock-accuracy = <50000>;
225 clock-output-names = "ext_osc32k";
229 * The following two are dummy clocks, placeholders
230 * used in the gmac_tx clock. The gmac driver will
231 * choose one parent depending on the PHY interface
232 * mode, using clk_set_rate auto-reparenting.
234 * The actual TX clock rate is not controlled by the
237 mii_phy_tx_clk: clk-mii-phy-tx {
239 compatible = "fixed-clock";
240 clock-frequency = <25000000>;
241 clock-output-names = "mii_phy_tx";
244 gmac_int_tx_clk: clk-gmac-int-tx {
246 compatible = "fixed-clock";
247 clock-frequency = <125000000>;
248 clock-output-names = "gmac_int_tx";
251 gmac_tx_clk: clk@1c200d0 {
253 compatible = "allwinner,sun7i-a20-gmac-clk";
254 reg = <0x01c200d0 0x4>;
255 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
256 clock-output-names = "gmac_tx";
261 compatible = "allwinner,sun6i-a31-display-engine";
262 allwinner,pipelines = <&fe0>, <&fe1>;
267 compatible = "simple-bus";
268 #address-cells = <1>;
272 dma: dma-controller@1c02000 {
273 compatible = "allwinner,sun6i-a31-dma";
274 reg = <0x01c02000 0x1000>;
275 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
276 clocks = <&ccu CLK_AHB1_DMA>;
277 resets = <&ccu RST_AHB1_DMA>;
281 tcon0: lcd-controller@1c0c000 {
282 compatible = "allwinner,sun6i-a31-tcon";
283 reg = <0x01c0c000 0x1000>;
284 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
286 resets = <&ccu RST_AHB1_LCD0>,
287 <&ccu RST_AHB1_LVDS>;
290 clocks = <&ccu CLK_AHB1_LCD0>,
298 clock-output-names = "tcon0-pixel-clock";
302 #address-cells = <1>;
306 #address-cells = <1>;
310 tcon0_in_drc0: endpoint@0 {
312 remote-endpoint = <&drc0_out_tcon0>;
315 tcon0_in_drc1: endpoint@1 {
317 remote-endpoint = <&drc1_out_tcon0>;
322 #address-cells = <1>;
326 tcon0_out_hdmi: endpoint@1 {
328 remote-endpoint = <&hdmi_in_tcon0>;
329 allwinner,tcon-channel = <1>;
335 tcon1: lcd-controller@1c0d000 {
336 compatible = "allwinner,sun6i-a31-tcon";
337 reg = <0x01c0d000 0x1000>;
338 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
340 resets = <&ccu RST_AHB1_LCD1>,
341 <&ccu RST_AHB1_LVDS>;
342 reset-names = "lcd", "lvds";
343 clocks = <&ccu CLK_AHB1_LCD1>,
351 clock-output-names = "tcon1-pixel-clock";
355 #address-cells = <1>;
359 #address-cells = <1>;
363 tcon1_in_drc0: endpoint@0 {
365 remote-endpoint = <&drc0_out_tcon1>;
368 tcon1_in_drc1: endpoint@1 {
370 remote-endpoint = <&drc1_out_tcon1>;
375 #address-cells = <1>;
379 tcon1_out_hdmi: endpoint@1 {
381 remote-endpoint = <&hdmi_in_tcon1>;
382 allwinner,tcon-channel = <1>;
389 compatible = "allwinner,sun7i-a20-mmc";
390 reg = <0x01c0f000 0x1000>;
391 clocks = <&ccu CLK_AHB1_MMC0>,
393 <&ccu CLK_MMC0_OUTPUT>,
394 <&ccu CLK_MMC0_SAMPLE>;
399 resets = <&ccu RST_AHB1_MMC0>;
401 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
402 pinctrl-names = "default";
403 pinctrl-0 = <&mmc0_pins>;
405 #address-cells = <1>;
410 compatible = "allwinner,sun7i-a20-mmc";
411 reg = <0x01c10000 0x1000>;
412 clocks = <&ccu CLK_AHB1_MMC1>,
414 <&ccu CLK_MMC1_OUTPUT>,
415 <&ccu CLK_MMC1_SAMPLE>;
420 resets = <&ccu RST_AHB1_MMC1>;
422 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
423 pinctrl-names = "default";
424 pinctrl-0 = <&mmc1_pins>;
426 #address-cells = <1>;
431 compatible = "allwinner,sun7i-a20-mmc";
432 reg = <0x01c11000 0x1000>;
433 clocks = <&ccu CLK_AHB1_MMC2>,
435 <&ccu CLK_MMC2_OUTPUT>,
436 <&ccu CLK_MMC2_SAMPLE>;
441 resets = <&ccu RST_AHB1_MMC2>;
443 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
445 #address-cells = <1>;
450 compatible = "allwinner,sun7i-a20-mmc";
451 reg = <0x01c12000 0x1000>;
452 clocks = <&ccu CLK_AHB1_MMC3>,
454 <&ccu CLK_MMC3_OUTPUT>,
455 <&ccu CLK_MMC3_SAMPLE>;
460 resets = <&ccu RST_AHB1_MMC3>;
462 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
464 #address-cells = <1>;
469 compatible = "allwinner,sun6i-a31-hdmi";
470 reg = <0x01c16000 0x1000>;
471 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
472 clocks = <&ccu CLK_AHB1_HDMI>, <&ccu CLK_HDMI>,
474 <&ccu CLK_PLL_VIDEO0_2X>,
475 <&ccu CLK_PLL_VIDEO1_2X>;
476 clock-names = "ahb", "mod", "ddc", "pll-0", "pll-1";
477 resets = <&ccu RST_AHB1_HDMI>;
478 dma-names = "ddc-tx", "ddc-rx", "audio-tx";
479 dmas = <&dma 13>, <&dma 13>, <&dma 14>;
483 #address-cells = <1>;
487 #address-cells = <1>;
491 hdmi_in_tcon0: endpoint@0 {
493 remote-endpoint = <&tcon0_out_hdmi>;
496 hdmi_in_tcon1: endpoint@1 {
498 remote-endpoint = <&tcon1_out_hdmi>;
508 usb_otg: usb@1c19000 {
509 compatible = "allwinner,sun6i-a31-musb";
510 reg = <0x01c19000 0x0400>;
511 clocks = <&ccu CLK_AHB1_OTG>;
512 resets = <&ccu RST_AHB1_OTG>;
513 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
514 interrupt-names = "mc";
517 extcon = <&usbphy 0>;
522 usbphy: phy@1c19400 {
523 compatible = "allwinner,sun6i-a31-usb-phy";
524 reg = <0x01c19400 0x10>,
527 reg-names = "phy_ctrl",
530 clocks = <&ccu CLK_USB_PHY0>,
533 clock-names = "usb0_phy",
536 resets = <&ccu RST_USB_PHY0>,
539 reset-names = "usb0_reset",
547 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
548 reg = <0x01c1a000 0x100>;
549 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
550 clocks = <&ccu CLK_AHB1_EHCI0>;
551 resets = <&ccu RST_AHB1_EHCI0>;
558 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
559 reg = <0x01c1a400 0x100>;
560 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
561 clocks = <&ccu CLK_AHB1_OHCI0>, <&ccu CLK_USB_OHCI0>;
562 resets = <&ccu RST_AHB1_OHCI0>;
569 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
570 reg = <0x01c1b000 0x100>;
571 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
572 clocks = <&ccu CLK_AHB1_EHCI1>;
573 resets = <&ccu RST_AHB1_EHCI1>;
580 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
581 reg = <0x01c1b400 0x100>;
582 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
583 clocks = <&ccu CLK_AHB1_OHCI1>, <&ccu CLK_USB_OHCI1>;
584 resets = <&ccu RST_AHB1_OHCI1>;
591 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
592 reg = <0x01c1c400 0x100>;
593 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
594 clocks = <&ccu CLK_AHB1_OHCI2>, <&ccu CLK_USB_OHCI2>;
595 resets = <&ccu RST_AHB1_OHCI2>;
600 compatible = "allwinner,sun6i-a31-ccu";
601 reg = <0x01c20000 0x400>;
602 clocks = <&osc24M>, <&rtc CLK_OSC32K>;
603 clock-names = "hosc", "losc";
608 pio: pinctrl@1c20800 {
609 compatible = "allwinner,sun6i-a31-pinctrl";
610 reg = <0x01c20800 0x400>;
611 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
612 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
613 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
614 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
615 clocks = <&ccu CLK_APB1_PIO>, <&osc24M>,
617 clock-names = "apb", "hosc", "losc";
619 interrupt-controller;
620 #interrupt-cells = <3>;
623 gmac_gmii_pins: gmac-gmii-pins {
624 pins = "PA0", "PA1", "PA2", "PA3",
625 "PA4", "PA5", "PA6", "PA7",
626 "PA8", "PA9", "PA10", "PA11",
627 "PA12", "PA13", "PA14", "PA15",
628 "PA16", "PA17", "PA18", "PA19",
629 "PA20", "PA21", "PA22", "PA23",
630 "PA24", "PA25", "PA26", "PA27";
633 * data lines in GMII mode run at 125MHz and
634 * might need a higher signal drive strength
636 drive-strength = <30>;
639 gmac_mii_pins: gmac-mii-pins {
640 pins = "PA0", "PA1", "PA2", "PA3",
641 "PA8", "PA9", "PA11",
642 "PA12", "PA13", "PA14", "PA19",
643 "PA20", "PA21", "PA22", "PA23",
644 "PA24", "PA26", "PA27";
648 gmac_rgmii_pins: gmac-rgmii-pins {
649 pins = "PA0", "PA1", "PA2", "PA3",
650 "PA9", "PA10", "PA11",
651 "PA12", "PA13", "PA14", "PA19",
652 "PA20", "PA25", "PA26", "PA27";
655 * data lines in RGMII mode use DDR mode
656 * and need a higher signal drive strength
658 drive-strength = <40>;
661 i2c0_pins: i2c0-pins {
662 pins = "PH14", "PH15";
666 i2c1_pins: i2c1-pins {
667 pins = "PH16", "PH17";
671 i2c2_pins: i2c2-pins {
672 pins = "PH18", "PH19";
676 lcd0_rgb888_pins: lcd0-rgb888-pins {
677 pins = "PD0", "PD1", "PD2", "PD3",
678 "PD4", "PD5", "PD6", "PD7",
679 "PD8", "PD9", "PD10", "PD11",
680 "PD12", "PD13", "PD14", "PD15",
681 "PD16", "PD17", "PD18", "PD19",
682 "PD20", "PD21", "PD22", "PD23",
683 "PD24", "PD25", "PD26", "PD27";
687 mmc0_pins: mmc0-pins {
688 pins = "PF0", "PF1", "PF2",
691 drive-strength = <30>;
695 mmc1_pins: mmc1-pins {
696 pins = "PG0", "PG1", "PG2", "PG3",
699 drive-strength = <30>;
703 mmc2_4bit_pins: mmc2-4bit-pins {
704 pins = "PC6", "PC7", "PC8", "PC9",
707 drive-strength = <30>;
711 mmc2_8bit_emmc_pins: mmc2-8bit-emmc-pins {
712 pins = "PC6", "PC7", "PC8", "PC9",
713 "PC10", "PC11", "PC12",
714 "PC13", "PC14", "PC15",
717 drive-strength = <30>;
721 mmc3_8bit_emmc_pins: mmc3-8bit-emmc-pins {
722 pins = "PC6", "PC7", "PC8", "PC9",
723 "PC10", "PC11", "PC12",
724 "PC13", "PC14", "PC15",
727 drive-strength = <40>;
731 spdif_tx_pin: spdif-tx-pin {
736 uart0_ph_pins: uart0-ph-pins {
737 pins = "PH20", "PH21";
743 compatible = "allwinner,sun4i-a10-timer";
744 reg = <0x01c20c00 0xa0>;
745 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
746 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
747 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
748 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
749 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
750 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
754 wdt1: watchdog@1c20ca0 {
755 compatible = "allwinner,sun6i-a31-wdt";
756 reg = <0x01c20ca0 0x20>;
757 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
761 spdif: spdif@1c21000 {
762 #sound-dai-cells = <0>;
763 compatible = "allwinner,sun6i-a31-spdif";
764 reg = <0x01c21000 0x400>;
765 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
766 clocks = <&ccu CLK_APB1_SPDIF>, <&ccu CLK_SPDIF>;
767 resets = <&ccu RST_APB1_SPDIF>;
768 clock-names = "apb", "spdif";
769 dmas = <&dma 2>, <&dma 2>;
770 dma-names = "rx", "tx";
775 #sound-dai-cells = <0>;
776 compatible = "allwinner,sun6i-a31-i2s";
777 reg = <0x01c22000 0x400>;
778 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
779 clocks = <&ccu CLK_APB1_DAUDIO0>, <&ccu CLK_DAUDIO0>;
780 resets = <&ccu RST_APB1_DAUDIO0>;
781 clock-names = "apb", "mod";
782 dmas = <&dma 3>, <&dma 3>;
783 dma-names = "rx", "tx";
788 #sound-dai-cells = <0>;
789 compatible = "allwinner,sun6i-a31-i2s";
790 reg = <0x01c22400 0x400>;
791 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
792 clocks = <&ccu CLK_APB1_DAUDIO1>, <&ccu CLK_DAUDIO1>;
793 resets = <&ccu RST_APB1_DAUDIO1>;
794 clock-names = "apb", "mod";
795 dmas = <&dma 4>, <&dma 4>;
796 dma-names = "rx", "tx";
800 lradc: lradc@1c22800 {
801 compatible = "allwinner,sun4i-a10-lradc-keys";
802 reg = <0x01c22800 0x100>;
803 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
808 compatible = "allwinner,sun6i-a31-ts";
809 reg = <0x01c25000 0x100>;
810 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
811 #thermal-sensor-cells = <0>;
814 uart0: serial@1c28000 {
815 compatible = "snps,dw-apb-uart";
816 reg = <0x01c28000 0x400>;
817 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
820 clocks = <&ccu CLK_APB2_UART0>;
821 resets = <&ccu RST_APB2_UART0>;
822 dmas = <&dma 6>, <&dma 6>;
823 dma-names = "tx", "rx";
827 uart1: serial@1c28400 {
828 compatible = "snps,dw-apb-uart";
829 reg = <0x01c28400 0x400>;
830 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
833 clocks = <&ccu CLK_APB2_UART1>;
834 resets = <&ccu RST_APB2_UART1>;
835 dmas = <&dma 7>, <&dma 7>;
836 dma-names = "tx", "rx";
840 uart2: serial@1c28800 {
841 compatible = "snps,dw-apb-uart";
842 reg = <0x01c28800 0x400>;
843 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
846 clocks = <&ccu CLK_APB2_UART2>;
847 resets = <&ccu RST_APB2_UART2>;
848 dmas = <&dma 8>, <&dma 8>;
849 dma-names = "tx", "rx";
853 uart3: serial@1c28c00 {
854 compatible = "snps,dw-apb-uart";
855 reg = <0x01c28c00 0x400>;
856 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
859 clocks = <&ccu CLK_APB2_UART3>;
860 resets = <&ccu RST_APB2_UART3>;
861 dmas = <&dma 9>, <&dma 9>;
862 dma-names = "tx", "rx";
866 uart4: serial@1c29000 {
867 compatible = "snps,dw-apb-uart";
868 reg = <0x01c29000 0x400>;
869 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
872 clocks = <&ccu CLK_APB2_UART4>;
873 resets = <&ccu RST_APB2_UART4>;
874 dmas = <&dma 10>, <&dma 10>;
875 dma-names = "tx", "rx";
879 uart5: serial@1c29400 {
880 compatible = "snps,dw-apb-uart";
881 reg = <0x01c29400 0x400>;
882 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
885 clocks = <&ccu CLK_APB2_UART5>;
886 resets = <&ccu RST_APB2_UART5>;
887 dmas = <&dma 22>, <&dma 22>;
888 dma-names = "tx", "rx";
893 compatible = "allwinner,sun6i-a31-i2c";
894 reg = <0x01c2ac00 0x400>;
895 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
896 clocks = <&ccu CLK_APB2_I2C0>;
897 resets = <&ccu RST_APB2_I2C0>;
898 pinctrl-names = "default";
899 pinctrl-0 = <&i2c0_pins>;
901 #address-cells = <1>;
906 compatible = "allwinner,sun6i-a31-i2c";
907 reg = <0x01c2b000 0x400>;
908 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
909 clocks = <&ccu CLK_APB2_I2C1>;
910 resets = <&ccu RST_APB2_I2C1>;
911 pinctrl-names = "default";
912 pinctrl-0 = <&i2c1_pins>;
914 #address-cells = <1>;
919 compatible = "allwinner,sun6i-a31-i2c";
920 reg = <0x01c2b400 0x400>;
921 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
922 clocks = <&ccu CLK_APB2_I2C2>;
923 resets = <&ccu RST_APB2_I2C2>;
924 pinctrl-names = "default";
925 pinctrl-0 = <&i2c2_pins>;
927 #address-cells = <1>;
932 compatible = "allwinner,sun6i-a31-i2c";
933 reg = <0x01c2b800 0x400>;
934 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
935 clocks = <&ccu CLK_APB2_I2C3>;
936 resets = <&ccu RST_APB2_I2C3>;
938 #address-cells = <1>;
942 gmac: ethernet@1c30000 {
943 compatible = "allwinner,sun7i-a20-gmac";
944 reg = <0x01c30000 0x1054>;
945 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
946 interrupt-names = "macirq";
947 clocks = <&ccu CLK_AHB1_EMAC>, <&gmac_tx_clk>;
948 clock-names = "stmmaceth", "allwinner_gmac_tx";
949 resets = <&ccu RST_AHB1_EMAC>;
950 reset-names = "stmmaceth";
953 snps,force_sf_dma_mode;
957 compatible = "snps,dwmac-mdio";
958 #address-cells = <1>;
963 crypto: crypto-engine@1c15000 {
964 compatible = "allwinner,sun6i-a31-crypto",
965 "allwinner,sun4i-a10-crypto";
966 reg = <0x01c15000 0x1000>;
967 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
968 clocks = <&ccu CLK_AHB1_SS>, <&ccu CLK_SS>;
969 clock-names = "ahb", "mod";
970 resets = <&ccu RST_AHB1_SS>;
974 codec: codec@1c22c00 {
975 #sound-dai-cells = <0>;
976 compatible = "allwinner,sun6i-a31-codec";
977 reg = <0x01c22c00 0x400>;
978 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
979 clocks = <&ccu CLK_APB1_CODEC>, <&ccu CLK_CODEC>;
980 clock-names = "apb", "codec";
981 resets = <&ccu RST_APB1_CODEC>;
982 dmas = <&dma 15>, <&dma 15>;
983 dma-names = "rx", "tx";
988 compatible = "allwinner,sun6i-a31-hstimer",
989 "allwinner,sun7i-a20-hstimer";
990 reg = <0x01c60000 0x1000>;
991 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
992 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
993 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
994 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
995 clocks = <&ccu CLK_AHB1_HSTIMER>;
996 resets = <&ccu RST_AHB1_HSTIMER>;
1000 compatible = "allwinner,sun6i-a31-spi";
1001 reg = <0x01c68000 0x1000>;
1002 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
1003 clocks = <&ccu CLK_AHB1_SPI0>, <&ccu CLK_SPI0>;
1004 clock-names = "ahb", "mod";
1005 dmas = <&dma 23>, <&dma 23>;
1006 dma-names = "rx", "tx";
1007 resets = <&ccu RST_AHB1_SPI0>;
1008 status = "disabled";
1009 #address-cells = <1>;
1014 compatible = "allwinner,sun6i-a31-spi";
1015 reg = <0x01c69000 0x1000>;
1016 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1017 clocks = <&ccu CLK_AHB1_SPI1>, <&ccu CLK_SPI1>;
1018 clock-names = "ahb", "mod";
1019 dmas = <&dma 24>, <&dma 24>;
1020 dma-names = "rx", "tx";
1021 resets = <&ccu RST_AHB1_SPI1>;
1022 status = "disabled";
1023 #address-cells = <1>;
1028 compatible = "allwinner,sun6i-a31-spi";
1029 reg = <0x01c6a000 0x1000>;
1030 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1031 clocks = <&ccu CLK_AHB1_SPI2>, <&ccu CLK_SPI2>;
1032 clock-names = "ahb", "mod";
1033 dmas = <&dma 25>, <&dma 25>;
1034 dma-names = "rx", "tx";
1035 resets = <&ccu RST_AHB1_SPI2>;
1036 status = "disabled";
1037 #address-cells = <1>;
1042 compatible = "allwinner,sun6i-a31-spi";
1043 reg = <0x01c6b000 0x1000>;
1044 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
1045 clocks = <&ccu CLK_AHB1_SPI3>, <&ccu CLK_SPI3>;
1046 clock-names = "ahb", "mod";
1047 dmas = <&dma 26>, <&dma 26>;
1048 dma-names = "rx", "tx";
1049 resets = <&ccu RST_AHB1_SPI3>;
1050 status = "disabled";
1051 #address-cells = <1>;
1055 gic: interrupt-controller@1c81000 {
1056 compatible = "arm,gic-400";
1057 reg = <0x01c81000 0x1000>,
1058 <0x01c82000 0x2000>,
1059 <0x01c84000 0x2000>,
1060 <0x01c86000 0x2000>;
1061 interrupt-controller;
1062 #interrupt-cells = <3>;
1063 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1066 fe0: display-frontend@1e00000 {
1067 compatible = "allwinner,sun6i-a31-display-frontend";
1068 reg = <0x01e00000 0x20000>;
1069 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1070 clocks = <&ccu CLK_AHB1_FE0>, <&ccu CLK_FE0>,
1071 <&ccu CLK_DRAM_FE0>;
1072 clock-names = "ahb", "mod",
1074 resets = <&ccu RST_AHB1_FE0>;
1077 #address-cells = <1>;
1081 #address-cells = <1>;
1085 fe0_out_be0: endpoint@0 {
1087 remote-endpoint = <&be0_in_fe0>;
1090 fe0_out_be1: endpoint@1 {
1092 remote-endpoint = <&be1_in_fe0>;
1098 fe1: display-frontend@1e20000 {
1099 compatible = "allwinner,sun6i-a31-display-frontend";
1100 reg = <0x01e20000 0x20000>;
1101 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
1102 clocks = <&ccu CLK_AHB1_FE1>, <&ccu CLK_FE1>,
1103 <&ccu CLK_DRAM_FE1>;
1104 clock-names = "ahb", "mod",
1106 resets = <&ccu RST_AHB1_FE1>;
1109 #address-cells = <1>;
1113 #address-cells = <1>;
1117 fe1_out_be0: endpoint@0 {
1119 remote-endpoint = <&be0_in_fe1>;
1122 fe1_out_be1: endpoint@1 {
1124 remote-endpoint = <&be1_in_fe1>;
1130 be1: display-backend@1e40000 {
1131 compatible = "allwinner,sun6i-a31-display-backend";
1132 reg = <0x01e40000 0x10000>;
1133 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1134 clocks = <&ccu CLK_AHB1_BE1>, <&ccu CLK_BE1>,
1135 <&ccu CLK_DRAM_BE1>;
1136 clock-names = "ahb", "mod",
1138 resets = <&ccu RST_AHB1_BE1>;
1141 #address-cells = <1>;
1145 #address-cells = <1>;
1149 be1_in_fe0: endpoint@0 {
1151 remote-endpoint = <&fe0_out_be1>;
1154 be1_in_fe1: endpoint@1 {
1156 remote-endpoint = <&fe1_out_be1>;
1161 #address-cells = <1>;
1165 be1_out_drc1: endpoint@1 {
1167 remote-endpoint = <&drc1_in_be1>;
1174 compatible = "allwinner,sun6i-a31-drc";
1175 reg = <0x01e50000 0x10000>;
1176 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1177 clocks = <&ccu CLK_AHB1_DRC1>, <&ccu CLK_IEP_DRC1>,
1178 <&ccu CLK_DRAM_DRC1>;
1179 clock-names = "ahb", "mod",
1181 resets = <&ccu RST_AHB1_DRC1>;
1184 #address-cells = <1>;
1188 #address-cells = <1>;
1192 drc1_in_be1: endpoint@1 {
1194 remote-endpoint = <&be1_out_drc1>;
1199 #address-cells = <1>;
1203 drc1_out_tcon0: endpoint@0 {
1205 remote-endpoint = <&tcon0_in_drc1>;
1208 drc1_out_tcon1: endpoint@1 {
1210 remote-endpoint = <&tcon1_in_drc1>;
1216 be0: display-backend@1e60000 {
1217 compatible = "allwinner,sun6i-a31-display-backend";
1218 reg = <0x01e60000 0x10000>;
1219 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1220 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_BE0>,
1221 <&ccu CLK_DRAM_BE0>;
1222 clock-names = "ahb", "mod",
1224 resets = <&ccu RST_AHB1_BE0>;
1227 #address-cells = <1>;
1231 #address-cells = <1>;
1235 be0_in_fe0: endpoint@0 {
1237 remote-endpoint = <&fe0_out_be0>;
1240 be0_in_fe1: endpoint@1 {
1242 remote-endpoint = <&fe1_out_be0>;
1249 be0_out_drc0: endpoint {
1250 remote-endpoint = <&drc0_in_be0>;
1257 compatible = "allwinner,sun6i-a31-drc";
1258 reg = <0x01e70000 0x10000>;
1259 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1260 clocks = <&ccu CLK_AHB1_DRC0>, <&ccu CLK_IEP_DRC0>,
1261 <&ccu CLK_DRAM_DRC0>;
1262 clock-names = "ahb", "mod",
1264 resets = <&ccu RST_AHB1_DRC0>;
1267 #address-cells = <1>;
1273 drc0_in_be0: endpoint {
1274 remote-endpoint = <&be0_out_drc0>;
1279 #address-cells = <1>;
1283 drc0_out_tcon0: endpoint@0 {
1285 remote-endpoint = <&tcon0_in_drc0>;
1288 drc0_out_tcon1: endpoint@1 {
1290 remote-endpoint = <&tcon1_in_drc0>;
1298 compatible = "allwinner,sun6i-a31-rtc";
1299 reg = <0x01f00000 0x54>;
1300 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1301 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1303 clock-output-names = "osc32k";
1306 r_intc: interrupt-controller@1f00c00 {
1307 compatible = "allwinner,sun6i-a31-r-intc";
1308 interrupt-controller;
1309 #interrupt-cells = <2>;
1310 reg = <0x01f00c00 0x400>;
1311 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1315 compatible = "allwinner,sun6i-a31-prcm";
1316 reg = <0x01f01400 0x200>;
1319 compatible = "allwinner,sun6i-a31-ar100-clk";
1321 clocks = <&rtc CLK_OSC32K>, <&osc24M>,
1322 <&ccu CLK_PLL_PERIPH>,
1323 <&ccu CLK_PLL_PERIPH>;
1324 clock-output-names = "ar100";
1328 compatible = "fixed-factor-clock";
1333 clock-output-names = "ahb0";
1337 compatible = "allwinner,sun6i-a31-apb0-clk";
1340 clock-output-names = "apb0";
1343 apb0_gates: apb0_gates_clk {
1344 compatible = "allwinner,sun6i-a31-apb0-gates-clk";
1347 clock-output-names = "apb0_pio", "apb0_ir",
1348 "apb0_timer", "apb0_p2wi",
1349 "apb0_uart", "apb0_1wire",
1355 compatible = "allwinner,sun4i-a10-mod0-clk";
1356 clocks = <&rtc CLK_OSC32K>, <&osc24M>;
1357 clock-output-names = "ir";
1360 apb0_rst: apb0_rst {
1361 compatible = "allwinner,sun6i-a31-clock-reset";
1367 compatible = "allwinner,sun6i-a31-cpuconfig";
1368 reg = <0x01f01c00 0x300>;
1372 compatible = "allwinner,sun6i-a31-ir";
1373 clocks = <&apb0_gates 1>, <&ir_clk>;
1374 clock-names = "apb", "ir";
1375 resets = <&apb0_rst 1>;
1376 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1377 reg = <0x01f02000 0x40>;
1378 status = "disabled";
1381 r_pio: pinctrl@1f02c00 {
1382 compatible = "allwinner,sun6i-a31-r-pinctrl";
1383 reg = <0x01f02c00 0x400>;
1384 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1385 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
1386 clocks = <&apb0_gates 0>, <&osc24M>, <&rtc CLK_OSC32K>;
1387 clock-names = "apb", "hosc", "losc";
1389 interrupt-controller;
1390 #interrupt-cells = <3>;
1393 s_ir_rx_pin: s-ir-rx-pin {
1398 s_p2wi_pins: s-p2wi-pins {
1399 pins = "PL0", "PL1";
1400 function = "s_p2wi";
1405 compatible = "allwinner,sun6i-a31-p2wi";
1406 reg = <0x01f03400 0x400>;
1407 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1408 clocks = <&apb0_gates 3>;
1409 clock-frequency = <100000>;
1410 resets = <&apb0_rst 3>;
1411 pinctrl-names = "default";
1412 pinctrl-0 = <&s_p2wi_pins>;
1413 status = "disabled";
1414 #address-cells = <1>;