arch/arm/dts/sun6i-a31.dtsi

   1 /*
   2  * Copyright 2013 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include "skeleton.dtsi"
  46
  47 #include <dt-bindings/interrupt-controller/arm-gic.h>
  48 #include <dt-bindings/thermal/thermal.h>
  49
  50 #include <dt-bindings/pinctrl/sun4i-a10.h>
  51
  52 / {
  53         interrupt-parent = <&gic>;
  54
  55         aliases {
  56                 ethernet0 = &gmac;
  57         };
  58
  59         chosen {
  60                 #address-cells = <1>;
  61                 #size-cells = <1>;
  62                 ranges;
  63
  64                 framebuffer@0 {
  65                         compatible = "allwinner,simple-framebuffer",
  66                                      "simple-framebuffer";
  67                         allwinner,pipeline = "de_be0-lcd0-hdmi";
  68                         clocks = <&pll6 0>;
  69                         status = "disabled";
  70                 };
  71
  72                 framebuffer@1 {
  73                         compatible = "allwinner,simple-framebuffer",
  74                                      "simple-framebuffer";
  75                         allwinner,pipeline = "de_be0-lcd0";
  76                         clocks = <&pll6 0>;
  77                         status = "disabled";
  78                 };
  79         };
  80
  81         timer {
  82                 compatible = "arm,armv7-timer";
  83                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  84                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  85                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  86                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  87                 clock-frequency = <24000000>;
  88                 arm,cpu-registers-not-fw-configured;
  89         };
  90
  91         cpus {
  92                 enable-method = "allwinner,sun6i-a31";
  93                 #address-cells = <1>;
  94                 #size-cells = <0>;
  95
  96                 cpu0: cpu@0 {
  97                         compatible = "arm,cortex-a7";
  98                         device_type = "cpu";
  99                         reg = <0>;
 100                         clocks = <&cpu>;
 101                         clock-latency = <244144>; /* 8 32k periods */
 102                         operating-points = <
 103                                 /* kHz    uV */
 104                                 1008000 1200000
 105                                 864000  1200000
 106                                 720000  1100000
 107                                 480000  1000000
 108                                 >;
 109                         #cooling-cells = <2>;
 110                         cooling-min-level = <0>;
 111                         cooling-max-level = <3>;
 112                 };
 113
 114                 cpu@1 {
 115                         compatible = "arm,cortex-a7";
 116                         device_type = "cpu";
 117                         reg = <1>;
 118                 };
 119
 120                 cpu@2 {
 121                         compatible = "arm,cortex-a7";
 122                         device_type = "cpu";
 123                         reg = <2>;
 124                 };
 125
 126                 cpu@3 {
 127                         compatible = "arm,cortex-a7";
 128                         device_type = "cpu";
 129                         reg = <3>;
 130                 };
 131         };
 132
 133         thermal-zones {
 134                 cpu_thermal {
 135                         /* milliseconds */
 136                         polling-delay-passive = <250>;
 137                         polling-delay = <1000>;
 138                         thermal-sensors = <&rtp>;
 139
 140                         cooling-maps {
 141                                 map0 {
 142                                         trip = <&cpu_alert0>;
 143                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 144                                 };
 145                         };
 146
 147                         trips {
 148                                 cpu_alert0: cpu_alert0 {
 149                                         /* milliCelsius */
 150                                         temperature = <70000>;
 151                                         hysteresis = <2000>;
 152                                         type = "passive";
 153                                 };
 154
 155                                 cpu_crit: cpu_crit {
 156                                         /* milliCelsius */
 157                                         temperature = <100000>;
 158                                         hysteresis = <2000>;
 159                                         type = "critical";
 160                                 };
 161                         };
 162                 };
 163         };
 164
 165         memory {
 166                 reg = <0x40000000 0x80000000>;
 167         };
 168
 169         pmu {
 170                 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
 171                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 172                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 173                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 174                              <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
 175         };
 176
 177         clocks {
 178                 #address-cells = <1>;
 179                 #size-cells = <1>;
 180                 ranges;
 181
 182                 osc24M: osc24M {
 183                         #clock-cells = <0>;
 184                         compatible = "fixed-clock";
 185                         clock-frequency = <24000000>;
 186                 };
 187
 188                 osc32k: clk@0 {
 189                         #clock-cells = <0>;
 190                         compatible = "fixed-clock";
 191                         clock-frequency = <32768>;
 192                         clock-output-names = "osc32k";
 193                 };
 194
 195                 pll1: clk@01c20000 {
 196                         #clock-cells = <0>;
 197                         compatible = "allwinner,sun6i-a31-pll1-clk";
 198                         reg = <0x01c20000 0x4>;
 199                         clocks = <&osc24M>;
 200                         clock-output-names = "pll1";
 201                 };
 202
 203                 pll6: clk@01c20028 {
 204                         #clock-cells = <1>;
 205                         compatible = "allwinner,sun6i-a31-pll6-clk";
 206                         reg = <0x01c20028 0x4>;
 207                         clocks = <&osc24M>;
 208                         clock-output-names = "pll6", "pll6x2";
 209                 };
 210
 211                 cpu: cpu@01c20050 {
 212                         #clock-cells = <0>;
 213                         compatible = "allwinner,sun4i-a10-cpu-clk";
 214                         reg = <0x01c20050 0x4>;
 215
 216                         /*
 217                          * PLL1 is listed twice here.
 218                          * While it looks suspicious, it's actually documented
 219                          * that way both in the datasheet and in the code from
 220                          * Allwinner.
 221                          */
 222                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
 223                         clock-output-names = "cpu";
 224                 };
 225
 226                 axi: axi@01c20050 {
 227                         #clock-cells = <0>;
 228                         compatible = "allwinner,sun4i-a10-axi-clk";
 229                         reg = <0x01c20050 0x4>;
 230                         clocks = <&cpu>;
 231                         clock-output-names = "axi";
 232                 };
 233
 234                 ahb1: ahb1@01c20054 {
 235                         #clock-cells = <0>;
 236                         compatible = "allwinner,sun6i-a31-ahb1-clk";
 237                         reg = <0x01c20054 0x4>;
 238                         clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
 239                         clock-output-names = "ahb1";
 240
 241                         /*
 242                          * Clock AHB1 from PLL6, instead of CPU/AXI which
 243                          * has rate changes due to cpufreq. Also the DMA
 244                          * controller requires AHB1 clocked from PLL6.
 245                          */
 246                         assigned-clocks = <&ahb1>;
 247                         assigned-clock-parents = <&pll6 0>;
 248                 };
 249
 250                 ahb1_gates: clk@01c20060 {
 251                         #clock-cells = <1>;
 252                         compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
 253                         reg = <0x01c20060 0x8>;
 254                         clocks = <&ahb1>;
 255                         clock-output-names = "ahb1_mipidsi", "ahb1_ss",
 256                                         "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
 257                                         "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
 258                                         "ahb1_nand0", "ahb1_sdram",
 259                                         "ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
 260                                         "ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
 261                                         "ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
 262                                         "ahb1_ehci1", "ahb1_ohci0",
 263                                         "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
 264                                         "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
 265                                         "ahb1_hdmi", "ahb1_de0", "ahb1_de1",
 266                                         "ahb1_fe0", "ahb1_fe1", "ahb1_mp",
 267                                         "ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
 268                                         "ahb1_drc0", "ahb1_drc1";
 269                 };
 270
 271                 apb1: apb1@01c20054 {
 272                         #clock-cells = <0>;
 273                         compatible = "allwinner,sun4i-a10-apb0-clk";
 274                         reg = <0x01c20054 0x4>;
 275                         clocks = <&ahb1>;
 276                         clock-output-names = "apb1";
 277                 };
 278
 279                 apb1_gates: clk@01c20068 {
 280                         #clock-cells = <1>;
 281                         compatible = "allwinner,sun6i-a31-apb1-gates-clk";
 282                         reg = <0x01c20068 0x4>;
 283                         clocks = <&apb1>;
 284                         clock-output-names = "apb1_codec", "apb1_digital_mic",
 285                                         "apb1_pio", "apb1_daudio0",
 286                                         "apb1_daudio1";
 287                 };
 288
 289                 apb2: clk@01c20058 {
 290                         #clock-cells = <0>;
 291                         compatible = "allwinner,sun4i-a10-apb1-clk";
 292                         reg = <0x01c20058 0x4>;
 293                         clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
 294                         clock-output-names = "apb2";
 295                 };
 296
 297                 apb2_gates: clk@01c2006c {
 298                         #clock-cells = <1>;
 299                         compatible = "allwinner,sun6i-a31-apb2-gates-clk";
 300                         reg = <0x01c2006c 0x4>;
 301                         clocks = <&apb2>;
 302                         clock-output-names = "apb2_i2c0", "apb2_i2c1",
 303                                              "apb2_i2c2", "apb2_i2c3",
 304                                              "apb2_uart0", "apb2_uart1",
 305                                              "apb2_uart2", "apb2_uart3",
 306                                              "apb2_uart4", "apb2_uart5";
 307                 };
 308
 309                 mmc0_clk: clk@01c20088 {
 310                         #clock-cells = <1>;
 311                         compatible = "allwinner,sun4i-a10-mmc-clk";
 312                         reg = <0x01c20088 0x4>;
 313                         clocks = <&osc24M>, <&pll6 0>;
 314                         clock-output-names = "mmc0",
 315                                              "mmc0_output",
 316                                              "mmc0_sample";
 317                 };
 318
 319                 mmc1_clk: clk@01c2008c {
 320                         #clock-cells = <1>;
 321                         compatible = "allwinner,sun4i-a10-mmc-clk";
 322                         reg = <0x01c2008c 0x4>;
 323                         clocks = <&osc24M>, <&pll6 0>;
 324                         clock-output-names = "mmc1",
 325                                              "mmc1_output",
 326                                              "mmc1_sample";
 327                 };
 328
 329                 mmc2_clk: clk@01c20090 {
 330                         #clock-cells = <1>;
 331                         compatible = "allwinner,sun4i-a10-mmc-clk";
 332                         reg = <0x01c20090 0x4>;
 333                         clocks = <&osc24M>, <&pll6 0>;
 334                         clock-output-names = "mmc2",
 335                                              "mmc2_output",
 336                                              "mmc2_sample";
 337                 };
 338
 339                 mmc3_clk: clk@01c20094 {
 340                         #clock-cells = <1>;
 341                         compatible = "allwinner,sun4i-a10-mmc-clk";
 342                         reg = <0x01c20094 0x4>;
 343                         clocks = <&osc24M>, <&pll6 0>;
 344                         clock-output-names = "mmc3",
 345                                              "mmc3_output",
 346                                              "mmc3_sample";
 347                 };
 348
 349                 spi0_clk: clk@01c200a0 {
 350                         #clock-cells = <0>;
 351                         compatible = "allwinner,sun4i-a10-mod0-clk";
 352                         reg = <0x01c200a0 0x4>;
 353                         clocks = <&osc24M>, <&pll6 0>;
 354                         clock-output-names = "spi0";
 355                 };
 356
 357                 spi1_clk: clk@01c200a4 {
 358                         #clock-cells = <0>;
 359                         compatible = "allwinner,sun4i-a10-mod0-clk";
 360                         reg = <0x01c200a4 0x4>;
 361                         clocks = <&osc24M>, <&pll6 0>;
 362                         clock-output-names = "spi1";
 363                 };
 364
 365                 spi2_clk: clk@01c200a8 {
 366                         #clock-cells = <0>;
 367                         compatible = "allwinner,sun4i-a10-mod0-clk";
 368                         reg = <0x01c200a8 0x4>;
 369                         clocks = <&osc24M>, <&pll6 0>;
 370                         clock-output-names = "spi2";
 371                 };
 372
 373                 spi3_clk: clk@01c200ac {
 374                         #clock-cells = <0>;
 375                         compatible = "allwinner,sun4i-a10-mod0-clk";
 376                         reg = <0x01c200ac 0x4>;
 377                         clocks = <&osc24M>, <&pll6 0>;
 378                         clock-output-names = "spi3";
 379                 };
 380
 381                 usb_clk: clk@01c200cc {
 382                         #clock-cells = <1>;
 383                         #reset-cells = <1>;
 384                         compatible = "allwinner,sun6i-a31-usb-clk";
 385                         reg = <0x01c200cc 0x4>;
 386                         clocks = <&osc24M>;
 387                         clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2",
 388                                              "usb_ohci0", "usb_ohci1",
 389                                              "usb_ohci2";
 390                 };
 391
 392                 /*
 393                  * The following two are dummy clocks, placeholders
 394                  * used in the gmac_tx clock. The gmac driver will
 395                  * choose one parent depending on the PHY interface
 396                  * mode, using clk_set_rate auto-reparenting.
 397                  *
 398                  * The actual TX clock rate is not controlled by the
 399                  * gmac_tx clock.
 400                  */
 401                 mii_phy_tx_clk: clk@1 {
 402                         #clock-cells = <0>;
 403                         compatible = "fixed-clock";
 404                         clock-frequency = <25000000>;
 405                         clock-output-names = "mii_phy_tx";
 406                 };
 407
 408                 gmac_int_tx_clk: clk@2 {
 409                         #clock-cells = <0>;
 410                         compatible = "fixed-clock";
 411                         clock-frequency = <125000000>;
 412                         clock-output-names = "gmac_int_tx";
 413                 };
 414
 415                 gmac_tx_clk: clk@01c200d0 {
 416                         #clock-cells = <0>;
 417                         compatible = "allwinner,sun7i-a20-gmac-clk";
 418                         reg = <0x01c200d0 0x4>;
 419                         clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
 420                         clock-output-names = "gmac_tx";
 421                 };
 422         };
 423
 424         soc@01c00000 {
 425                 compatible = "simple-bus";
 426                 #address-cells = <1>;
 427                 #size-cells = <1>;
 428                 ranges;
 429
 430                 dma: dma-controller@01c02000 {
 431                         compatible = "allwinner,sun6i-a31-dma";
 432                         reg = <0x01c02000 0x1000>;
 433                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 434                         clocks = <&ahb1_gates 6>;
 435                         resets = <&ahb1_rst 6>;
 436                         #dma-cells = <1>;
 437                 };
 438
 439                 mmc0: mmc@01c0f000 {
 440                         compatible = "allwinner,sun5i-a13-mmc";
 441                         reg = <0x01c0f000 0x1000>;
 442                         clocks = <&ahb1_gates 8>,
 443                                  <&mmc0_clk 0>,
 444                                  <&mmc0_clk 1>,
 445                                  <&mmc0_clk 2>;
 446                         clock-names = "ahb",
 447                                       "mmc",
 448                                       "output",
 449                                       "sample";
 450                         resets = <&ahb1_rst 8>;
 451                         reset-names = "ahb";
 452                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 453                         status = "disabled";
 454                         #address-cells = <1>;
 455                         #size-cells = <0>;
 456                 };
 457
 458                 mmc1: mmc@01c10000 {
 459                         compatible = "allwinner,sun5i-a13-mmc";
 460                         reg = <0x01c10000 0x1000>;
 461                         clocks = <&ahb1_gates 9>,
 462                                  <&mmc1_clk 0>,
 463                                  <&mmc1_clk 1>,
 464                                  <&mmc1_clk 2>;
 465                         clock-names = "ahb",
 466                                       "mmc",
 467                                       "output",
 468                                       "sample";
 469                         resets = <&ahb1_rst 9>;
 470                         reset-names = "ahb";
 471                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 472                         status = "disabled";
 473                         #address-cells = <1>;
 474                         #size-cells = <0>;
 475                 };
 476
 477                 mmc2: mmc@01c11000 {
 478                         compatible = "allwinner,sun5i-a13-mmc";
 479                         reg = <0x01c11000 0x1000>;
 480                         clocks = <&ahb1_gates 10>,
 481                                  <&mmc2_clk 0>,
 482                                  <&mmc2_clk 1>,
 483                                  <&mmc2_clk 2>;
 484                         clock-names = "ahb",
 485                                       "mmc",
 486                                       "output",
 487                                       "sample";
 488                         resets = <&ahb1_rst 10>;
 489                         reset-names = "ahb";
 490                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 491                         status = "disabled";
 492                         #address-cells = <1>;
 493                         #size-cells = <0>;
 494                 };
 495
 496                 mmc3: mmc@01c12000 {
 497                         compatible = "allwinner,sun5i-a13-mmc";
 498                         reg = <0x01c12000 0x1000>;
 499                         clocks = <&ahb1_gates 11>,
 500                                  <&mmc3_clk 0>,
 501                                  <&mmc3_clk 1>,
 502                                  <&mmc3_clk 2>;
 503                         clock-names = "ahb",
 504                                       "mmc",
 505                                       "output",
 506                                       "sample";
 507                         resets = <&ahb1_rst 11>;
 508                         reset-names = "ahb";
 509                         interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 510                         status = "disabled";
 511                         #address-cells = <1>;
 512                         #size-cells = <0>;
 513                 };
 514
 515                 usb_otg: usb@01c19000 {
 516                         compatible = "allwinner,sun6i-a31-musb";
 517                         reg = <0x01c19000 0x0400>;
 518                         clocks = <&ahb1_gates 24>;
 519                         resets = <&ahb1_rst 24>;
 520                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 521                         interrupt-names = "mc";
 522                         phys = <&usbphy 0>;
 523                         phy-names = "usb";
 524                         extcon = <&usbphy 0>;
 525                         status = "disabled";
 526                 };
 527
 528                 usbphy: phy@01c19400 {
 529                         compatible = "allwinner,sun6i-a31-usb-phy";
 530                         reg = <0x01c19400 0x10>,
 531                               <0x01c1a800 0x4>,
 532                               <0x01c1b800 0x4>;
 533                         reg-names = "phy_ctrl",
 534                                     "pmu1",
 535                                     "pmu2";
 536                         clocks = <&usb_clk 8>,
 537                                  <&usb_clk 9>,
 538                                  <&usb_clk 10>;
 539                         clock-names = "usb0_phy",
 540                                       "usb1_phy",
 541                                       "usb2_phy";
 542                         resets = <&usb_clk 0>,
 543                                  <&usb_clk 1>,
 544                                  <&usb_clk 2>;
 545                         reset-names = "usb0_reset",
 546                                       "usb1_reset",
 547                                       "usb2_reset";
 548                         status = "disabled";
 549                         #phy-cells = <1>;
 550                 };
 551
 552                 ehci0: usb@01c1a000 {
 553                         compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
 554                         reg = <0x01c1a000 0x100>;
 555                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 556                         clocks = <&ahb1_gates 26>;
 557                         resets = <&ahb1_rst 26>;
 558                         phys = <&usbphy 1>;
 559                         phy-names = "usb";
 560                         status = "disabled";
 561                 };
 562
 563                 ohci0: usb@01c1a400 {
 564                         compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
 565                         reg = <0x01c1a400 0x100>;
 566                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 567                         clocks = <&ahb1_gates 29>, <&usb_clk 16>;
 568                         resets = <&ahb1_rst 29>;
 569                         phys = <&usbphy 1>;
 570                         phy-names = "usb";
 571                         status = "disabled";
 572                 };
 573
 574                 ehci1: usb@01c1b000 {
 575                         compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
 576                         reg = <0x01c1b000 0x100>;
 577                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 578                         clocks = <&ahb1_gates 27>;
 579                         resets = <&ahb1_rst 27>;
 580                         phys = <&usbphy 2>;
 581                         phy-names = "usb";
 582                         status = "disabled";
 583                 };
 584
 585                 ohci1: usb@01c1b400 {
 586                         compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
 587                         reg = <0x01c1b400 0x100>;
 588                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 589                         clocks = <&ahb1_gates 30>, <&usb_clk 17>;
 590                         resets = <&ahb1_rst 30>;
 591                         phys = <&usbphy 2>;
 592                         phy-names = "usb";
 593                         status = "disabled";
 594                 };
 595
 596                 ohci2: usb@01c1c400 {
 597                         compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
 598                         reg = <0x01c1c400 0x100>;
 599                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 600                         clocks = <&ahb1_gates 31>, <&usb_clk 18>;
 601                         resets = <&ahb1_rst 31>;
 602                         status = "disabled";
 603                 };
 604
 605                 pio: pinctrl@01c20800 {
 606                         compatible = "allwinner,sun6i-a31-pinctrl";
 607                         reg = <0x01c20800 0x400>;
 608                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 609                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 610                                      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 611                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 612                         clocks = <&apb1_gates 5>;
 613                         gpio-controller;
 614                         interrupt-controller;
 615                         #interrupt-cells = <3>;
 616                         #gpio-cells = <3>;
 617
 618                         uart0_pins_a: uart0@0 {
 619                                 allwinner,pins = "PH20", "PH21";
 620                                 allwinner,function = "uart0";
 621                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 622                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 623                         };
 624
 625                         i2c0_pins_a: i2c0@0 {
 626                                 allwinner,pins = "PH14", "PH15";
 627                                 allwinner,function = "i2c0";
 628                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 629                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 630                         };
 631
 632                         i2c1_pins_a: i2c1@0 {
 633                                 allwinner,pins = "PH16", "PH17";
 634                                 allwinner,function = "i2c1";
 635                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 636                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 637                         };
 638
 639                         i2c2_pins_a: i2c2@0 {
 640                                 allwinner,pins = "PH18", "PH19";
 641                                 allwinner,function = "i2c2";
 642                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 643                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 644                         };
 645
 646                         mmc0_pins_a: mmc0@0 {
 647                                 allwinner,pins = "PF0", "PF1", "PF2",
 648                                                  "PF3", "PF4", "PF5";
 649                                 allwinner,function = "mmc0";
 650                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 651                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 652                         };
 653
 654                         mmc1_pins_a: mmc1@0 {
 655                                 allwinner,pins = "PG0", "PG1", "PG2", "PG3",
 656                                                  "PG4", "PG5";
 657                                 allwinner,function = "mmc1";
 658                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 659                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 660                         };
 661
 662                         mmc2_pins_a: mmc2@0 {
 663                                 allwinner,pins = "PC6", "PC7", "PC8", "PC9",
 664                                                  "PC10", "PC11";
 665                                 allwinner,function = "mmc2";
 666                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 667                                 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
 668                         };
 669
 670                         mmc2_8bit_emmc_pins: mmc2@1 {
 671                                 allwinner,pins = "PC6", "PC7", "PC8", "PC9",
 672                                                  "PC10", "PC11", "PC12",
 673                                                  "PC13", "PC14", "PC15",
 674                                                  "PC24";
 675                                 allwinner,function = "mmc2";
 676                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 677                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 678                         };
 679
 680                         gmac_pins_mii_a: gmac_mii@0 {
 681                                 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
 682                                                 "PA8", "PA9", "PA11",
 683                                                 "PA12", "PA13", "PA14", "PA19",
 684                                                 "PA20", "PA21", "PA22", "PA23",
 685                                                 "PA24", "PA26", "PA27";
 686                                 allwinner,function = "gmac";
 687                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 688                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 689                         };
 690
 691                         gmac_pins_gmii_a: gmac_gmii@0 {
 692                                 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
 693                                                 "PA4", "PA5", "PA6", "PA7",
 694                                                 "PA8", "PA9", "PA10", "PA11",
 695                                                 "PA12", "PA13", "PA14", "PA15",
 696                                                 "PA16", "PA17", "PA18", "PA19",
 697                                                 "PA20", "PA21", "PA22", "PA23",
 698                                                 "PA24", "PA25", "PA26", "PA27";
 699                                 allwinner,function = "gmac";
 700                                 /*
 701                                  * data lines in GMII mode run at 125MHz and
 702                                  * might need a higher signal drive strength
 703                                  */
 704                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 705                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 706                         };
 707
 708                         gmac_pins_rgmii_a: gmac_rgmii@0 {
 709                                 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
 710                                                 "PA9", "PA10", "PA11",
 711                                                 "PA12", "PA13", "PA14", "PA19",
 712                                                 "PA20", "PA25", "PA26", "PA27";
 713                                 allwinner,function = "gmac";
 714                                 /*
 715                                  * data lines in RGMII mode use DDR mode
 716                                  * and need a higher signal drive strength
 717                                  */
 718                                 allwinner,drive = <SUN4I_PINCTRL_40_MA>;
 719                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 720                         };
 721                 };
 722
 723                 ahb1_rst: reset@01c202c0 {
 724                         #reset-cells = <1>;
 725                         compatible = "allwinner,sun6i-a31-ahb1-reset";
 726                         reg = <0x01c202c0 0xc>;
 727                 };
 728
 729                 apb1_rst: reset@01c202d0 {
 730                         #reset-cells = <1>;
 731                         compatible = "allwinner,sun6i-a31-clock-reset";
 732                         reg = <0x01c202d0 0x4>;
 733                 };
 734
 735                 apb2_rst: reset@01c202d8 {
 736                         #reset-cells = <1>;
 737                         compatible = "allwinner,sun6i-a31-clock-reset";
 738                         reg = <0x01c202d8 0x4>;
 739                 };
 740
 741                 timer@01c20c00 {
 742                         compatible = "allwinner,sun4i-a10-timer";
 743                         reg = <0x01c20c00 0xa0>;
 744                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 745                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 746                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
 747                                      <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
 748                                      <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 749                         clocks = <&osc24M>;
 750                 };
 751
 752                 wdt1: watchdog@01c20ca0 {
 753                         compatible = "allwinner,sun6i-a31-wdt";
 754                         reg = <0x01c20ca0 0x20>;
 755                 };
 756
 757                 rtp: rtp@01c25000 {
 758                         compatible = "allwinner,sun6i-a31-ts";
 759                         reg = <0x01c25000 0x100>;
 760                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 761                         #thermal-sensor-cells = <0>;
 762                 };
 763
 764                 uart0: serial@01c28000 {
 765                         compatible = "snps,dw-apb-uart";
 766                         reg = <0x01c28000 0x400>;
 767                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 768                         reg-shift = <2>;
 769                         reg-io-width = <4>;
 770                         clocks = <&apb2_gates 16>;
 771                         resets = <&apb2_rst 16>;
 772                         dmas = <&dma 6>, <&dma 6>;
 773                         dma-names = "rx", "tx";
 774                         status = "disabled";
 775                 };
 776
 777                 uart1: serial@01c28400 {
 778                         compatible = "snps,dw-apb-uart";
 779                         reg = <0x01c28400 0x400>;
 780                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 781                         reg-shift = <2>;
 782                         reg-io-width = <4>;
 783                         clocks = <&apb2_gates 17>;
 784                         resets = <&apb2_rst 17>;
 785                         dmas = <&dma 7>, <&dma 7>;
 786                         dma-names = "rx", "tx";
 787                         status = "disabled";
 788                 };
 789
 790                 uart2: serial@01c28800 {
 791                         compatible = "snps,dw-apb-uart";
 792                         reg = <0x01c28800 0x400>;
 793                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 794                         reg-shift = <2>;
 795                         reg-io-width = <4>;
 796                         clocks = <&apb2_gates 18>;
 797                         resets = <&apb2_rst 18>;
 798                         dmas = <&dma 8>, <&dma 8>;
 799                         dma-names = "rx", "tx";
 800                         status = "disabled";
 801                 };
 802
 803                 uart3: serial@01c28c00 {
 804                         compatible = "snps,dw-apb-uart";
 805                         reg = <0x01c28c00 0x400>;
 806                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 807                         reg-shift = <2>;
 808                         reg-io-width = <4>;
 809                         clocks = <&apb2_gates 19>;
 810                         resets = <&apb2_rst 19>;
 811                         dmas = <&dma 9>, <&dma 9>;
 812                         dma-names = "rx", "tx";
 813                         status = "disabled";
 814                 };
 815
 816                 uart4: serial@01c29000 {
 817                         compatible = "snps,dw-apb-uart";
 818                         reg = <0x01c29000 0x400>;
 819                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 820                         reg-shift = <2>;
 821                         reg-io-width = <4>;
 822                         clocks = <&apb2_gates 20>;
 823                         resets = <&apb2_rst 20>;
 824                         dmas = <&dma 10>, <&dma 10>;
 825                         dma-names = "rx", "tx";
 826                         status = "disabled";
 827                 };
 828
 829                 uart5: serial@01c29400 {
 830                         compatible = "snps,dw-apb-uart";
 831                         reg = <0x01c29400 0x400>;
 832                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 833                         reg-shift = <2>;
 834                         reg-io-width = <4>;
 835                         clocks = <&apb2_gates 21>;
 836                         resets = <&apb2_rst 21>;
 837                         dmas = <&dma 22>, <&dma 22>;
 838                         dma-names = "rx", "tx";
 839                         status = "disabled";
 840                 };
 841
 842                 i2c0: i2c@01c2ac00 {
 843                         compatible = "allwinner,sun6i-a31-i2c";
 844                         reg = <0x01c2ac00 0x400>;
 845                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 846                         clocks = <&apb2_gates 0>;
 847                         resets = <&apb2_rst 0>;
 848                         status = "disabled";
 849                         #address-cells = <1>;
 850                         #size-cells = <0>;
 851                 };
 852
 853                 i2c1: i2c@01c2b000 {
 854                         compatible = "allwinner,sun6i-a31-i2c";
 855                         reg = <0x01c2b000 0x400>;
 856                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 857                         clocks = <&apb2_gates 1>;
 858                         resets = <&apb2_rst 1>;
 859                         status = "disabled";
 860                         #address-cells = <1>;
 861                         #size-cells = <0>;
 862                 };
 863
 864                 i2c2: i2c@01c2b400 {
 865                         compatible = "allwinner,sun6i-a31-i2c";
 866                         reg = <0x01c2b400 0x400>;
 867                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 868                         clocks = <&apb2_gates 2>;
 869                         resets = <&apb2_rst 2>;
 870                         status = "disabled";
 871                         #address-cells = <1>;
 872                         #size-cells = <0>;
 873                 };
 874
 875                 i2c3: i2c@01c2b800 {
 876                         compatible = "allwinner,sun6i-a31-i2c";
 877                         reg = <0x01c2b800 0x400>;
 878                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 879                         clocks = <&apb2_gates 3>;
 880                         resets = <&apb2_rst 3>;
 881                         status = "disabled";
 882                         #address-cells = <1>;
 883                         #size-cells = <0>;
 884                 };
 885
 886                 gmac: ethernet@01c30000 {
 887                         compatible = "allwinner,sun7i-a20-gmac";
 888                         reg = <0x01c30000 0x1054>;
 889                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 890                         interrupt-names = "macirq";
 891                         clocks = <&ahb1_gates 17>, <&gmac_tx_clk>;
 892                         clock-names = "stmmaceth", "allwinner_gmac_tx";
 893                         resets = <&ahb1_rst 17>;
 894                         reset-names = "stmmaceth";
 895                         snps,pbl = <2>;
 896                         snps,fixed-burst;
 897                         snps,force_sf_dma_mode;
 898                         status = "disabled";
 899                         #address-cells = <1>;
 900                         #size-cells = <0>;
 901                 };
 902
 903                 timer@01c60000 {
 904                         compatible = "allwinner,sun6i-a31-hstimer",
 905                                      "allwinner,sun7i-a20-hstimer";
 906                         reg = <0x01c60000 0x1000>;
 907                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
 908                                      <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
 909                                      <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 910                                      <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 911                         clocks = <&ahb1_gates 19>;
 912                         resets = <&ahb1_rst 19>;
 913                 };
 914
 915                 spi0: spi@01c68000 {
 916                         compatible = "allwinner,sun6i-a31-spi";
 917                         reg = <0x01c68000 0x1000>;
 918                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 919                         clocks = <&ahb1_gates 20>, <&spi0_clk>;
 920                         clock-names = "ahb", "mod";
 921                         dmas = <&dma 23>, <&dma 23>;
 922                         dma-names = "rx", "tx";
 923                         resets = <&ahb1_rst 20>;
 924                         status = "disabled";
 925                 };
 926
 927                 spi1: spi@01c69000 {
 928                         compatible = "allwinner,sun6i-a31-spi";
 929                         reg = <0x01c69000 0x1000>;
 930                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 931                         clocks = <&ahb1_gates 21>, <&spi1_clk>;
 932                         clock-names = "ahb", "mod";
 933                         dmas = <&dma 24>, <&dma 24>;
 934                         dma-names = "rx", "tx";
 935                         resets = <&ahb1_rst 21>;
 936                         status = "disabled";
 937                 };
 938
 939                 spi2: spi@01c6a000 {
 940                         compatible = "allwinner,sun6i-a31-spi";
 941                         reg = <0x01c6a000 0x1000>;
 942                         interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 943                         clocks = <&ahb1_gates 22>, <&spi2_clk>;
 944                         clock-names = "ahb", "mod";
 945                         dmas = <&dma 25>, <&dma 25>;
 946                         dma-names = "rx", "tx";
 947                         resets = <&ahb1_rst 22>;
 948                         status = "disabled";
 949                 };
 950
 951                 spi3: spi@01c6b000 {
 952                         compatible = "allwinner,sun6i-a31-spi";
 953                         reg = <0x01c6b000 0x1000>;
 954                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 955                         clocks = <&ahb1_gates 23>, <&spi3_clk>;
 956                         clock-names = "ahb", "mod";
 957                         dmas = <&dma 26>, <&dma 26>;
 958                         dma-names = "rx", "tx";
 959                         resets = <&ahb1_rst 23>;
 960                         status = "disabled";
 961                 };
 962
 963                 gic: interrupt-controller@01c81000 {
 964                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 965                         reg = <0x01c81000 0x1000>,
 966                               <0x01c82000 0x1000>,
 967                               <0x01c84000 0x2000>,
 968                               <0x01c86000 0x2000>;
 969                         interrupt-controller;
 970                         #interrupt-cells = <3>;
 971                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 972                 };
 973
 974                 rtc: rtc@01f00000 {
 975                         compatible = "allwinner,sun6i-a31-rtc";
 976                         reg = <0x01f00000 0x54>;
 977                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 978                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 979                 };
 980
 981                 nmi_intc: interrupt-controller@01f00c0c {
 982                         compatible = "allwinner,sun6i-a31-sc-nmi";
 983                         interrupt-controller;
 984                         #interrupt-cells = <2>;
 985                         reg = <0x01f00c0c 0x38>;
 986                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 987                 };
 988
 989                 prcm@01f01400 {
 990                         compatible = "allwinner,sun6i-a31-prcm";
 991                         reg = <0x01f01400 0x200>;
 992
 993                         ar100: ar100_clk {
 994                                 compatible = "allwinner,sun6i-a31-ar100-clk";
 995                                 #clock-cells = <0>;
 996                                 clocks = <&osc32k>, <&osc24M>, <&pll6 0>,
 997                                          <&pll6 0>;
 998                                 clock-output-names = "ar100";
 999                         };
1000
1001                         ahb0: ahb0_clk {
1002                                 compatible = "fixed-factor-clock";
1003                                 #clock-cells = <0>;
1004                                 clock-div = <1>;
1005                                 clock-mult = <1>;
1006                                 clocks = <&ar100>;
1007                                 clock-output-names = "ahb0";
1008                         };
1009
1010                         apb0: apb0_clk {
1011                                 compatible = "allwinner,sun6i-a31-apb0-clk";
1012                                 #clock-cells = <0>;
1013                                 clocks = <&ahb0>;
1014                                 clock-output-names = "apb0";
1015                         };
1016
1017                         apb0_gates: apb0_gates_clk {
1018                                 compatible = "allwinner,sun6i-a31-apb0-gates-clk";
1019                                 #clock-cells = <1>;
1020                                 clocks = <&apb0>;
1021                                 clock-output-names = "apb0_pio", "apb0_ir",
1022                                                 "apb0_timer", "apb0_p2wi",
1023                                                 "apb0_uart", "apb0_1wire",
1024                                                 "apb0_i2c";
1025                         };
1026
1027                         ir_clk: ir_clk {
1028                                 #clock-cells = <0>;
1029                                 compatible = "allwinner,sun4i-a10-mod0-clk";
1030                                 clocks = <&osc32k>, <&osc24M>;
1031                                 clock-output-names = "ir";
1032                         };
1033
1034                         apb0_rst: apb0_rst {
1035                                 compatible = "allwinner,sun6i-a31-clock-reset";
1036                                 #reset-cells = <1>;
1037                         };
1038                 };
1039
1040                 cpucfg@01f01c00 {
1041                         compatible = "allwinner,sun6i-a31-cpuconfig";
1042                         reg = <0x01f01c00 0x300>;
1043                 };
1044
1045                 ir: ir@01f02000 {
1046                         compatible = "allwinner,sun5i-a13-ir";
1047                         clocks = <&apb0_gates 1>, <&ir_clk>;
1048                         clock-names = "apb", "ir";
1049                         resets = <&apb0_rst 1>;
1050                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1051                         reg = <0x01f02000 0x40>;
1052                         status = "disabled";
1053                 };
1054
1055                 r_pio: pinctrl@01f02c00 {
1056                         compatible = "allwinner,sun6i-a31-r-pinctrl";
1057                         reg = <0x01f02c00 0x400>;
1058                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1059                                      <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
1060                         clocks = <&apb0_gates 0>;
1061                         resets = <&apb0_rst 0>;
1062                         gpio-controller;
1063                         interrupt-controller;
1064                         #interrupt-cells = <2>;
1065                         #size-cells = <0>;
1066                         #gpio-cells = <3>;
1067
1068                         ir_pins_a: ir@0 {
1069                                 allwinner,pins = "PL4";
1070                                 allwinner,function = "s_ir";
1071                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1072                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1073                         };
1074
1075                         p2wi_pins: p2wi {
1076                                 allwinner,pins = "PL0", "PL1";
1077                                 allwinner,function = "s_p2wi";
1078                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1079                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1080                         };
1081                 };
1082
1083                 p2wi: i2c@01f03400 {
1084                         compatible = "allwinner,sun6i-a31-p2wi";
1085                         reg = <0x01f03400 0x400>;
1086                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1087                         clocks = <&apb0_gates 3>;
1088                         clock-frequency = <100000>;
1089                         resets = <&apb0_rst 3>;
1090                         pinctrl-names = "default";
1091                         pinctrl-0 = <&p2wi_pins>;
1092                         status = "disabled";
1093                         #address-cells = <1>;
1094                         #size-cells = <0>;
1095                 };
1096         };
1097 };