arch/arm/dts/sun50i-a64.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 // Copyright (C) 2016 ARM Ltd.
   3 // based on the Allwinner H3 dtsi:
   4 //    Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
   5
   6 #include <dt-bindings/clock/sun50i-a64-ccu.h>
   7 #include <dt-bindings/clock/sun6i-rtc.h>
   8 #include <dt-bindings/clock/sun8i-de2.h>
   9 #include <dt-bindings/clock/sun8i-r-ccu.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/reset/sun50i-a64-ccu.h>
  12 #include <dt-bindings/reset/sun8i-de2.h>
  13 #include <dt-bindings/reset/sun8i-r-ccu.h>
  14 #include <dt-bindings/thermal/thermal.h>
  15
  16 / {
  17         interrupt-parent = <&gic>;
  18         #address-cells = <1>;
  19         #size-cells = <1>;
  20
  21         chosen {
  22                 #address-cells = <1>;
  23                 #size-cells = <1>;
  24                 ranges;
  25
  26                 simplefb_lcd: framebuffer-lcd {
  27                         compatible = "allwinner,simple-framebuffer",
  28                                      "simple-framebuffer";
  29                         allwinner,pipeline = "mixer0-lcd0";
  30                         clocks = <&ccu CLK_TCON0>,
  31                                  <&display_clocks CLK_MIXER0>;
  32                         status = "disabled";
  33                 };
  34
  35                 simplefb_hdmi: framebuffer-hdmi {
  36                         compatible = "allwinner,simple-framebuffer",
  37                                      "simple-framebuffer";
  38                         allwinner,pipeline = "mixer1-lcd1-hdmi";
  39                         clocks = <&display_clocks CLK_MIXER1>,
  40                                  <&ccu CLK_TCON1>, <&ccu CLK_HDMI>;
  41                         status = "disabled";
  42                 };
  43         };
  44
  45         cpus {
  46                 #address-cells = <1>;
  47                 #size-cells = <0>;
  48
  49                 cpu0: cpu@0 {
  50                         compatible = "arm,cortex-a53";
  51                         device_type = "cpu";
  52                         reg = <0>;
  53                         enable-method = "psci";
  54                         next-level-cache = <&L2>;
  55                         clocks = <&ccu CLK_CPUX>;
  56                         clock-names = "cpu";
  57                         #cooling-cells = <2>;
  58                 };
  59
  60                 cpu1: cpu@1 {
  61                         compatible = "arm,cortex-a53";
  62                         device_type = "cpu";
  63                         reg = <1>;
  64                         enable-method = "psci";
  65                         next-level-cache = <&L2>;
  66                         clocks = <&ccu CLK_CPUX>;
  67                         clock-names = "cpu";
  68                         #cooling-cells = <2>;
  69                 };
  70
  71                 cpu2: cpu@2 {
  72                         compatible = "arm,cortex-a53";
  73                         device_type = "cpu";
  74                         reg = <2>;
  75                         enable-method = "psci";
  76                         next-level-cache = <&L2>;
  77                         clocks = <&ccu CLK_CPUX>;
  78                         clock-names = "cpu";
  79                         #cooling-cells = <2>;
  80                 };
  81
  82                 cpu3: cpu@3 {
  83                         compatible = "arm,cortex-a53";
  84                         device_type = "cpu";
  85                         reg = <3>;
  86                         enable-method = "psci";
  87                         next-level-cache = <&L2>;
  88                         clocks = <&ccu CLK_CPUX>;
  89                         clock-names = "cpu";
  90                         #cooling-cells = <2>;
  91                 };
  92
  93                 L2: l2-cache {
  94                         compatible = "cache";
  95                         cache-level = <2>;
  96                 };
  97         };
  98
  99         de: display-engine {
 100                 compatible = "allwinner,sun50i-a64-display-engine";
 101                 allwinner,pipelines = <&mixer0>,
 102                                       <&mixer1>;
 103                 status = "disabled";
 104         };
 105
 106         gpu_opp_table: opp-table-gpu {
 107                 compatible = "operating-points-v2";
 108
 109                 opp-120000000 {
 110                         opp-hz = /bits/ 64 <120000000>;
 111                 };
 112
 113                 opp-312000000 {
 114                         opp-hz = /bits/ 64 <312000000>;
 115                 };
 116
 117                 opp-432000000 {
 118                         opp-hz = /bits/ 64 <432000000>;
 119                 };
 120         };
 121
 122         osc24M: osc24M_clk {
 123                 #clock-cells = <0>;
 124                 compatible = "fixed-clock";
 125                 clock-frequency = <24000000>;
 126                 clock-output-names = "osc24M";
 127         };
 128
 129         osc32k: osc32k_clk {
 130                 #clock-cells = <0>;
 131                 compatible = "fixed-clock";
 132                 clock-frequency = <32768>;
 133                 clock-output-names = "ext-osc32k";
 134         };
 135
 136         pmu {
 137                 compatible = "arm,cortex-a53-pmu";
 138                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 139                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 140                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 141                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 142                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 143         };
 144
 145         psci {
 146                 compatible = "arm,psci-0.2";
 147                 method = "smc";
 148         };
 149
 150         sound: sound {
 151                 #address-cells = <1>;
 152                 #size-cells = <0>;
 153                 compatible = "simple-audio-card";
 154                 simple-audio-card,name = "sun50i-a64-audio";
 155                 simple-audio-card,aux-devs = <&codec_analog>;
 156                 simple-audio-card,routing =
 157                                 "Left DAC", "DACL",
 158                                 "Right DAC", "DACR",
 159                                 "ADCL", "Left ADC",
 160                                 "ADCR", "Right ADC";
 161                 status = "disabled";
 162
 163                 simple-audio-card,dai-link@0 {
 164                         format = "i2s";
 165                         frame-master = <&link0_cpu>;
 166                         bitclock-master = <&link0_cpu>;
 167                         mclk-fs = <128>;
 168
 169                         link0_cpu: cpu {
 170                                 sound-dai = <&dai>;
 171                         };
 172
 173                         link0_codec: codec {
 174                                 sound-dai = <&codec 0>;
 175                         };
 176                 };
 177         };
 178
 179         timer {
 180                 compatible = "arm,armv8-timer";
 181                 allwinner,erratum-unknown1;
 182                 arm,no-tick-in-suspend;
 183                 interrupts = <GIC_PPI 13
 184                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 185                              <GIC_PPI 14
 186                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 187                              <GIC_PPI 11
 188                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 189                              <GIC_PPI 10
 190                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 191         };
 192
 193         thermal-zones {
 194                 cpu_thermal: cpu0-thermal {
 195                         /* milliseconds */
 196                         polling-delay-passive = <0>;
 197                         polling-delay = <0>;
 198                         thermal-sensors = <&ths 0>;
 199
 200                         cooling-maps {
 201                                 map0 {
 202                                         trip = <&cpu_alert0>;
 203                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 204                                                          <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 205                                                          <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 206                                                          <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 207                                 };
 208                                 map1 {
 209                                         trip = <&cpu_alert1>;
 210                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 211                                                          <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 212                                                          <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 213                                                          <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 214                                 };
 215                         };
 216
 217                         trips {
 218                                 cpu_alert0: cpu_alert0 {
 219                                         /* milliCelsius */
 220                                         temperature = <75000>;
 221                                         hysteresis = <2000>;
 222                                         type = "passive";
 223                                 };
 224
 225                                 cpu_alert1: cpu_alert1 {
 226                                         /* milliCelsius */
 227                                         temperature = <90000>;
 228                                         hysteresis = <2000>;
 229                                         type = "hot";
 230                                 };
 231
 232                                 cpu_crit: cpu_crit {
 233                                         /* milliCelsius */
 234                                         temperature = <110000>;
 235                                         hysteresis = <2000>;
 236                                         type = "critical";
 237                                 };
 238                         };
 239                 };
 240
 241                 gpu0_thermal: gpu0-thermal {
 242                         /* milliseconds */
 243                         polling-delay-passive = <0>;
 244                         polling-delay = <0>;
 245                         thermal-sensors = <&ths 1>;
 246                 };
 247
 248                 gpu1_thermal: gpu1-thermal {
 249                         /* milliseconds */
 250                         polling-delay-passive = <0>;
 251                         polling-delay = <0>;
 252                         thermal-sensors = <&ths 2>;
 253                 };
 254         };
 255
 256         soc {
 257                 compatible = "simple-bus";
 258                 #address-cells = <1>;
 259                 #size-cells = <1>;
 260                 ranges;
 261
 262                 bus@1000000 {
 263                         compatible = "allwinner,sun50i-a64-de2";
 264                         reg = <0x1000000 0x400000>;
 265                         allwinner,sram = <&de2_sram 1>;
 266                         #address-cells = <1>;
 267                         #size-cells = <1>;
 268                         ranges = <0 0x1000000 0x400000>;
 269
 270                         display_clocks: clock@0 {
 271                                 compatible = "allwinner,sun50i-a64-de2-clk";
 272                                 reg = <0x0 0x10000>;
 273                                 clocks = <&ccu CLK_BUS_DE>,
 274                                          <&ccu CLK_DE>;
 275                                 clock-names = "bus",
 276                                               "mod";
 277                                 resets = <&ccu RST_BUS_DE>;
 278                                 #clock-cells = <1>;
 279                                 #reset-cells = <1>;
 280                         };
 281
 282                         rotate: rotate@20000 {
 283                                 compatible = "allwinner,sun50i-a64-de2-rotate",
 284                                              "allwinner,sun8i-a83t-de2-rotate";
 285                                 reg = <0x20000 0x10000>;
 286                                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 287                                 clocks = <&display_clocks CLK_BUS_ROT>,
 288                                          <&display_clocks CLK_ROT>;
 289                                 clock-names = "bus",
 290                                               "mod";
 291                                 resets = <&display_clocks RST_ROT>;
 292                         };
 293
 294                         mixer0: mixer@100000 {
 295                                 compatible = "allwinner,sun50i-a64-de2-mixer-0";
 296                                 reg = <0x100000 0x100000>;
 297                                 clocks = <&display_clocks CLK_BUS_MIXER0>,
 298                                          <&display_clocks CLK_MIXER0>;
 299                                 clock-names = "bus",
 300                                               "mod";
 301                                 resets = <&display_clocks RST_MIXER0>;
 302
 303                                 ports {
 304                                         #address-cells = <1>;
 305                                         #size-cells = <0>;
 306
 307                                         mixer0_out: port@1 {
 308                                                 #address-cells = <1>;
 309                                                 #size-cells = <0>;
 310                                                 reg = <1>;
 311
 312                                                 mixer0_out_tcon0: endpoint@0 {
 313                                                         reg = <0>;
 314                                                         remote-endpoint = <&tcon0_in_mixer0>;
 315                                                 };
 316
 317                                                 mixer0_out_tcon1: endpoint@1 {
 318                                                         reg = <1>;
 319                                                         remote-endpoint = <&tcon1_in_mixer0>;
 320                                                 };
 321                                         };
 322                                 };
 323                         };
 324
 325                         mixer1: mixer@200000 {
 326                                 compatible = "allwinner,sun50i-a64-de2-mixer-1";
 327                                 reg = <0x200000 0x100000>;
 328                                 clocks = <&display_clocks CLK_BUS_MIXER1>,
 329                                          <&display_clocks CLK_MIXER1>;
 330                                 clock-names = "bus",
 331                                               "mod";
 332                                 resets = <&display_clocks RST_MIXER1>;
 333
 334                                 ports {
 335                                         #address-cells = <1>;
 336                                         #size-cells = <0>;
 337
 338                                         mixer1_out: port@1 {
 339                                                 #address-cells = <1>;
 340                                                 #size-cells = <0>;
 341                                                 reg = <1>;
 342
 343                                                 mixer1_out_tcon0: endpoint@0 {
 344                                                         reg = <0>;
 345                                                         remote-endpoint = <&tcon0_in_mixer1>;
 346                                                 };
 347
 348                                                 mixer1_out_tcon1: endpoint@1 {
 349                                                         reg = <1>;
 350                                                         remote-endpoint = <&tcon1_in_mixer1>;
 351                                                 };
 352                                         };
 353                                 };
 354                         };
 355                 };
 356
 357                 syscon: syscon@1c00000 {
 358                         compatible = "allwinner,sun50i-a64-system-control";
 359                         reg = <0x01c00000 0x1000>;
 360                         #address-cells = <1>;
 361                         #size-cells = <1>;
 362                         ranges;
 363
 364                         sram_c: sram@18000 {
 365                                 compatible = "mmio-sram";
 366                                 reg = <0x00018000 0x28000>;
 367                                 #address-cells = <1>;
 368                                 #size-cells = <1>;
 369                                 ranges = <0 0x00018000 0x28000>;
 370
 371                                 de2_sram: sram-section@0 {
 372                                         compatible = "allwinner,sun50i-a64-sram-c";
 373                                         reg = <0x0000 0x28000>;
 374                                 };
 375                         };
 376
 377                         sram_c1: sram@1d00000 {
 378                                 compatible = "mmio-sram";
 379                                 reg = <0x01d00000 0x40000>;
 380                                 #address-cells = <1>;
 381                                 #size-cells = <1>;
 382                                 ranges = <0 0x01d00000 0x40000>;
 383
 384                                 ve_sram: sram-section@0 {
 385                                         compatible = "allwinner,sun50i-a64-sram-c1",
 386                                                      "allwinner,sun4i-a10-sram-c1";
 387                                         reg = <0x000000 0x40000>;
 388                                 };
 389                         };
 390                 };
 391
 392                 dma: dma-controller@1c02000 {
 393                         compatible = "allwinner,sun50i-a64-dma";
 394                         reg = <0x01c02000 0x1000>;
 395                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 396                         clocks = <&ccu CLK_BUS_DMA>;
 397                         dma-channels = <8>;
 398                         dma-requests = <27>;
 399                         resets = <&ccu RST_BUS_DMA>;
 400                         #dma-cells = <1>;
 401                 };
 402
 403                 tcon0: lcd-controller@1c0c000 {
 404                         compatible = "allwinner,sun50i-a64-tcon-lcd",
 405                                      "allwinner,sun8i-a83t-tcon-lcd";
 406                         reg = <0x01c0c000 0x1000>;
 407                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 408                         clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
 409                         clock-names = "ahb", "tcon-ch0";
 410                         clock-output-names = "tcon-pixel-clock";
 411                         #clock-cells = <0>;
 412                         resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
 413                         reset-names = "lcd", "lvds";
 414
 415                         ports {
 416                                 #address-cells = <1>;
 417                                 #size-cells = <0>;
 418
 419                                 tcon0_in: port@0 {
 420                                         #address-cells = <1>;
 421                                         #size-cells = <0>;
 422                                         reg = <0>;
 423
 424                                         tcon0_in_mixer0: endpoint@0 {
 425                                                 reg = <0>;
 426                                                 remote-endpoint = <&mixer0_out_tcon0>;
 427                                         };
 428
 429                                         tcon0_in_mixer1: endpoint@1 {
 430                                                 reg = <1>;
 431                                                 remote-endpoint = <&mixer1_out_tcon0>;
 432                                         };
 433                                 };
 434
 435                                 tcon0_out: port@1 {
 436                                         #address-cells = <1>;
 437                                         #size-cells = <0>;
 438                                         reg = <1>;
 439
 440                                         tcon0_out_dsi: endpoint@1 {
 441                                                 reg = <1>;
 442                                                 remote-endpoint = <&dsi_in_tcon0>;
 443                                                 allwinner,tcon-channel = <1>;
 444                                         };
 445                                 };
 446                         };
 447                 };
 448
 449                 tcon1: lcd-controller@1c0d000 {
 450                         compatible = "allwinner,sun50i-a64-tcon-tv",
 451                                      "allwinner,sun8i-a83t-tcon-tv";
 452                         reg = <0x01c0d000 0x1000>;
 453                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 454                         clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
 455                         clock-names = "ahb", "tcon-ch1";
 456                         resets = <&ccu RST_BUS_TCON1>;
 457                         reset-names = "lcd";
 458
 459                         ports {
 460                                 #address-cells = <1>;
 461                                 #size-cells = <0>;
 462
 463                                 tcon1_in: port@0 {
 464                                         #address-cells = <1>;
 465                                         #size-cells = <0>;
 466                                         reg = <0>;
 467
 468                                         tcon1_in_mixer0: endpoint@0 {
 469                                                 reg = <0>;
 470                                                 remote-endpoint = <&mixer0_out_tcon1>;
 471                                         };
 472
 473                                         tcon1_in_mixer1: endpoint@1 {
 474                                                 reg = <1>;
 475                                                 remote-endpoint = <&mixer1_out_tcon1>;
 476                                         };
 477                                 };
 478
 479                                 tcon1_out: port@1 {
 480                                         #address-cells = <1>;
 481                                         #size-cells = <0>;
 482                                         reg = <1>;
 483
 484                                         tcon1_out_hdmi: endpoint@1 {
 485                                                 reg = <1>;
 486                                                 remote-endpoint = <&hdmi_in_tcon1>;
 487                                         };
 488                                 };
 489                         };
 490                 };
 491
 492                 video-codec@1c0e000 {
 493                         compatible = "allwinner,sun50i-a64-video-engine";
 494                         reg = <0x01c0e000 0x1000>;
 495                         clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
 496                                  <&ccu CLK_DRAM_VE>;
 497                         clock-names = "ahb", "mod", "ram";
 498                         resets = <&ccu RST_BUS_VE>;
 499                         interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 500                         allwinner,sram = <&ve_sram 1>;
 501                 };
 502
 503                 mmc0: mmc@1c0f000 {
 504                         compatible = "allwinner,sun50i-a64-mmc";
 505                         reg = <0x01c0f000 0x1000>;
 506                         clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
 507                         clock-names = "ahb", "mmc";
 508                         resets = <&ccu RST_BUS_MMC0>;
 509                         reset-names = "ahb";
 510                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 511                         max-frequency = <150000000>;
 512                         status = "disabled";
 513                         #address-cells = <1>;
 514                         #size-cells = <0>;
 515                 };
 516
 517                 mmc1: mmc@1c10000 {
 518                         compatible = "allwinner,sun50i-a64-mmc";
 519                         reg = <0x01c10000 0x1000>;
 520                         clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
 521                         clock-names = "ahb", "mmc";
 522                         resets = <&ccu RST_BUS_MMC1>;
 523                         reset-names = "ahb";
 524                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 525                         max-frequency = <150000000>;
 526                         status = "disabled";
 527                         #address-cells = <1>;
 528                         #size-cells = <0>;
 529                 };
 530
 531                 mmc2: mmc@1c11000 {
 532                         compatible = "allwinner,sun50i-a64-emmc";
 533                         reg = <0x01c11000 0x1000>;
 534                         clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
 535                         clock-names = "ahb", "mmc";
 536                         resets = <&ccu RST_BUS_MMC2>;
 537                         reset-names = "ahb";
 538                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 539                         max-frequency = <150000000>;
 540                         status = "disabled";
 541                         #address-cells = <1>;
 542                         #size-cells = <0>;
 543                 };
 544
 545                 sid: eeprom@1c14000 {
 546                         compatible = "allwinner,sun50i-a64-sid";
 547                         reg = <0x1c14000 0x400>;
 548                         #address-cells = <1>;
 549                         #size-cells = <1>;
 550
 551                         ths_calibration: thermal-sensor-calibration@34 {
 552                                 reg = <0x34 0x8>;
 553                         };
 554                 };
 555
 556                 crypto: crypto@1c15000 {
 557                         compatible = "allwinner,sun50i-a64-crypto";
 558                         reg = <0x01c15000 0x1000>;
 559                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 560                         clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
 561                         clock-names = "bus", "mod";
 562                         resets = <&ccu RST_BUS_CE>;
 563                 };
 564
 565                 msgbox: mailbox@1c17000 {
 566                         compatible = "allwinner,sun50i-a64-msgbox",
 567                                      "allwinner,sun6i-a31-msgbox";
 568                         reg = <0x01c17000 0x1000>;
 569                         clocks = <&ccu CLK_BUS_MSGBOX>;
 570                         resets = <&ccu RST_BUS_MSGBOX>;
 571                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 572                         #mbox-cells = <1>;
 573                 };
 574
 575                 usb_otg: usb@1c19000 {
 576                         compatible = "allwinner,sun8i-a33-musb";
 577                         reg = <0x01c19000 0x0400>;
 578                         clocks = <&ccu CLK_BUS_OTG>;
 579                         resets = <&ccu RST_BUS_OTG>;
 580                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 581                         interrupt-names = "mc";
 582                         phys = <&usbphy 0>;
 583                         phy-names = "usb";
 584                         extcon = <&usbphy 0>;
 585                         dr_mode = "otg";
 586                         status = "disabled";
 587                 };
 588
 589                 usbphy: phy@1c19400 {
 590                         compatible = "allwinner,sun50i-a64-usb-phy";
 591                         reg = <0x01c19400 0x14>,
 592                               <0x01c1a800 0x4>,
 593                               <0x01c1b800 0x4>;
 594                         reg-names = "phy_ctrl",
 595                                     "pmu0",
 596                                     "pmu1";
 597                         clocks = <&ccu CLK_USB_PHY0>,
 598                                  <&ccu CLK_USB_PHY1>;
 599                         clock-names = "usb0_phy",
 600                                       "usb1_phy";
 601                         resets = <&ccu RST_USB_PHY0>,
 602                                  <&ccu RST_USB_PHY1>;
 603                         reset-names = "usb0_reset",
 604                                       "usb1_reset";
 605                         status = "disabled";
 606                         #phy-cells = <1>;
 607                 };
 608
 609                 ehci0: usb@1c1a000 {
 610                         compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
 611                         reg = <0x01c1a000 0x100>;
 612                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 613                         clocks = <&ccu CLK_BUS_OHCI0>,
 614                                  <&ccu CLK_BUS_EHCI0>,
 615                                  <&ccu CLK_USB_OHCI0>;
 616                         resets = <&ccu RST_BUS_OHCI0>,
 617                                  <&ccu RST_BUS_EHCI0>;
 618                         phys = <&usbphy 0>;
 619                         phy-names = "usb";
 620                         status = "disabled";
 621                 };
 622
 623                 ohci0: usb@1c1a400 {
 624                         compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
 625                         reg = <0x01c1a400 0x100>;
 626                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 627                         clocks = <&ccu CLK_BUS_OHCI0>,
 628                                  <&ccu CLK_USB_OHCI0>;
 629                         resets = <&ccu RST_BUS_OHCI0>;
 630                         phys = <&usbphy 0>;
 631                         phy-names = "usb";
 632                         status = "disabled";
 633                 };
 634
 635                 ehci1: usb@1c1b000 {
 636                         compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
 637                         reg = <0x01c1b000 0x100>;
 638                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 639                         clocks = <&ccu CLK_BUS_OHCI1>,
 640                                  <&ccu CLK_BUS_EHCI1>,
 641                                  <&ccu CLK_USB_OHCI1>;
 642                         resets = <&ccu RST_BUS_OHCI1>,
 643                                  <&ccu RST_BUS_EHCI1>;
 644                         phys = <&usbphy 1>;
 645                         phy-names = "usb";
 646                         status = "disabled";
 647                 };
 648
 649                 ohci1: usb@1c1b400 {
 650                         compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
 651                         reg = <0x01c1b400 0x100>;
 652                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 653                         clocks = <&ccu CLK_BUS_OHCI1>,
 654                                  <&ccu CLK_USB_OHCI1>;
 655                         resets = <&ccu RST_BUS_OHCI1>;
 656                         phys = <&usbphy 1>;
 657                         phy-names = "usb";
 658                         status = "disabled";
 659                 };
 660
 661                 ccu: clock@1c20000 {
 662                         compatible = "allwinner,sun50i-a64-ccu";
 663                         reg = <0x01c20000 0x400>;
 664                         clocks = <&osc24M>, <&rtc CLK_OSC32K>;
 665                         clock-names = "hosc", "losc";
 666                         #clock-cells = <1>;
 667                         #reset-cells = <1>;
 668                 };
 669
 670                 pio: pinctrl@1c20800 {
 671                         compatible = "allwinner,sun50i-a64-pinctrl";
 672                         reg = <0x01c20800 0x400>;
 673                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 674                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 675                                      <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 676                         clocks = <&ccu CLK_BUS_PIO>, <&osc24M>,
 677                                  <&rtc CLK_OSC32K>;
 678                         clock-names = "apb", "hosc", "losc";
 679                         gpio-controller;
 680                         #gpio-cells = <3>;
 681                         interrupt-controller;
 682                         #interrupt-cells = <3>;
 683
 684                         /omit-if-no-ref/
 685                         aif2_pins: aif2-pins {
 686                                 pins = "PB4", "PB5", "PB6", "PB7";
 687                                 function = "aif2";
 688                         };
 689
 690                         /omit-if-no-ref/
 691                         aif3_pins: aif3-pins {
 692                                 pins = "PG10", "PG11", "PG12", "PG13";
 693                                 function = "aif3";
 694                         };
 695
 696                         csi_pins: csi-pins {
 697                                 pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6",
 698                                        "PE7", "PE8", "PE9", "PE10", "PE11";
 699                                 function = "csi";
 700                         };
 701
 702                         /omit-if-no-ref/
 703                         csi_mclk_pin: csi-mclk-pin {
 704                                 pins = "PE1";
 705                                 function = "csi";
 706                         };
 707
 708                         i2c0_pins: i2c0-pins {
 709                                 pins = "PH0", "PH1";
 710                                 function = "i2c0";
 711                         };
 712
 713                         i2c1_pins: i2c1-pins {
 714                                 pins = "PH2", "PH3";
 715                                 function = "i2c1";
 716                         };
 717
 718                         i2c2_pins: i2c2-pins {
 719                                 pins = "PE14", "PE15";
 720                                 function = "i2c2";
 721                         };
 722
 723                         /omit-if-no-ref/
 724                         lcd_rgb666_pins: lcd-rgb666-pins {
 725                                 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
 726                                        "PD5", "PD6", "PD7", "PD8", "PD9",
 727                                        "PD10", "PD11", "PD12", "PD13",
 728                                        "PD14", "PD15", "PD16", "PD17",
 729                                        "PD18", "PD19", "PD20", "PD21";
 730                                 function = "lcd0";
 731                         };
 732
 733                         mmc0_pins: mmc0-pins {
 734                                 pins = "PF0", "PF1", "PF2", "PF3",
 735                                        "PF4", "PF5";
 736                                 function = "mmc0";
 737                                 drive-strength = <30>;
 738                                 bias-pull-up;
 739                         };
 740
 741                         mmc1_pins: mmc1-pins {
 742                                 pins = "PG0", "PG1", "PG2", "PG3",
 743                                        "PG4", "PG5";
 744                                 function = "mmc1";
 745                                 drive-strength = <30>;
 746                                 bias-pull-up;
 747                         };
 748
 749                         mmc2_pins: mmc2-pins {
 750                                 pins = "PC5", "PC6", "PC8", "PC9",
 751                                        "PC10","PC11", "PC12", "PC13",
 752                                        "PC14", "PC15", "PC16";
 753                                 function = "mmc2";
 754                                 drive-strength = <30>;
 755                                 bias-pull-up;
 756                         };
 757
 758                         mmc2_ds_pin: mmc2-ds-pin {
 759                                 pins = "PC1";
 760                                 function = "mmc2";
 761                                 drive-strength = <30>;
 762                                 bias-pull-up;
 763                         };
 764
 765                         pwm_pin: pwm-pin {
 766                                 pins = "PD22";
 767                                 function = "pwm";
 768                         };
 769
 770                         rmii_pins: rmii-pins {
 771                                 pins = "PD10", "PD11", "PD13", "PD14", "PD17",
 772                                        "PD18", "PD19", "PD20", "PD22", "PD23";
 773                                 function = "emac";
 774                                 drive-strength = <40>;
 775                         };
 776
 777                         rgmii_pins: rgmii-pins {
 778                                 pins = "PD8", "PD9", "PD10", "PD11", "PD12",
 779                                        "PD13", "PD15", "PD16", "PD17", "PD18",
 780                                        "PD19", "PD20", "PD21", "PD22", "PD23";
 781                                 function = "emac";
 782                                 drive-strength = <40>;
 783                         };
 784
 785                         spdif_tx_pin: spdif-tx-pin {
 786                                 pins = "PH8";
 787                                 function = "spdif";
 788                         };
 789
 790                         spi0_pins: spi0-pins {
 791                                 pins = "PC0", "PC1", "PC2", "PC3";
 792                                 function = "spi0";
 793                         };
 794
 795                         spi1_pins: spi1-pins {
 796                                 pins = "PD0", "PD1", "PD2", "PD3";
 797                                 function = "spi1";
 798                         };
 799
 800                         uart0_pb_pins: uart0-pb-pins {
 801                                 pins = "PB8", "PB9";
 802                                 function = "uart0";
 803                         };
 804
 805                         uart1_pins: uart1-pins {
 806                                 pins = "PG6", "PG7";
 807                                 function = "uart1";
 808                         };
 809
 810                         uart1_rts_cts_pins: uart1-rts-cts-pins {
 811                                 pins = "PG8", "PG9";
 812                                 function = "uart1";
 813                         };
 814
 815                         uart2_pins: uart2-pins {
 816                                 pins = "PB0", "PB1";
 817                                 function = "uart2";
 818                         };
 819
 820                         uart3_pins: uart3-pins {
 821                                 pins = "PD0", "PD1";
 822                                 function = "uart3";
 823                         };
 824
 825                         uart4_pins: uart4-pins {
 826                                 pins = "PD2", "PD3";
 827                                 function = "uart4";
 828                         };
 829
 830                         uart4_rts_cts_pins: uart4-rts-cts-pins {
 831                                 pins = "PD4", "PD5";
 832                                 function = "uart4";
 833                         };
 834                 };
 835
 836                 timer@1c20c00 {
 837                         compatible = "allwinner,sun50i-a64-timer",
 838                                      "allwinner,sun8i-a23-timer";
 839                         reg = <0x01c20c00 0xa0>;
 840                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 841                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 842                         clocks = <&osc24M>;
 843                 };
 844
 845                 wdt0: watchdog@1c20ca0 {
 846                         compatible = "allwinner,sun50i-a64-wdt",
 847                                      "allwinner,sun6i-a31-wdt";
 848                         reg = <0x01c20ca0 0x20>;
 849                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 850                         clocks = <&osc24M>;
 851                 };
 852
 853                 spdif: spdif@1c21000 {
 854                         #sound-dai-cells = <0>;
 855                         compatible = "allwinner,sun50i-a64-spdif",
 856                                      "allwinner,sun8i-h3-spdif";
 857                         reg = <0x01c21000 0x400>;
 858                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 859                         clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
 860                         resets = <&ccu RST_BUS_SPDIF>;
 861                         clock-names = "apb", "spdif";
 862                         dmas = <&dma 2>;
 863                         dma-names = "tx";
 864                         pinctrl-names = "default";
 865                         pinctrl-0 = <&spdif_tx_pin>;
 866                         status = "disabled";
 867                 };
 868
 869                 lradc: lradc@1c21800 {
 870                         compatible = "allwinner,sun50i-a64-lradc",
 871                                      "allwinner,sun8i-a83t-r-lradc";
 872                         reg = <0x01c21800 0x400>;
 873                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 874                         status = "disabled";
 875                 };
 876
 877                 i2s0: i2s@1c22000 {
 878                         #sound-dai-cells = <0>;
 879                         compatible = "allwinner,sun50i-a64-i2s",
 880                                      "allwinner,sun8i-h3-i2s";
 881                         reg = <0x01c22000 0x400>;
 882                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 883                         clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
 884                         clock-names = "apb", "mod";
 885                         resets = <&ccu RST_BUS_I2S0>;
 886                         dma-names = "rx", "tx";
 887                         dmas = <&dma 3>, <&dma 3>;
 888                         status = "disabled";
 889                 };
 890
 891                 i2s1: i2s@1c22400 {
 892                         #sound-dai-cells = <0>;
 893                         compatible = "allwinner,sun50i-a64-i2s",
 894                                      "allwinner,sun8i-h3-i2s";
 895                         reg = <0x01c22400 0x400>;
 896                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 897                         clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
 898                         clock-names = "apb", "mod";
 899                         resets = <&ccu RST_BUS_I2S1>;
 900                         dma-names = "rx", "tx";
 901                         dmas = <&dma 4>, <&dma 4>;
 902                         status = "disabled";
 903                 };
 904
 905                 i2s2: i2s@1c22800 {
 906                         #sound-dai-cells = <0>;
 907                         compatible = "allwinner,sun50i-a64-i2s",
 908                                      "allwinner,sun8i-h3-i2s";
 909                         reg = <0x01c22800 0x400>;
 910                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 911                         clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
 912                         clock-names = "apb", "mod";
 913                         resets = <&ccu RST_BUS_I2S2>;
 914                         dma-names = "rx", "tx";
 915                         dmas = <&dma 27>, <&dma 27>;
 916                         status = "disabled";
 917                 };
 918
 919                 dai: dai@1c22c00 {
 920                         #sound-dai-cells = <0>;
 921                         compatible = "allwinner,sun50i-a64-codec-i2s";
 922                         reg = <0x01c22c00 0x200>;
 923                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 924                         clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
 925                         clock-names = "apb", "mod";
 926                         resets = <&ccu RST_BUS_CODEC>;
 927                         dmas = <&dma 15>, <&dma 15>;
 928                         dma-names = "rx", "tx";
 929                         status = "disabled";
 930                 };
 931
 932                 codec: codec@1c22e00 {
 933                         #sound-dai-cells = <1>;
 934                         compatible = "allwinner,sun50i-a64-codec",
 935                                      "allwinner,sun8i-a33-codec";
 936                         reg = <0x01c22e00 0x600>;
 937                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 938                         clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
 939                         clock-names = "bus", "mod";
 940                         status = "disabled";
 941                 };
 942
 943                 ths: thermal-sensor@1c25000 {
 944                         compatible = "allwinner,sun50i-a64-ths";
 945                         reg = <0x01c25000 0x100>;
 946                         clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
 947                         clock-names = "bus", "mod";
 948                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 949                         resets = <&ccu RST_BUS_THS>;
 950                         nvmem-cells = <&ths_calibration>;
 951                         nvmem-cell-names = "calibration";
 952                         #thermal-sensor-cells = <1>;
 953                 };
 954
 955                 uart0: serial@1c28000 {
 956                         compatible = "snps,dw-apb-uart";
 957                         reg = <0x01c28000 0x400>;
 958                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 959                         reg-shift = <2>;
 960                         reg-io-width = <4>;
 961                         clocks = <&ccu CLK_BUS_UART0>;
 962                         resets = <&ccu RST_BUS_UART0>;
 963                         status = "disabled";
 964                 };
 965
 966                 uart1: serial@1c28400 {
 967                         compatible = "snps,dw-apb-uart";
 968                         reg = <0x01c28400 0x400>;
 969                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 970                         reg-shift = <2>;
 971                         reg-io-width = <4>;
 972                         clocks = <&ccu CLK_BUS_UART1>;
 973                         resets = <&ccu RST_BUS_UART1>;
 974                         status = "disabled";
 975                 };
 976
 977                 uart2: serial@1c28800 {
 978                         compatible = "snps,dw-apb-uart";
 979                         reg = <0x01c28800 0x400>;
 980                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 981                         reg-shift = <2>;
 982                         reg-io-width = <4>;
 983                         clocks = <&ccu CLK_BUS_UART2>;
 984                         resets = <&ccu RST_BUS_UART2>;
 985                         status = "disabled";
 986                 };
 987
 988                 uart3: serial@1c28c00 {
 989                         compatible = "snps,dw-apb-uart";
 990                         reg = <0x01c28c00 0x400>;
 991                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 992                         reg-shift = <2>;
 993                         reg-io-width = <4>;
 994                         clocks = <&ccu CLK_BUS_UART3>;
 995                         resets = <&ccu RST_BUS_UART3>;
 996                         status = "disabled";
 997                 };
 998
 999                 uart4: serial@1c29000 {
1000                         compatible = "snps,dw-apb-uart";
1001                         reg = <0x01c29000 0x400>;
1002                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1003                         reg-shift = <2>;
1004                         reg-io-width = <4>;
1005                         clocks = <&ccu CLK_BUS_UART4>;
1006                         resets = <&ccu RST_BUS_UART4>;
1007                         status = "disabled";
1008                 };
1009
1010                 i2c0: i2c@1c2ac00 {
1011                         compatible = "allwinner,sun6i-a31-i2c";
1012                         reg = <0x01c2ac00 0x400>;
1013                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1014                         clocks = <&ccu CLK_BUS_I2C0>;
1015                         resets = <&ccu RST_BUS_I2C0>;
1016                         pinctrl-names = "default";
1017                         pinctrl-0 = <&i2c0_pins>;
1018                         status = "disabled";
1019                         #address-cells = <1>;
1020                         #size-cells = <0>;
1021                 };
1022
1023                 i2c1: i2c@1c2b000 {
1024                         compatible = "allwinner,sun6i-a31-i2c";
1025                         reg = <0x01c2b000 0x400>;
1026                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1027                         clocks = <&ccu CLK_BUS_I2C1>;
1028                         resets = <&ccu RST_BUS_I2C1>;
1029                         pinctrl-names = "default";
1030                         pinctrl-0 = <&i2c1_pins>;
1031                         status = "disabled";
1032                         #address-cells = <1>;
1033                         #size-cells = <0>;
1034                 };
1035
1036                 i2c2: i2c@1c2b400 {
1037                         compatible = "allwinner,sun6i-a31-i2c";
1038                         reg = <0x01c2b400 0x400>;
1039                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1040                         clocks = <&ccu CLK_BUS_I2C2>;
1041                         resets = <&ccu RST_BUS_I2C2>;
1042                         pinctrl-names = "default";
1043                         pinctrl-0 = <&i2c2_pins>;
1044                         status = "disabled";
1045                         #address-cells = <1>;
1046                         #size-cells = <0>;
1047                 };
1048
1049                 spi0: spi@1c68000 {
1050                         compatible = "allwinner,sun8i-h3-spi";
1051                         reg = <0x01c68000 0x1000>;
1052                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
1053                         clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
1054                         clock-names = "ahb", "mod";
1055                         dmas = <&dma 23>, <&dma 23>;
1056                         dma-names = "rx", "tx";
1057                         pinctrl-names = "default";
1058                         pinctrl-0 = <&spi0_pins>;
1059                         resets = <&ccu RST_BUS_SPI0>;
1060                         status = "disabled";
1061                         num-cs = <1>;
1062                         #address-cells = <1>;
1063                         #size-cells = <0>;
1064                 };
1065
1066                 spi1: spi@1c69000 {
1067                         compatible = "allwinner,sun8i-h3-spi";
1068                         reg = <0x01c69000 0x1000>;
1069                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1070                         clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
1071                         clock-names = "ahb", "mod";
1072                         dmas = <&dma 24>, <&dma 24>;
1073                         dma-names = "rx", "tx";
1074                         pinctrl-names = "default";
1075                         pinctrl-0 = <&spi1_pins>;
1076                         resets = <&ccu RST_BUS_SPI1>;
1077                         status = "disabled";
1078                         num-cs = <1>;
1079                         #address-cells = <1>;
1080                         #size-cells = <0>;
1081                 };
1082
1083                 emac: ethernet@1c30000 {
1084                         compatible = "allwinner,sun50i-a64-emac";
1085                         syscon = <&syscon>;
1086                         reg = <0x01c30000 0x10000>;
1087                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1088                         interrupt-names = "macirq";
1089                         resets = <&ccu RST_BUS_EMAC>;
1090                         reset-names = "stmmaceth";
1091                         clocks = <&ccu CLK_BUS_EMAC>;
1092                         clock-names = "stmmaceth";
1093                         status = "disabled";
1094
1095                         mdio: mdio {
1096                                 compatible = "snps,dwmac-mdio";
1097                                 #address-cells = <1>;
1098                                 #size-cells = <0>;
1099                         };
1100                 };
1101
1102                 mali: gpu@1c40000 {
1103                         compatible = "allwinner,sun50i-a64-mali", "arm,mali-400";
1104                         reg = <0x01c40000 0x10000>;
1105                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1106                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1107                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1108                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1109                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1110                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1111                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1112                         interrupt-names = "gp",
1113                                           "gpmmu",
1114                                           "pp0",
1115                                           "ppmmu0",
1116                                           "pp1",
1117                                           "ppmmu1",
1118                                           "pmu";
1119                         clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
1120                         clock-names = "bus", "core";
1121                         resets = <&ccu RST_BUS_GPU>;
1122                         operating-points-v2 = <&gpu_opp_table>;
1123                 };
1124
1125                 gic: interrupt-controller@1c81000 {
1126                         compatible = "arm,gic-400";
1127                         reg = <0x01c81000 0x1000>,
1128                               <0x01c82000 0x2000>,
1129                               <0x01c84000 0x2000>,
1130                               <0x01c86000 0x2000>;
1131                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1132                         interrupt-controller;
1133                         #interrupt-cells = <3>;
1134                 };
1135
1136                 pwm: pwm@1c21400 {
1137                         compatible = "allwinner,sun50i-a64-pwm",
1138                                      "allwinner,sun5i-a13-pwm";
1139                         reg = <0x01c21400 0x400>;
1140                         clocks = <&osc24M>;
1141                         pinctrl-names = "default";
1142                         pinctrl-0 = <&pwm_pin>;
1143                         #pwm-cells = <3>;
1144                         status = "disabled";
1145                 };
1146
1147                 mbus: dram-controller@1c62000 {
1148                         compatible = "allwinner,sun50i-a64-mbus";
1149                         reg = <0x01c62000 0x1000>,
1150                               <0x01c63000 0x1000>;
1151                         reg-names = "mbus", "dram";
1152                         clocks = <&ccu CLK_MBUS>,
1153                                  <&ccu CLK_DRAM>,
1154                                  <&ccu CLK_BUS_DRAM>;
1155                         clock-names = "mbus", "dram", "bus";
1156                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
1157                         #address-cells = <1>;
1158                         #size-cells = <1>;
1159                         dma-ranges = <0x00000000 0x40000000 0xc0000000>;
1160                         #interconnect-cells = <1>;
1161                 };
1162
1163                 csi: csi@1cb0000 {
1164                         compatible = "allwinner,sun50i-a64-csi";
1165                         reg = <0x01cb0000 0x1000>;
1166                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1167                         clocks = <&ccu CLK_BUS_CSI>,
1168                                  <&ccu CLK_CSI_SCLK>,
1169                                  <&ccu CLK_DRAM_CSI>;
1170                         clock-names = "bus", "mod", "ram";
1171                         resets = <&ccu RST_BUS_CSI>;
1172                         pinctrl-names = "default";
1173                         pinctrl-0 = <&csi_pins>;
1174                         status = "disabled";
1175                 };
1176
1177                 dsi: dsi@1ca0000 {
1178                         compatible = "allwinner,sun50i-a64-mipi-dsi";
1179                         reg = <0x01ca0000 0x1000>;
1180                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1181                         clocks = <&ccu CLK_BUS_MIPI_DSI>;
1182                         resets = <&ccu RST_BUS_MIPI_DSI>;
1183                         phys = <&dphy>;
1184                         phy-names = "dphy";
1185                         status = "disabled";
1186                         #address-cells = <1>;
1187                         #size-cells = <0>;
1188
1189                         port {
1190                                 dsi_in_tcon0: endpoint {
1191                                         remote-endpoint = <&tcon0_out_dsi>;
1192                                 };
1193                         };
1194                 };
1195
1196                 dphy: d-phy@1ca1000 {
1197                         compatible = "allwinner,sun50i-a64-mipi-dphy",
1198                                      "allwinner,sun6i-a31-mipi-dphy";
1199                         reg = <0x01ca1000 0x1000>;
1200                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1201                         clocks = <&ccu CLK_BUS_MIPI_DSI>,
1202                                  <&ccu CLK_DSI_DPHY>;
1203                         clock-names = "bus", "mod";
1204                         resets = <&ccu RST_BUS_MIPI_DSI>;
1205                         status = "disabled";
1206                         #phy-cells = <0>;
1207                 };
1208
1209                 deinterlace: deinterlace@1e00000 {
1210                         compatible = "allwinner,sun50i-a64-deinterlace",
1211                                      "allwinner,sun8i-h3-deinterlace";
1212                         reg = <0x01e00000 0x20000>;
1213                         clocks = <&ccu CLK_BUS_DEINTERLACE>,
1214                                  <&ccu CLK_DEINTERLACE>,
1215                                  <&ccu CLK_DRAM_DEINTERLACE>;
1216                         clock-names = "bus", "mod", "ram";
1217                         resets = <&ccu RST_BUS_DEINTERLACE>;
1218                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1219                         interconnects = <&mbus 9>;
1220                         interconnect-names = "dma-mem";
1221                 };
1222
1223                 hdmi: hdmi@1ee0000 {
1224                         compatible = "allwinner,sun50i-a64-dw-hdmi",
1225                                      "allwinner,sun8i-a83t-dw-hdmi";
1226                         reg = <0x01ee0000 0x10000>;
1227                         reg-io-width = <1>;
1228                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1229                         clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
1230                                  <&ccu CLK_HDMI>, <&rtc CLK_OSC32K>;
1231                         clock-names = "iahb", "isfr", "tmds", "cec";
1232                         resets = <&ccu RST_BUS_HDMI1>;
1233                         reset-names = "ctrl";
1234                         phys = <&hdmi_phy>;
1235                         phy-names = "phy";
1236                         status = "disabled";
1237
1238                         ports {
1239                                 #address-cells = <1>;
1240                                 #size-cells = <0>;
1241
1242                                 hdmi_in: port@0 {
1243                                         reg = <0>;
1244
1245                                         hdmi_in_tcon1: endpoint {
1246                                                 remote-endpoint = <&tcon1_out_hdmi>;
1247                                         };
1248                                 };
1249
1250                                 hdmi_out: port@1 {
1251                                         reg = <1>;
1252                                 };
1253                         };
1254                 };
1255
1256                 hdmi_phy: hdmi-phy@1ef0000 {
1257                         compatible = "allwinner,sun50i-a64-hdmi-phy";
1258                         reg = <0x01ef0000 0x10000>;
1259                         clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
1260                                  <&ccu CLK_PLL_VIDEO0>;
1261                         clock-names = "bus", "mod", "pll-0";
1262                         resets = <&ccu RST_BUS_HDMI0>;
1263                         reset-names = "phy";
1264                         #phy-cells = <0>;
1265                 };
1266
1267                 rtc: rtc@1f00000 {
1268                         compatible = "allwinner,sun50i-a64-rtc",
1269                                      "allwinner,sun8i-h3-rtc";
1270                         reg = <0x01f00000 0x400>;
1271                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1272                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1273                         clock-output-names = "osc32k", "osc32k-out", "iosc";
1274                         clocks = <&osc32k>;
1275                         #clock-cells = <1>;
1276                 };
1277
1278                 r_intc: interrupt-controller@1f00c00 {
1279                         compatible = "allwinner,sun50i-a64-r-intc",
1280                                      "allwinner,sun6i-a31-r-intc";
1281                         interrupt-controller;
1282                         #interrupt-cells = <2>;
1283                         reg = <0x01f00c00 0x400>;
1284                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1285                 };
1286
1287                 r_ccu: clock@1f01400 {
1288                         compatible = "allwinner,sun50i-a64-r-ccu";
1289                         reg = <0x01f01400 0x100>;
1290                         clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>,
1291                                  <&ccu CLK_PLL_PERIPH0>;
1292                         clock-names = "hosc", "losc", "iosc", "pll-periph";
1293                         #clock-cells = <1>;
1294                         #reset-cells = <1>;
1295                 };
1296
1297                 codec_analog: codec-analog@1f015c0 {
1298                         compatible = "allwinner,sun50i-a64-codec-analog";
1299                         reg = <0x01f015c0 0x4>;
1300                         status = "disabled";
1301                 };
1302
1303                 r_i2c: i2c@1f02400 {
1304                         compatible = "allwinner,sun50i-a64-i2c",
1305                                      "allwinner,sun6i-a31-i2c";
1306                         reg = <0x01f02400 0x400>;
1307                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1308                         clocks = <&r_ccu CLK_APB0_I2C>;
1309                         resets = <&r_ccu RST_APB0_I2C>;
1310                         status = "disabled";
1311                         #address-cells = <1>;
1312                         #size-cells = <0>;
1313                 };
1314
1315                 r_ir: ir@1f02000 {
1316                         compatible = "allwinner,sun50i-a64-ir",
1317                                      "allwinner,sun6i-a31-ir";
1318                         reg = <0x01f02000 0x400>;
1319                         clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
1320                         clock-names = "apb", "ir";
1321                         resets = <&r_ccu RST_APB0_IR>;
1322                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1323                         pinctrl-names = "default";
1324                         pinctrl-0 = <&r_ir_rx_pin>;
1325                         status = "disabled";
1326                 };
1327
1328                 r_pwm: pwm@1f03800 {
1329                         compatible = "allwinner,sun50i-a64-pwm",
1330                                      "allwinner,sun5i-a13-pwm";
1331                         reg = <0x01f03800 0x400>;
1332                         clocks = <&osc24M>;
1333                         pinctrl-names = "default";
1334                         pinctrl-0 = <&r_pwm_pin>;
1335                         #pwm-cells = <3>;
1336                         status = "disabled";
1337                 };
1338
1339                 r_pio: pinctrl@1f02c00 {
1340                         compatible = "allwinner,sun50i-a64-r-pinctrl";
1341                         reg = <0x01f02c00 0x400>;
1342                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1343                         clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
1344                         clock-names = "apb", "hosc", "losc";
1345                         gpio-controller;
1346                         #gpio-cells = <3>;
1347                         interrupt-controller;
1348                         #interrupt-cells = <3>;
1349
1350                         r_i2c_pl89_pins: r-i2c-pl89-pins {
1351                                 pins = "PL8", "PL9";
1352                                 function = "s_i2c";
1353                         };
1354
1355                         r_ir_rx_pin: r-ir-rx-pin {
1356                                 pins = "PL11";
1357                                 function = "s_cir_rx";
1358                         };
1359
1360                         r_pwm_pin: r-pwm-pin {
1361                                 pins = "PL10";
1362                                 function = "s_pwm";
1363                         };
1364
1365                         r_rsb_pins: r-rsb-pins {
1366                                 pins = "PL0", "PL1";
1367                                 function = "s_rsb";
1368                         };
1369                 };
1370
1371                 r_rsb: rsb@1f03400 {
1372                         compatible = "allwinner,sun8i-a23-rsb";
1373                         reg = <0x01f03400 0x400>;
1374                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1375                         clocks = <&r_ccu 6>;
1376                         clock-frequency = <3000000>;
1377                         resets = <&r_ccu 2>;
1378                         pinctrl-names = "default";
1379                         pinctrl-0 = <&r_rsb_pins>;
1380                         status = "disabled";
1381                         #address-cells = <1>;
1382                         #size-cells = <0>;
1383                 };
1384         };
1385 };