arch/arm/dts/sun50i-a64.dtsi

   1 /*
   2  * Copyright (C) 2016 ARM Ltd.
   3  * based on the Allwinner H3 dtsi:
   4  *    Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/pinctrl/sun4i-a10.h>
  47
  48 / {
  49         interrupt-parent = <&gic>;
  50         #address-cells = <1>;
  51         #size-cells = <1>;
  52
  53         cpus {
  54                 #address-cells = <1>;
  55                 #size-cells = <0>;
  56
  57                 cpu@0 {
  58                         compatible = "arm,cortex-a53", "arm,armv8";
  59                         device_type = "cpu";
  60                         reg = <0>;
  61                         enable-method = "psci";
  62                 };
  63
  64                 cpu@1 {
  65                         compatible = "arm,cortex-a53", "arm,armv8";
  66                         device_type = "cpu";
  67                         reg = <1>;
  68                         enable-method = "psci";
  69                 };
  70
  71                 cpu@2 {
  72                         compatible = "arm,cortex-a53", "arm,armv8";
  73                         device_type = "cpu";
  74                         reg = <2>;
  75                         enable-method = "psci";
  76                 };
  77
  78                 cpu@3 {
  79                         compatible = "arm,cortex-a53", "arm,armv8";
  80                         device_type = "cpu";
  81                         reg = <3>;
  82                         enable-method = "psci";
  83                 };
  84         };
  85
  86         psci {
  87                 compatible = "arm,psci-0.2";
  88                 method = "smc";
  89         };
  90
  91         memory {
  92                 device_type = "memory";
  93                 reg = <0x40000000 0>;
  94         };
  95
  96         gic: interrupt-controller@1c81000 {
  97                 compatible = "arm,gic-400";
  98                 interrupt-controller;
  99                 #interrupt-cells = <3>;
 100                 #address-cells = <0>;
 101
 102                 reg = <0x01c81000 0x1000>,
 103                       <0x01c82000 0x2000>,
 104                       <0x01c84000 0x2000>,
 105                       <0x01c86000 0x2000>;
 106                 interrupts = <GIC_PPI 9
 107                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 108         };
 109
 110         timer {
 111                 compatible = "arm,armv8-timer";
 112                 interrupts = <GIC_PPI 13
 113                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 114                              <GIC_PPI 14
 115                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 116                              <GIC_PPI 11
 117                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 118                              <GIC_PPI 10
 119                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 120         };
 121
 122         clocks {
 123                 #address-cells = <1>;
 124                 #size-cells = <1>;
 125                 ranges;
 126
 127                 osc24M: osc24M_clk {
 128                         #clock-cells = <0>;
 129                         compatible = "fixed-clock";
 130                         clock-frequency = <24000000>;
 131                         clock-output-names = "osc24M";
 132                 };
 133
 134                 osc32k: osc32k_clk {
 135                         #clock-cells = <0>;
 136                         compatible = "fixed-clock";
 137                         clock-frequency = <32768>;
 138                         clock-output-names = "osc32k";
 139                 };
 140
 141                 pll1: pll1_clk@1c20000 {
 142                         #clock-cells = <0>;
 143                         compatible = "allwinner,sun8i-a23-pll1-clk";
 144                         reg = <0x01c20000 0x4>;
 145                         clocks = <&osc24M>;
 146                         clock-output-names = "pll1";
 147                 };
 148
 149                 pll6: pll6_clk@1c20028 {
 150                         #clock-cells = <1>;
 151                         compatible = "allwinner,sun6i-a31-pll6-clk";
 152                         reg = <0x01c20028 0x4>;
 153                         clocks = <&osc24M>;
 154                         clock-output-names = "pll6", "pll6x2";
 155                 };
 156
 157                 pll6d2: pll6d2_clk {
 158                         #clock-cells = <0>;
 159                         compatible = "fixed-factor-clock";
 160                         clock-div = <2>;
 161                         clock-mult = <1>;
 162                         clocks = <&pll6 0>;
 163                         clock-output-names = "pll6d2";
 164                 };
 165
 166                 pll7: pll7_clk@1c2002c {
 167                         #clock-cells = <1>;
 168                         compatible = "allwinner,sun6i-a31-pll6-clk";
 169                         reg = <0x01c2002c 0x4>;
 170                         clocks = <&osc24M>;
 171                         clock-output-names = "pll7", "pll7x2";
 172                 };
 173
 174                 cpu: cpu_clk@1c20050 {
 175                         #clock-cells = <0>;
 176                         compatible = "allwinner,sun4i-a10-cpu-clk";
 177                         reg = <0x01c20050 0x4>;
 178                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
 179                         clock-output-names = "cpu";
 180                         critical-clocks = <0>;
 181                 };
 182
 183                 axi: axi_clk@1c20050 {
 184                         #clock-cells = <0>;
 185                         compatible = "allwinner,sun4i-a10-axi-clk";
 186                         reg = <0x01c20050 0x4>;
 187                         clocks = <&cpu>;
 188                         clock-output-names = "axi";
 189                 };
 190
 191                 ahb1: ahb1_clk@1c20054 {
 192                         #clock-cells = <0>;
 193                         compatible = "allwinner,sun6i-a31-ahb1-clk";
 194                         reg = <0x01c20054 0x4>;
 195                         clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
 196                         clock-output-names = "ahb1";
 197                 };
 198
 199                 ahb2: ahb2_clk@1c2005c {
 200                         #clock-cells = <0>;
 201                         compatible = "allwinner,sun8i-h3-ahb2-clk";
 202                         reg = <0x01c2005c 0x4>;
 203                         clocks = <&ahb1>, <&pll6d2>;
 204                         clock-output-names = "ahb2";
 205                 };
 206
 207                 apb1: apb1_clk@1c20054 {
 208                         #clock-cells = <0>;
 209                         compatible = "allwinner,sun4i-a10-apb0-clk";
 210                         reg = <0x01c20054 0x4>;
 211                         clocks = <&ahb1>;
 212                         clock-output-names = "apb1";
 213                 };
 214
 215                 apb2: apb2_clk@1c20058 {
 216                         #clock-cells = <0>;
 217                         compatible = "allwinner,sun4i-a10-apb1-clk";
 218                         reg = <0x01c20058 0x4>;
 219                         clocks = <&osc32k>, <&osc24M>, <&pll6 1>, <&pll6 1>;
 220                         clock-output-names = "apb2";
 221                 };
 222
 223                 bus_gates: bus_gates_clk@1c20060 {
 224                         #clock-cells = <1>;
 225                         compatible = "allwinner,sun50i-a64-bus-gates-clk",
 226                                      "allwinner,sunxi-multi-bus-gates-clk";
 227                         reg = <0x01c20060 0x14>;
 228                         ahb1_parent {
 229                                 clocks = <&ahb1>;
 230                                 clock-indices = <1>, <5>,
 231                                                 <6>, <8>,
 232                                                 <9>, <10>,
 233                                                 <13>, <14>,
 234                                                 <18>, <19>,
 235                                                 <20>, <21>,
 236                                                 <23>, <24>,
 237                                                 <25>, <28>,
 238                                                 <32>, <35>,
 239                                                 <36>, <37>,
 240                                                 <40>, <43>,
 241                                                 <44>, <52>,
 242                                                 <53>, <54>,
 243                                                 <135>;
 244                                 clock-output-names = "bus_mipidsi", "bus_ce",
 245                                                 "bus_dma", "bus_mmc0",
 246                                                 "bus_mmc1", "bus_mmc2",
 247                                                 "bus_nand", "bus_sdram",
 248                                                 "bus_ts", "bus_hstimer",
 249                                                 "bus_spi0", "bus_spi1",
 250                                                 "bus_otg", "bus_otg_ehci0",
 251                                                 "bus_ehci0", "bus_otg_ohci0",
 252                                                 "bus_ve", "bus_lcd0",
 253                                                 "bus_lcd1", "bus_deint",
 254                                                 "bus_csi", "bus_hdmi",
 255                                                 "bus_de", "bus_gpu",
 256                                                 "bus_msgbox", "bus_spinlock",
 257                                                 "bus_dbg";
 258                         };
 259                         ahb2_parent {
 260                                 clocks = <&ahb2>;
 261                                 clock-indices = <17>, <29>;
 262                                 clock-output-names = "bus_gmac", "bus_ohci0";
 263                         };
 264                         apb1_parent {
 265                                 clocks = <&apb1>;
 266                                 clock-indices = <64>, <65>,
 267                                                 <69>, <72>,
 268                                                 <76>, <77>,
 269                                                 <78>;
 270                                 clock-output-names = "bus_codec", "bus_spdif",
 271                                                 "bus_pio", "bus_ths",
 272                                                 "bus_i2s0", "bus_i2s1",
 273                                                 "bus_i2s2";
 274                         };
 275                         abp2_parent {
 276                                 clocks = <&apb2>;
 277                                 clock-indices = <96>, <97>,
 278                                                 <98>, <101>,
 279                                                 <112>, <113>,
 280                                                 <114>, <115>,
 281                                                 <116>;
 282                                 clock-output-names = "bus_i2c0", "bus_i2c1",
 283                                                 "bus_i2c2", "bus_scr",
 284                                                 "bus_uart0", "bus_uart1",
 285                                                 "bus_uart2", "bus_uart3",
 286                                                 "bus_uart4";
 287                         };
 288                 };
 289
 290                 mmc0_clk: mmc0_clk@1c20088 {
 291                         #clock-cells = <0>;
 292                         compatible = "allwinner,sun4i-a10-mod0-clk";
 293                         reg = <0x01c20088 0x4>;
 294                         clocks = <&osc24M>, <&pll6 1>, <&pll7 1>;
 295                         clock-output-names = "mmc0";
 296                 };
 297
 298                 mmc1_clk: mmc1_clk@1c2008c {
 299                         #clock-cells = <0>;
 300                         compatible = "allwinner,sun4i-a10-mod0-clk";
 301                         reg = <0x01c2008c 0x4>;
 302                         clocks = <&osc24M>, <&pll6 1>, <&pll7 1>;
 303                         clock-output-names = "mmc1";
 304                 };
 305
 306                 mmc2_clk: mmc2_clk@1c20090 {
 307                         #clock-cells = <0>;
 308                         compatible = "allwinner,sun4i-a10-mod0-clk";
 309                         reg = <0x01c20090 0x4>;
 310                         clocks = <&osc24M>, <&pll6 1>, <&pll7 1>;
 311                         clock-output-names = "mmc2";
 312                 };
 313         };
 314
 315         soc {
 316                 compatible = "simple-bus";
 317                 #address-cells = <1>;
 318                 #size-cells = <1>;
 319                 ranges;
 320
 321                 mmc0: mmc@1c0f000 {
 322                         compatible = "allwinner,sun50i-a64-mmc",
 323                                      "allwinner,sun5i-a13-mmc";
 324                         reg = <0x01c0f000 0x1000>;
 325                         clocks = <&bus_gates 8>, <&mmc0_clk>,
 326                                  <&mmc0_clk>, <&mmc0_clk>;
 327                         clock-names = "ahb", "mmc",
 328                                       "output", "sample";
 329                         resets = <&ahb_rst 8>;
 330                         reset-names = "ahb";
 331                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 332                         status = "disabled";
 333                         #address-cells = <1>;
 334                         #size-cells = <0>;
 335                 };
 336
 337                 mmc1: mmc@1c10000 {
 338                         compatible = "allwinner,sun50i-a64-mmc",
 339                                      "allwinner,sun5i-a13-mmc";
 340                         reg = <0x01c10000 0x1000>;
 341                         clocks = <&bus_gates 9>, <&mmc1_clk>,
 342                                  <&mmc1_clk>, <&mmc1_clk>;
 343                         clock-names = "ahb", "mmc",
 344                                       "output", "sample";
 345                         resets = <&ahb_rst 9>;
 346                         reset-names = "ahb";
 347                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 348                         status = "disabled";
 349                         #address-cells = <1>;
 350                         #size-cells = <0>;
 351                 };
 352
 353                 mmc2: mmc@1c11000 {
 354                         compatible = "allwinner,sun50i-a64-mmc",
 355                                      "allwinner,sun5i-a13-mmc";
 356                         reg = <0x01c11000 0x1000>;
 357                         clocks = <&bus_gates 10>, <&mmc2_clk>,
 358                                  <&mmc2_clk>, <&mmc2_clk>;
 359                         clock-names = "ahb", "mmc",
 360                                       "output", "sample";
 361                         resets = <&ahb_rst 10>;
 362                         reset-names = "ahb";
 363                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 364                         status = "disabled";
 365                         #address-cells = <1>;
 366                         #size-cells = <0>;
 367                 };
 368
 369                 pio: pinctrl@1c20800 {
 370                         compatible = "allwinner,sun50i-a64-pinctrl";
 371                         reg = <0x01c20800 0x400>;
 372                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 373                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 374                                      <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 375                         clocks = <&bus_gates 69>;
 376                         gpio-controller;
 377                         #gpio-cells = <3>;
 378                         interrupt-controller;
 379                         #interrupt-cells = <2>;
 380
 381                         uart0_pins_a: uart0@0 {
 382                                 allwinner,pins = "PB8", "PB9";
 383                                 allwinner,function = "uart0";
 384                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 385                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 386                         };
 387
 388                         uart0_pins_b: uart0@1 {
 389                                 allwinner,pins = "PF2", "PF3";
 390                                 allwinner,function = "uart0";
 391                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 392                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 393                         };
 394
 395                         uart1_2pins: uart1_2@0 {
 396                                 allwinner,pins = "PG6", "PG7";
 397                                 allwinner,function = "uart1";
 398                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 399                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 400                         };
 401
 402                         uart1_4pins: uart1_4@0 {
 403                                 allwinner,pins = "PG6", "PG7", "PG8", "PG9";
 404                                 allwinner,function = "uart1";
 405                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 406                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 407                         };
 408
 409                         uart2_2pins: uart2_2@0 {
 410                                 allwinner,pins = "PB0", "PB1";
 411                                 allwinner,function = "uart2";
 412                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 413                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 414                         };
 415
 416                         uart2_4pins: uart2_4@0 {
 417                                 allwinner,pins = "PB0", "PB1", "PB2", "PB3";
 418                                 allwinner,function = "uart2";
 419                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 420                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 421                         };
 422
 423                         uart3_pins_a: uart3@0 {
 424                                 allwinner,pins = "PD0", "PD1";
 425                                 allwinner,function = "uart3";
 426                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 427                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 428                         };
 429
 430                         uart3_2pins_b: uart3_2@1 {
 431                                 allwinner,pins = "PH4", "PH5";
 432                                 allwinner,function = "uart3";
 433                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 434                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 435                         };
 436
 437                         uart3_4pins_b: uart3_4@1 {
 438                                 allwinner,pins = "PH4", "PH5", "PH6", "PH7";
 439                                 allwinner,function = "uart3";
 440                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 441                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 442                         };
 443
 444                         uart4_2pins: uart4_2@0 {
 445                                 allwinner,pins = "PD2", "PD3";
 446                                 allwinner,function = "uart4";
 447                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 448                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 449                         };
 450
 451                         uart4_4pins: uart4_4@0 {
 452                                 allwinner,pins = "PD2", "PD3", "PD4", "PD5";
 453                                 allwinner,function = "uart4";
 454                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 455                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 456                         };
 457
 458                         mmc0_pins: mmc0@0 {
 459                                 allwinner,pins = "PF0", "PF1", "PF2", "PF3",
 460                                                  "PF4", "PF5";
 461                                 allwinner,function = "mmc0";
 462                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 463                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 464                         };
 465
 466                         mmc0_default_cd_pin: mmc0_cd_pin@0 {
 467                                 allwinner,pins = "PF6";
 468                                 allwinner,function = "gpio_in";
 469                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 470                                 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
 471                         };
 472
 473                         mmc1_pins: mmc1@0 {
 474                                 allwinner,pins = "PG0", "PG1", "PG2", "PG3",
 475                                                  "PG4", "PG5";
 476                                 allwinner,function = "mmc1";
 477                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 478                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 479                         };
 480
 481                         mmc2_pins: mmc2@0 {
 482                                 allwinner,pins = "PC1", "PC5", "PC6", "PC8",
 483                                                  "PC9", "PC10";
 484                                 allwinner,function = "mmc2";
 485                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 486                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 487                         };
 488
 489                         i2c0_pins: i2c0_pins {
 490                                 allwinner,pins = "PH0", "PH1";
 491                                 allwinner,function = "i2c0";
 492                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 493                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 494                         };
 495
 496                         i2c1_pins: i2c1_pins {
 497                                 allwinner,pins = "PH2", "PH3";
 498                                 allwinner,function = "i2c1";
 499                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 500                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 501                         };
 502
 503                         i2c2_pins: i2c2_pins {
 504                                 allwinner,pins = "PE14", "PE15";
 505                                 allwinner,function = "i2c2";
 506                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 507                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 508                         };
 509                 };
 510
 511                 ahb_rst: reset@1c202c0 {
 512                         #reset-cells = <1>;
 513                         compatible = "allwinner,sun6i-a31-clock-reset";
 514                         reg = <0x01c202c0 0xc>;
 515                 };
 516
 517                 apb1_rst: reset@1c202d0 {
 518                         #reset-cells = <1>;
 519                         compatible = "allwinner,sun6i-a31-clock-reset";
 520                         reg = <0x01c202d0 0x4>;
 521                 };
 522
 523                 apb2_rst: reset@1c202d8 {
 524                         #reset-cells = <1>;
 525                         compatible = "allwinner,sun6i-a31-clock-reset";
 526                         reg = <0x01c202d8 0x4>;
 527                 };
 528
 529                 uart0: serial@1c28000 {
 530                         compatible = "snps,dw-apb-uart";
 531                         reg = <0x01c28000 0x400>;
 532                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 533                         reg-shift = <2>;
 534                         reg-io-width = <4>;
 535                         clocks = <&bus_gates 112>;
 536                         resets = <&apb2_rst 16>;
 537                         status = "disabled";
 538                 };
 539
 540                 uart1: serial@1c28400 {
 541                         compatible = "snps,dw-apb-uart";
 542                         reg = <0x01c28400 0x400>;
 543                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 544                         reg-shift = <2>;
 545                         reg-io-width = <4>;
 546                         clocks = <&bus_gates 113>;
 547                         resets = <&apb2_rst 17>;
 548                         status = "disabled";
 549                 };
 550
 551                 uart2: serial@1c28800 {
 552                         compatible = "snps,dw-apb-uart";
 553                         reg = <0x01c28800 0x400>;
 554                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 555                         reg-shift = <2>;
 556                         reg-io-width = <4>;
 557                         clocks = <&bus_gates 114>;
 558                         resets = <&apb2_rst 18>;
 559                         status = "disabled";
 560                 };
 561
 562                 uart3: serial@1c28c00 {
 563                         compatible = "snps,dw-apb-uart";
 564                         reg = <0x01c28c00 0x400>;
 565                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 566                         reg-shift = <2>;
 567                         reg-io-width = <4>;
 568                         clocks = <&bus_gates 115>;
 569                         resets = <&apb2_rst 19>;
 570                         status = "disabled";
 571                 };
 572
 573                 uart4: serial@1c29000 {
 574                         compatible = "snps,dw-apb-uart";
 575                         reg = <0x01c29000 0x400>;
 576                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 577                         reg-shift = <2>;
 578                         reg-io-width = <4>;
 579                         clocks = <&bus_gates 116>;
 580                         resets = <&apb2_rst 20>;
 581                         status = "disabled";
 582                 };
 583
 584                 rtc: rtc@1f00000 {
 585                         compatible = "allwinner,sun6i-a31-rtc";
 586                         reg = <0x01f00000 0x54>;
 587                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 588                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 589                 };
 590
 591                 i2c0: i2c@1c2ac00 {
 592                         compatible = "allwinner,sun6i-a31-i2c";
 593                         reg = <0x01c2ac00 0x400>;
 594                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 595                         clocks = <&bus_gates 96>;
 596                         resets = <&apb2_rst 0>;
 597                         status = "disabled";
 598                         #address-cells = <1>;
 599                         #size-cells = <0>;
 600                 };
 601
 602                 i2c1: i2c@1c2b000 {
 603                         compatible = "allwinner,sun6i-a31-i2c";
 604                         reg = <0x01c2b000 0x400>;
 605                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 606                         clocks = <&bus_gates 97>;
 607                         resets = <&apb2_rst 1>;
 608                         status = "disabled";
 609                         #address-cells = <1>;
 610                         #size-cells = <0>;
 611                 };
 612
 613                 i2c2: i2c@1c2b400 {
 614                         compatible = "allwinner,sun6i-a31-i2c";
 615                         reg = <0x01c2b400 0x400>;
 616                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 617                         clocks = <&bus_gates 98>;
 618                         resets = <&apb2_rst 2>;
 619                         status = "disabled";
 620                         #address-cells = <1>;
 621                         #size-cells = <0>;
 622                 };
 623         };
 624 };