2 * Copyright (C) 2016 ARM Ltd.
3 * based on the Allwinner H3 dtsi:
4 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
45 #include <dt-bindings/clock/sun50i-a64-ccu.h>
46 #include <dt-bindings/clock/sun8i-de2.h>
47 #include <dt-bindings/clock/sun8i-r-ccu.h>
48 #include <dt-bindings/interrupt-controller/arm-gic.h>
49 #include <dt-bindings/reset/sun50i-a64-ccu.h>
50 #include <dt-bindings/reset/sun8i-de2.h>
51 #include <dt-bindings/reset/sun8i-r-ccu.h>
54 interrupt-parent = <&gic>;
63 simplefb_lcd: framebuffer-lcd {
64 compatible = "allwinner,simple-framebuffer",
66 allwinner,pipeline = "mixer0-lcd0";
67 clocks = <&ccu CLK_TCON0>,
68 <&display_clocks CLK_MIXER0>;
72 simplefb_hdmi: framebuffer-hdmi {
73 compatible = "allwinner,simple-framebuffer",
75 allwinner,pipeline = "mixer1-lcd1-hdmi";
76 clocks = <&display_clocks CLK_MIXER1>,
77 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>;
87 compatible = "arm,cortex-a53", "arm,armv8";
90 enable-method = "psci";
91 next-level-cache = <&L2>;
95 compatible = "arm,cortex-a53", "arm,armv8";
98 enable-method = "psci";
99 next-level-cache = <&L2>;
103 compatible = "arm,cortex-a53", "arm,armv8";
106 enable-method = "psci";
107 next-level-cache = <&L2>;
111 compatible = "arm,cortex-a53", "arm,armv8";
114 enable-method = "psci";
115 next-level-cache = <&L2>;
119 compatible = "cache";
125 compatible = "allwinner,sun50i-a64-display-engine";
126 allwinner,pipelines = <&mixer0>,
133 compatible = "fixed-clock";
134 clock-frequency = <24000000>;
135 clock-output-names = "osc24M";
140 compatible = "fixed-clock";
141 clock-frequency = <32768>;
142 clock-output-names = "osc32k";
145 iosc: internal-osc-clk {
147 compatible = "fixed-clock";
148 clock-frequency = <16000000>;
149 clock-accuracy = <300000000>;
150 clock-output-names = "iosc";
154 compatible = "arm,psci-0.2";
159 compatible = "simple-audio-card";
160 simple-audio-card,name = "On-board SPDIF";
162 simple-audio-card,cpu {
163 sound-dai = <&spdif>;
166 simple-audio-card,codec {
167 sound-dai = <&spdif_out>;
171 spdif_out: spdif-out {
172 #sound-dai-cells = <0>;
173 compatible = "linux,spdif-dit";
177 compatible = "arm,armv8-timer";
178 interrupts = <GIC_PPI 13
179 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
181 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
183 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
185 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
189 compatible = "simple-bus";
190 #address-cells = <1>;
195 compatible = "allwinner,sun50i-a64-de2";
196 reg = <0x1000000 0x400000>;
197 allwinner,sram = <&de2_sram 1>;
198 #address-cells = <1>;
200 ranges = <0 0x1000000 0x400000>;
202 display_clocks: clock@0 {
203 compatible = "allwinner,sun50i-a64-de2-clk";
204 reg = <0x0 0x100000>;
205 clocks = <&ccu CLK_DE>,
209 resets = <&ccu RST_BUS_DE>;
214 mixer0: mixer@100000 {
215 compatible = "allwinner,sun50i-a64-de2-mixer-0";
216 reg = <0x100000 0x100000>;
217 clocks = <&display_clocks CLK_BUS_MIXER0>,
218 <&display_clocks CLK_MIXER0>;
221 resets = <&display_clocks RST_MIXER0>;
224 #address-cells = <1>;
230 mixer0_out_tcon0: endpoint {
231 remote-endpoint = <&tcon0_in_mixer0>;
237 mixer1: mixer@200000 {
238 compatible = "allwinner,sun50i-a64-de2-mixer-1";
239 reg = <0x200000 0x100000>;
240 clocks = <&display_clocks CLK_BUS_MIXER1>,
241 <&display_clocks CLK_MIXER1>;
244 resets = <&display_clocks RST_MIXER1>;
247 #address-cells = <1>;
253 mixer1_out_tcon1: endpoint {
254 remote-endpoint = <&tcon1_in_mixer1>;
261 syscon: syscon@1c00000 {
262 compatible = "allwinner,sun50i-a64-system-control",
264 reg = <0x01c00000 0x1000>;
265 #address-cells = <1>;
270 compatible = "mmio-sram";
271 reg = <0x00018000 0x28000>;
272 #address-cells = <1>;
274 ranges = <0 0x00018000 0x28000>;
276 de2_sram: sram-section@0 {
277 compatible = "allwinner,sun50i-a64-sram-c";
278 reg = <0x0000 0x28000>;
283 dma: dma-controller@1c02000 {
284 compatible = "allwinner,sun50i-a64-dma";
285 reg = <0x01c02000 0x1000>;
286 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
287 clocks = <&ccu CLK_BUS_DMA>;
290 resets = <&ccu RST_BUS_DMA>;
294 tcon0: lcd-controller@1c0c000 {
295 compatible = "allwinner,sun50i-a64-tcon-lcd",
296 "allwinner,sun8i-a83t-tcon-lcd";
297 reg = <0x01c0c000 0x1000>;
298 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
299 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
300 clock-names = "ahb", "tcon-ch0";
301 clock-output-names = "tcon-pixel-clock";
302 resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
303 reset-names = "lcd", "lvds";
306 #address-cells = <1>;
310 #address-cells = <1>;
314 tcon0_in_mixer0: endpoint@0 {
316 remote-endpoint = <&mixer0_out_tcon0>;
321 #address-cells = <1>;
328 tcon1: lcd-controller@1c0d000 {
329 compatible = "allwinner,sun50i-a64-tcon-tv",
330 "allwinner,sun8i-a83t-tcon-tv";
331 reg = <0x01c0d000 0x1000>;
332 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
333 clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
334 clock-names = "ahb", "tcon-ch1";
335 resets = <&ccu RST_BUS_TCON1>;
339 #address-cells = <1>;
345 tcon1_in_mixer1: endpoint {
346 remote-endpoint = <&mixer1_out_tcon1>;
351 #address-cells = <1>;
355 tcon1_out_hdmi: endpoint@1 {
357 remote-endpoint = <&hdmi_in_tcon1>;
364 compatible = "allwinner,sun50i-a64-mmc";
365 reg = <0x01c0f000 0x1000>;
366 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
367 clock-names = "ahb", "mmc";
368 resets = <&ccu RST_BUS_MMC0>;
370 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
371 max-frequency = <150000000>;
373 #address-cells = <1>;
378 compatible = "allwinner,sun50i-a64-mmc";
379 reg = <0x01c10000 0x1000>;
380 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
381 clock-names = "ahb", "mmc";
382 resets = <&ccu RST_BUS_MMC1>;
384 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
385 max-frequency = <150000000>;
387 #address-cells = <1>;
392 compatible = "allwinner,sun50i-a64-emmc";
393 reg = <0x01c11000 0x1000>;
394 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
395 clock-names = "ahb", "mmc";
396 resets = <&ccu RST_BUS_MMC2>;
398 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
399 max-frequency = <200000000>;
401 #address-cells = <1>;
405 sid: eeprom@1c14000 {
406 compatible = "allwinner,sun50i-a64-sid";
407 reg = <0x1c14000 0x400>;
410 usb_otg: usb@1c19000 {
411 compatible = "allwinner,sun8i-a33-musb";
412 reg = <0x01c19000 0x0400>;
413 clocks = <&ccu CLK_BUS_OTG>;
414 resets = <&ccu RST_BUS_OTG>;
415 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
416 interrupt-names = "mc";
419 extcon = <&usbphy 0>;
423 usbphy: phy@1c19400 {
424 compatible = "allwinner,sun50i-a64-usb-phy";
425 reg = <0x01c19400 0x14>,
428 reg-names = "phy_ctrl",
431 clocks = <&ccu CLK_USB_PHY0>,
433 clock-names = "usb0_phy",
435 resets = <&ccu RST_USB_PHY0>,
437 reset-names = "usb0_reset",
444 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
445 reg = <0x01c1a000 0x100>;
446 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
447 clocks = <&ccu CLK_BUS_OHCI0>,
448 <&ccu CLK_BUS_EHCI0>,
449 <&ccu CLK_USB_OHCI0>;
450 resets = <&ccu RST_BUS_OHCI0>,
451 <&ccu RST_BUS_EHCI0>;
456 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
457 reg = <0x01c1a400 0x100>;
458 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
459 clocks = <&ccu CLK_BUS_OHCI0>,
460 <&ccu CLK_USB_OHCI0>;
461 resets = <&ccu RST_BUS_OHCI0>;
466 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
467 reg = <0x01c1b000 0x100>;
468 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
469 clocks = <&ccu CLK_BUS_OHCI1>,
470 <&ccu CLK_BUS_EHCI1>,
471 <&ccu CLK_USB_OHCI1>;
472 resets = <&ccu RST_BUS_OHCI1>,
473 <&ccu RST_BUS_EHCI1>;
480 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
481 reg = <0x01c1b400 0x100>;
482 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
483 clocks = <&ccu CLK_BUS_OHCI1>,
484 <&ccu CLK_USB_OHCI1>;
485 resets = <&ccu RST_BUS_OHCI1>;
492 compatible = "allwinner,sun50i-a64-ccu";
493 reg = <0x01c20000 0x400>;
494 clocks = <&osc24M>, <&osc32k>;
495 clock-names = "hosc", "losc";
500 pio: pinctrl@1c20800 {
501 compatible = "allwinner,sun50i-a64-pinctrl";
502 reg = <0x01c20800 0x400>;
503 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
504 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
505 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
509 interrupt-controller;
510 #interrupt-cells = <3>;
512 i2c0_pins: i2c0_pins {
517 i2c1_pins: i2c1_pins {
522 mmc0_pins: mmc0-pins {
523 pins = "PF0", "PF1", "PF2", "PF3",
526 drive-strength = <30>;
530 mmc1_pins: mmc1-pins {
531 pins = "PG0", "PG1", "PG2", "PG3",
534 drive-strength = <30>;
538 mmc2_pins: mmc2-pins {
539 pins = "PC5", "PC6", "PC8", "PC9",
540 "PC10","PC11", "PC12", "PC13",
541 "PC14", "PC15", "PC16";
543 drive-strength = <30>;
547 mmc2_ds_pin: mmc2-ds-pin {
550 drive-strength = <30>;
559 rmii_pins: rmii_pins {
560 pins = "PD10", "PD11", "PD13", "PD14", "PD17",
561 "PD18", "PD19", "PD20", "PD22", "PD23";
563 drive-strength = <40>;
566 rgmii_pins: rgmii_pins {
567 pins = "PD8", "PD9", "PD10", "PD11", "PD12",
568 "PD13", "PD15", "PD16", "PD17", "PD18",
569 "PD19", "PD20", "PD21", "PD22", "PD23";
571 drive-strength = <40>;
574 spdif_tx_pin: spdif {
580 pins = "PC0", "PC1", "PC2", "PC3";
585 pins = "PD0", "PD1", "PD2", "PD3";
589 uart0_pb_pins: uart0-pb-pins {
594 uart1_pins: uart1_pins {
599 uart1_rts_cts_pins: uart1_rts_cts_pins {
604 uart2_pins: uart2-pins {
609 uart3_pins: uart3-pins {
614 uart4_pins: uart4-pins {
619 uart4_rts_cts_pins: uart4-rts-cts-pins {
625 spdif: spdif@1c21000 {
626 #sound-dai-cells = <0>;
627 compatible = "allwinner,sun50i-a64-spdif",
628 "allwinner,sun8i-h3-spdif";
629 reg = <0x01c21000 0x400>;
630 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
631 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
632 resets = <&ccu RST_BUS_SPDIF>;
633 clock-names = "apb", "spdif";
636 pinctrl-names = "default";
637 pinctrl-0 = <&spdif_tx_pin>;
642 #sound-dai-cells = <0>;
643 compatible = "allwinner,sun50i-a64-i2s",
644 "allwinner,sun8i-h3-i2s";
645 reg = <0x01c22000 0x400>;
646 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
647 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
648 clock-names = "apb", "mod";
649 resets = <&ccu RST_BUS_I2S0>;
650 dma-names = "rx", "tx";
651 dmas = <&dma 3>, <&dma 3>;
656 #sound-dai-cells = <0>;
657 compatible = "allwinner,sun50i-a64-i2s",
658 "allwinner,sun8i-h3-i2s";
659 reg = <0x01c22400 0x400>;
660 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
661 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
662 clock-names = "apb", "mod";
663 resets = <&ccu RST_BUS_I2S1>;
664 dma-names = "rx", "tx";
665 dmas = <&dma 4>, <&dma 4>;
669 uart0: serial@1c28000 {
670 compatible = "snps,dw-apb-uart";
671 reg = <0x01c28000 0x400>;
672 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
675 clocks = <&ccu CLK_BUS_UART0>;
676 resets = <&ccu RST_BUS_UART0>;
680 uart1: serial@1c28400 {
681 compatible = "snps,dw-apb-uart";
682 reg = <0x01c28400 0x400>;
683 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
686 clocks = <&ccu CLK_BUS_UART1>;
687 resets = <&ccu RST_BUS_UART1>;
691 uart2: serial@1c28800 {
692 compatible = "snps,dw-apb-uart";
693 reg = <0x01c28800 0x400>;
694 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
697 clocks = <&ccu CLK_BUS_UART2>;
698 resets = <&ccu RST_BUS_UART2>;
702 uart3: serial@1c28c00 {
703 compatible = "snps,dw-apb-uart";
704 reg = <0x01c28c00 0x400>;
705 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
708 clocks = <&ccu CLK_BUS_UART3>;
709 resets = <&ccu RST_BUS_UART3>;
713 uart4: serial@1c29000 {
714 compatible = "snps,dw-apb-uart";
715 reg = <0x01c29000 0x400>;
716 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
719 clocks = <&ccu CLK_BUS_UART4>;
720 resets = <&ccu RST_BUS_UART4>;
725 compatible = "allwinner,sun6i-a31-i2c";
726 reg = <0x01c2ac00 0x400>;
727 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
728 clocks = <&ccu CLK_BUS_I2C0>;
729 resets = <&ccu RST_BUS_I2C0>;
731 #address-cells = <1>;
736 compatible = "allwinner,sun6i-a31-i2c";
737 reg = <0x01c2b000 0x400>;
738 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
739 clocks = <&ccu CLK_BUS_I2C1>;
740 resets = <&ccu RST_BUS_I2C1>;
742 #address-cells = <1>;
747 compatible = "allwinner,sun6i-a31-i2c";
748 reg = <0x01c2b400 0x400>;
749 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
750 clocks = <&ccu CLK_BUS_I2C2>;
751 resets = <&ccu RST_BUS_I2C2>;
753 #address-cells = <1>;
759 compatible = "allwinner,sun8i-h3-spi";
760 reg = <0x01c68000 0x1000>;
761 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
762 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
763 clock-names = "ahb", "mod";
764 dmas = <&dma 23>, <&dma 23>;
765 dma-names = "rx", "tx";
766 pinctrl-names = "default";
767 pinctrl-0 = <&spi0_pins>;
768 resets = <&ccu RST_BUS_SPI0>;
771 #address-cells = <1>;
776 compatible = "allwinner,sun8i-h3-spi";
777 reg = <0x01c69000 0x1000>;
778 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
779 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
780 clock-names = "ahb", "mod";
781 dmas = <&dma 24>, <&dma 24>;
782 dma-names = "rx", "tx";
783 pinctrl-names = "default";
784 pinctrl-0 = <&spi1_pins>;
785 resets = <&ccu RST_BUS_SPI1>;
788 #address-cells = <1>;
792 emac: ethernet@1c30000 {
793 compatible = "allwinner,sun50i-a64-emac";
795 reg = <0x01c30000 0x10000>;
796 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
797 interrupt-names = "macirq";
798 resets = <&ccu RST_BUS_EMAC>;
799 reset-names = "stmmaceth";
800 clocks = <&ccu CLK_BUS_EMAC>;
801 clock-names = "stmmaceth";
805 compatible = "snps,dwmac-mdio";
806 #address-cells = <1>;
811 gic: interrupt-controller@1c81000 {
812 compatible = "arm,gic-400";
813 reg = <0x01c81000 0x1000>,
817 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
818 interrupt-controller;
819 #interrupt-cells = <3>;
823 compatible = "allwinner,sun50i-a64-pwm",
824 "allwinner,sun5i-a13-pwm";
825 reg = <0x01c21400 0x400>;
827 pinctrl-names = "default";
828 pinctrl-0 = <&pwm_pin>;
834 compatible = "allwinner,sun50i-a64-dw-hdmi",
835 "allwinner,sun8i-a83t-dw-hdmi";
836 reg = <0x01ee0000 0x10000>;
838 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
839 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
841 clock-names = "iahb", "isfr", "tmds";
842 resets = <&ccu RST_BUS_HDMI1>;
843 reset-names = "ctrl";
845 phy-names = "hdmi-phy";
849 #address-cells = <1>;
855 hdmi_in_tcon1: endpoint {
856 remote-endpoint = <&tcon1_out_hdmi>;
866 hdmi_phy: hdmi-phy@1ef0000 {
867 compatible = "allwinner,sun50i-a64-hdmi-phy";
868 reg = <0x01ef0000 0x10000>;
869 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
871 clock-names = "bus", "mod", "pll-0";
872 resets = <&ccu RST_BUS_HDMI0>;
878 compatible = "allwinner,sun6i-a31-rtc";
879 reg = <0x01f00000 0x54>;
880 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
881 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
882 clock-output-names = "rtc-osc32k", "rtc-osc32k-out";
887 r_intc: interrupt-controller@1f00c00 {
888 compatible = "allwinner,sun50i-a64-r-intc",
889 "allwinner,sun6i-a31-r-intc";
890 interrupt-controller;
891 #interrupt-cells = <2>;
892 reg = <0x01f00c00 0x400>;
893 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
896 r_ccu: clock@1f01400 {
897 compatible = "allwinner,sun50i-a64-r-ccu";
898 reg = <0x01f01400 0x100>;
899 clocks = <&osc24M>, <&osc32k>, <&iosc>,
901 clock-names = "hosc", "losc", "iosc", "pll-periph";
907 compatible = "allwinner,sun50i-a64-i2c",
908 "allwinner,sun6i-a31-i2c";
909 reg = <0x01f02400 0x400>;
910 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
911 clocks = <&r_ccu CLK_APB0_I2C>;
912 resets = <&r_ccu RST_APB0_I2C>;
914 #address-cells = <1>;
919 compatible = "allwinner,sun50i-a64-pwm",
920 "allwinner,sun5i-a13-pwm";
921 reg = <0x01f03800 0x400>;
923 pinctrl-names = "default";
924 pinctrl-0 = <&r_pwm_pin>;
929 r_pio: pinctrl@1f02c00 {
930 compatible = "allwinner,sun50i-a64-r-pinctrl";
931 reg = <0x01f02c00 0x400>;
932 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
933 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
934 clock-names = "apb", "hosc", "losc";
937 interrupt-controller;
938 #interrupt-cells = <3>;
940 r_i2c_pl89_pins: r-i2c-pl89-pins {
957 compatible = "allwinner,sun8i-a23-rsb";
958 reg = <0x01f03400 0x400>;
959 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
961 clock-frequency = <3000000>;
963 pinctrl-names = "default";
964 pinctrl-0 = <&r_rsb_pins>;
966 #address-cells = <1>;
970 wdt0: watchdog@1c20ca0 {
971 compatible = "allwinner,sun50i-a64-wdt",
972 "allwinner,sun6i-a31-wdt";
973 reg = <0x01c20ca0 0x20>;
974 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;