1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 // Copyright (C) 2016 ARM Ltd.
3 // based on the Allwinner H3 dtsi:
4 // Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
6 #include <dt-bindings/clock/sun50i-a64-ccu.h>
7 #include <dt-bindings/clock/sun8i-de2.h>
8 #include <dt-bindings/clock/sun8i-r-ccu.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/reset/sun50i-a64-ccu.h>
11 #include <dt-bindings/reset/sun8i-de2.h>
12 #include <dt-bindings/reset/sun8i-r-ccu.h>
13 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
25 simplefb_lcd: framebuffer-lcd {
26 compatible = "allwinner,simple-framebuffer",
28 allwinner,pipeline = "mixer0-lcd0";
29 clocks = <&ccu CLK_TCON0>,
30 <&display_clocks CLK_MIXER0>;
34 simplefb_hdmi: framebuffer-hdmi {
35 compatible = "allwinner,simple-framebuffer",
37 allwinner,pipeline = "mixer1-lcd1-hdmi";
38 clocks = <&display_clocks CLK_MIXER1>,
39 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>;
49 compatible = "arm,cortex-a53";
52 enable-method = "psci";
53 next-level-cache = <&L2>;
60 compatible = "arm,cortex-a53";
63 enable-method = "psci";
64 next-level-cache = <&L2>;
71 compatible = "arm,cortex-a53";
74 enable-method = "psci";
75 next-level-cache = <&L2>;
82 compatible = "arm,cortex-a53";
85 enable-method = "psci";
86 next-level-cache = <&L2>;
99 compatible = "allwinner,sun50i-a64-display-engine";
100 allwinner,pipelines = <&mixer0>,
107 compatible = "fixed-clock";
108 clock-frequency = <24000000>;
109 clock-output-names = "osc24M";
114 compatible = "fixed-clock";
115 clock-frequency = <32768>;
116 clock-output-names = "ext-osc32k";
120 compatible = "arm,cortex-a53-pmu";
121 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
122 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
123 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
124 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
125 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
129 compatible = "arm,psci-0.2";
134 compatible = "simple-audio-card";
135 simple-audio-card,name = "sun50i-a64-audio";
136 simple-audio-card,format = "i2s";
137 simple-audio-card,frame-master = <&cpudai>;
138 simple-audio-card,bitclock-master = <&cpudai>;
139 simple-audio-card,mclk-fs = <128>;
140 simple-audio-card,aux-devs = <&codec_analog>;
141 simple-audio-card,routing =
142 "Left DAC", "AIF1 Slot 0 Left",
143 "Right DAC", "AIF1 Slot 0 Right",
144 "AIF1 Slot 0 Left ADC", "Left ADC",
145 "AIF1 Slot 0 Right ADC", "Right ADC";
148 cpudai: simple-audio-card,cpu {
152 link_codec: simple-audio-card,codec {
153 sound-dai = <&codec>;
158 compatible = "arm,armv8-timer";
159 allwinner,erratum-unknown1;
160 interrupts = <GIC_PPI 13
161 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
163 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
165 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
167 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
171 cpu_thermal: cpu0-thermal {
173 polling-delay-passive = <0>;
175 thermal-sensors = <&ths 0>;
179 trip = <&cpu_alert0>;
180 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
181 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
182 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
183 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
186 trip = <&cpu_alert1>;
187 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
188 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
189 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
190 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
195 cpu_alert0: cpu_alert0 {
197 temperature = <75000>;
202 cpu_alert1: cpu_alert1 {
204 temperature = <90000>;
211 temperature = <110000>;
218 gpu0_thermal: gpu0-thermal {
220 polling-delay-passive = <0>;
222 thermal-sensors = <&ths 1>;
225 gpu1_thermal: gpu1-thermal {
227 polling-delay-passive = <0>;
229 thermal-sensors = <&ths 2>;
234 compatible = "simple-bus";
235 #address-cells = <1>;
240 compatible = "allwinner,sun50i-a64-de2";
241 reg = <0x1000000 0x400000>;
242 allwinner,sram = <&de2_sram 1>;
243 #address-cells = <1>;
245 ranges = <0 0x1000000 0x400000>;
247 display_clocks: clock@0 {
248 compatible = "allwinner,sun50i-a64-de2-clk";
250 clocks = <&ccu CLK_BUS_DE>,
254 resets = <&ccu RST_BUS_DE>;
259 rotate: rotate@20000 {
260 compatible = "allwinner,sun50i-a64-de2-rotate",
261 "allwinner,sun8i-a83t-de2-rotate";
262 reg = <0x20000 0x10000>;
263 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
264 clocks = <&display_clocks CLK_BUS_ROT>,
265 <&display_clocks CLK_ROT>;
268 resets = <&display_clocks RST_ROT>;
271 mixer0: mixer@100000 {
272 compatible = "allwinner,sun50i-a64-de2-mixer-0";
273 reg = <0x100000 0x100000>;
274 clocks = <&display_clocks CLK_BUS_MIXER0>,
275 <&display_clocks CLK_MIXER0>;
278 resets = <&display_clocks RST_MIXER0>;
281 #address-cells = <1>;
285 #address-cells = <1>;
289 mixer0_out_tcon0: endpoint@0 {
291 remote-endpoint = <&tcon0_in_mixer0>;
294 mixer0_out_tcon1: endpoint@1 {
296 remote-endpoint = <&tcon1_in_mixer0>;
302 mixer1: mixer@200000 {
303 compatible = "allwinner,sun50i-a64-de2-mixer-1";
304 reg = <0x200000 0x100000>;
305 clocks = <&display_clocks CLK_BUS_MIXER1>,
306 <&display_clocks CLK_MIXER1>;
309 resets = <&display_clocks RST_MIXER1>;
312 #address-cells = <1>;
316 #address-cells = <1>;
320 mixer1_out_tcon0: endpoint@0 {
322 remote-endpoint = <&tcon0_in_mixer1>;
325 mixer1_out_tcon1: endpoint@1 {
327 remote-endpoint = <&tcon1_in_mixer1>;
334 syscon: syscon@1c00000 {
335 compatible = "allwinner,sun50i-a64-system-control";
336 reg = <0x01c00000 0x1000>;
337 #address-cells = <1>;
342 compatible = "mmio-sram";
343 reg = <0x00018000 0x28000>;
344 #address-cells = <1>;
346 ranges = <0 0x00018000 0x28000>;
348 de2_sram: sram-section@0 {
349 compatible = "allwinner,sun50i-a64-sram-c";
350 reg = <0x0000 0x28000>;
354 sram_c1: sram@1d00000 {
355 compatible = "mmio-sram";
356 reg = <0x01d00000 0x40000>;
357 #address-cells = <1>;
359 ranges = <0 0x01d00000 0x40000>;
361 ve_sram: sram-section@0 {
362 compatible = "allwinner,sun50i-a64-sram-c1",
363 "allwinner,sun4i-a10-sram-c1";
364 reg = <0x000000 0x40000>;
369 dma: dma-controller@1c02000 {
370 compatible = "allwinner,sun50i-a64-dma";
371 reg = <0x01c02000 0x1000>;
372 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
373 clocks = <&ccu CLK_BUS_DMA>;
376 resets = <&ccu RST_BUS_DMA>;
380 tcon0: lcd-controller@1c0c000 {
381 compatible = "allwinner,sun50i-a64-tcon-lcd",
382 "allwinner,sun8i-a83t-tcon-lcd";
383 reg = <0x01c0c000 0x1000>;
384 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
385 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
386 clock-names = "ahb", "tcon-ch0";
387 clock-output-names = "tcon-pixel-clock";
389 resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
390 reset-names = "lcd", "lvds";
393 #address-cells = <1>;
397 #address-cells = <1>;
401 tcon0_in_mixer0: endpoint@0 {
403 remote-endpoint = <&mixer0_out_tcon0>;
406 tcon0_in_mixer1: endpoint@1 {
408 remote-endpoint = <&mixer1_out_tcon0>;
413 #address-cells = <1>;
417 tcon0_out_dsi: endpoint@1 {
419 remote-endpoint = <&dsi_in_tcon0>;
420 allwinner,tcon-channel = <1>;
426 tcon1: lcd-controller@1c0d000 {
427 compatible = "allwinner,sun50i-a64-tcon-tv",
428 "allwinner,sun8i-a83t-tcon-tv";
429 reg = <0x01c0d000 0x1000>;
430 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
431 clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
432 clock-names = "ahb", "tcon-ch1";
433 resets = <&ccu RST_BUS_TCON1>;
437 #address-cells = <1>;
441 #address-cells = <1>;
445 tcon1_in_mixer0: endpoint@0 {
447 remote-endpoint = <&mixer0_out_tcon1>;
450 tcon1_in_mixer1: endpoint@1 {
452 remote-endpoint = <&mixer1_out_tcon1>;
457 #address-cells = <1>;
461 tcon1_out_hdmi: endpoint@1 {
463 remote-endpoint = <&hdmi_in_tcon1>;
469 video-codec@1c0e000 {
470 compatible = "allwinner,sun50i-a64-video-engine";
471 reg = <0x01c0e000 0x1000>;
472 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
474 clock-names = "ahb", "mod", "ram";
475 resets = <&ccu RST_BUS_VE>;
476 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
477 allwinner,sram = <&ve_sram 1>;
481 compatible = "allwinner,sun50i-a64-mmc";
482 reg = <0x01c0f000 0x1000>;
483 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
484 clock-names = "ahb", "mmc";
485 resets = <&ccu RST_BUS_MMC0>;
487 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
488 max-frequency = <150000000>;
490 #address-cells = <1>;
495 compatible = "allwinner,sun50i-a64-mmc";
496 reg = <0x01c10000 0x1000>;
497 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
498 clock-names = "ahb", "mmc";
499 resets = <&ccu RST_BUS_MMC1>;
501 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
502 max-frequency = <150000000>;
504 #address-cells = <1>;
509 compatible = "allwinner,sun50i-a64-emmc";
510 reg = <0x01c11000 0x1000>;
511 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
512 clock-names = "ahb", "mmc";
513 resets = <&ccu RST_BUS_MMC2>;
515 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
516 max-frequency = <200000000>;
518 #address-cells = <1>;
522 sid: eeprom@1c14000 {
523 compatible = "allwinner,sun50i-a64-sid";
524 reg = <0x1c14000 0x400>;
525 #address-cells = <1>;
528 ths_calibration: thermal-sensor-calibration@34 {
533 crypto: crypto@1c15000 {
534 compatible = "allwinner,sun50i-a64-crypto";
535 reg = <0x01c15000 0x1000>;
536 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
537 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
538 clock-names = "bus", "mod";
539 resets = <&ccu RST_BUS_CE>;
542 msgbox: mailbox@1c17000 {
543 compatible = "allwinner,sun50i-a64-msgbox",
544 "allwinner,sun6i-a31-msgbox";
545 reg = <0x01c17000 0x1000>;
546 clocks = <&ccu CLK_BUS_MSGBOX>;
547 resets = <&ccu RST_BUS_MSGBOX>;
548 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
552 usb_otg: usb@1c19000 {
553 compatible = "allwinner,sun8i-a33-musb";
554 reg = <0x01c19000 0x0400>;
555 clocks = <&ccu CLK_BUS_OTG>;
556 resets = <&ccu RST_BUS_OTG>;
557 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
558 interrupt-names = "mc";
561 extcon = <&usbphy 0>;
566 usbphy: phy@1c19400 {
567 compatible = "allwinner,sun50i-a64-usb-phy";
568 reg = <0x01c19400 0x14>,
571 reg-names = "phy_ctrl",
574 clocks = <&ccu CLK_USB_PHY0>,
576 clock-names = "usb0_phy",
578 resets = <&ccu RST_USB_PHY0>,
580 reset-names = "usb0_reset",
587 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
588 reg = <0x01c1a000 0x100>;
589 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
590 clocks = <&ccu CLK_BUS_OHCI0>,
591 <&ccu CLK_BUS_EHCI0>,
592 <&ccu CLK_USB_OHCI0>;
593 resets = <&ccu RST_BUS_OHCI0>,
594 <&ccu RST_BUS_EHCI0>;
599 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
600 reg = <0x01c1a400 0x100>;
601 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
602 clocks = <&ccu CLK_BUS_OHCI0>,
603 <&ccu CLK_USB_OHCI0>;
604 resets = <&ccu RST_BUS_OHCI0>;
609 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
610 reg = <0x01c1b000 0x100>;
611 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
612 clocks = <&ccu CLK_BUS_OHCI1>,
613 <&ccu CLK_BUS_EHCI1>,
614 <&ccu CLK_USB_OHCI1>;
615 resets = <&ccu RST_BUS_OHCI1>,
616 <&ccu RST_BUS_EHCI1>;
623 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
624 reg = <0x01c1b400 0x100>;
625 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
626 clocks = <&ccu CLK_BUS_OHCI1>,
627 <&ccu CLK_USB_OHCI1>;
628 resets = <&ccu RST_BUS_OHCI1>;
635 compatible = "allwinner,sun50i-a64-ccu";
636 reg = <0x01c20000 0x400>;
637 clocks = <&osc24M>, <&rtc 0>;
638 clock-names = "hosc", "losc";
643 pio: pinctrl@1c20800 {
644 compatible = "allwinner,sun50i-a64-pinctrl";
645 reg = <0x01c20800 0x400>;
646 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
647 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
648 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
649 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
650 clock-names = "apb", "hosc", "losc";
653 interrupt-controller;
654 #interrupt-cells = <3>;
657 pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6",
658 "PE7", "PE8", "PE9", "PE10", "PE11";
663 csi_mclk_pin: csi-mclk-pin {
668 i2c0_pins: i2c0-pins {
673 i2c1_pins: i2c1-pins {
678 i2c2_pins: i2c2-pins {
679 pins = "PE14", "PE15";
684 lcd_rgb666_pins: lcd-rgb666-pins {
685 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
686 "PD5", "PD6", "PD7", "PD8", "PD9",
687 "PD10", "PD11", "PD12", "PD13",
688 "PD14", "PD15", "PD16", "PD17",
689 "PD18", "PD19", "PD20", "PD21";
693 mmc0_pins: mmc0-pins {
694 pins = "PF0", "PF1", "PF2", "PF3",
697 drive-strength = <30>;
701 mmc1_pins: mmc1-pins {
702 pins = "PG0", "PG1", "PG2", "PG3",
705 drive-strength = <30>;
709 mmc2_pins: mmc2-pins {
710 pins = "PC5", "PC6", "PC8", "PC9",
711 "PC10","PC11", "PC12", "PC13",
712 "PC14", "PC15", "PC16";
714 drive-strength = <30>;
718 mmc2_ds_pin: mmc2-ds-pin {
721 drive-strength = <30>;
730 rmii_pins: rmii-pins {
731 pins = "PD10", "PD11", "PD13", "PD14", "PD17",
732 "PD18", "PD19", "PD20", "PD22", "PD23";
734 drive-strength = <40>;
737 rgmii_pins: rgmii-pins {
738 pins = "PD8", "PD9", "PD10", "PD11", "PD12",
739 "PD13", "PD15", "PD16", "PD17", "PD18",
740 "PD19", "PD20", "PD21", "PD22", "PD23";
742 drive-strength = <40>;
745 spdif_tx_pin: spdif-tx-pin {
750 spi0_pins: spi0-pins {
751 pins = "PC0", "PC1", "PC2", "PC3";
755 spi1_pins: spi1-pins {
756 pins = "PD0", "PD1", "PD2", "PD3";
760 uart0_pb_pins: uart0-pb-pins {
765 uart1_pins: uart1-pins {
770 uart1_rts_cts_pins: uart1-rts-cts-pins {
775 uart2_pins: uart2-pins {
780 uart3_pins: uart3-pins {
785 uart4_pins: uart4-pins {
790 uart4_rts_cts_pins: uart4-rts-cts-pins {
796 spdif: spdif@1c21000 {
797 #sound-dai-cells = <0>;
798 compatible = "allwinner,sun50i-a64-spdif",
799 "allwinner,sun8i-h3-spdif";
800 reg = <0x01c21000 0x400>;
801 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
802 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
803 resets = <&ccu RST_BUS_SPDIF>;
804 clock-names = "apb", "spdif";
807 pinctrl-names = "default";
808 pinctrl-0 = <&spdif_tx_pin>;
812 lradc: lradc@1c21800 {
813 compatible = "allwinner,sun50i-a64-lradc",
814 "allwinner,sun8i-a83t-r-lradc";
815 reg = <0x01c21800 0x400>;
816 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
821 #sound-dai-cells = <0>;
822 compatible = "allwinner,sun50i-a64-i2s",
823 "allwinner,sun8i-h3-i2s";
824 reg = <0x01c22000 0x400>;
825 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
826 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
827 clock-names = "apb", "mod";
828 resets = <&ccu RST_BUS_I2S0>;
829 dma-names = "rx", "tx";
830 dmas = <&dma 3>, <&dma 3>;
835 #sound-dai-cells = <0>;
836 compatible = "allwinner,sun50i-a64-i2s",
837 "allwinner,sun8i-h3-i2s";
838 reg = <0x01c22400 0x400>;
839 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
840 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
841 clock-names = "apb", "mod";
842 resets = <&ccu RST_BUS_I2S1>;
843 dma-names = "rx", "tx";
844 dmas = <&dma 4>, <&dma 4>;
849 #sound-dai-cells = <0>;
850 compatible = "allwinner,sun50i-a64-codec-i2s";
851 reg = <0x01c22c00 0x200>;
852 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
853 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
854 clock-names = "apb", "mod";
855 resets = <&ccu RST_BUS_CODEC>;
856 dmas = <&dma 15>, <&dma 15>;
857 dma-names = "rx", "tx";
861 codec: codec@1c22e00 {
862 #sound-dai-cells = <0>;
863 compatible = "allwinner,sun8i-a33-codec";
864 reg = <0x01c22e00 0x600>;
865 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
866 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
867 clock-names = "bus", "mod";
871 ths: thermal-sensor@1c25000 {
872 compatible = "allwinner,sun50i-a64-ths";
873 reg = <0x01c25000 0x100>;
874 clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
875 clock-names = "bus", "mod";
876 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
877 resets = <&ccu RST_BUS_THS>;
878 nvmem-cells = <&ths_calibration>;
879 nvmem-cell-names = "calibration";
880 #thermal-sensor-cells = <1>;
883 uart0: serial@1c28000 {
884 compatible = "snps,dw-apb-uart";
885 reg = <0x01c28000 0x400>;
886 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
889 clocks = <&ccu CLK_BUS_UART0>;
890 resets = <&ccu RST_BUS_UART0>;
894 uart1: serial@1c28400 {
895 compatible = "snps,dw-apb-uart";
896 reg = <0x01c28400 0x400>;
897 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
900 clocks = <&ccu CLK_BUS_UART1>;
901 resets = <&ccu RST_BUS_UART1>;
905 uart2: serial@1c28800 {
906 compatible = "snps,dw-apb-uart";
907 reg = <0x01c28800 0x400>;
908 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
911 clocks = <&ccu CLK_BUS_UART2>;
912 resets = <&ccu RST_BUS_UART2>;
916 uart3: serial@1c28c00 {
917 compatible = "snps,dw-apb-uart";
918 reg = <0x01c28c00 0x400>;
919 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
922 clocks = <&ccu CLK_BUS_UART3>;
923 resets = <&ccu RST_BUS_UART3>;
927 uart4: serial@1c29000 {
928 compatible = "snps,dw-apb-uart";
929 reg = <0x01c29000 0x400>;
930 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
933 clocks = <&ccu CLK_BUS_UART4>;
934 resets = <&ccu RST_BUS_UART4>;
939 compatible = "allwinner,sun6i-a31-i2c";
940 reg = <0x01c2ac00 0x400>;
941 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
942 clocks = <&ccu CLK_BUS_I2C0>;
943 resets = <&ccu RST_BUS_I2C0>;
944 pinctrl-names = "default";
945 pinctrl-0 = <&i2c0_pins>;
947 #address-cells = <1>;
952 compatible = "allwinner,sun6i-a31-i2c";
953 reg = <0x01c2b000 0x400>;
954 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
955 clocks = <&ccu CLK_BUS_I2C1>;
956 resets = <&ccu RST_BUS_I2C1>;
957 pinctrl-names = "default";
958 pinctrl-0 = <&i2c1_pins>;
960 #address-cells = <1>;
965 compatible = "allwinner,sun6i-a31-i2c";
966 reg = <0x01c2b400 0x400>;
967 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
968 clocks = <&ccu CLK_BUS_I2C2>;
969 resets = <&ccu RST_BUS_I2C2>;
970 pinctrl-names = "default";
971 pinctrl-0 = <&i2c2_pins>;
973 #address-cells = <1>;
978 compatible = "allwinner,sun8i-h3-spi";
979 reg = <0x01c68000 0x1000>;
980 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
981 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
982 clock-names = "ahb", "mod";
983 dmas = <&dma 23>, <&dma 23>;
984 dma-names = "rx", "tx";
985 pinctrl-names = "default";
986 pinctrl-0 = <&spi0_pins>;
987 resets = <&ccu RST_BUS_SPI0>;
990 #address-cells = <1>;
995 compatible = "allwinner,sun8i-h3-spi";
996 reg = <0x01c69000 0x1000>;
997 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
998 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
999 clock-names = "ahb", "mod";
1000 dmas = <&dma 24>, <&dma 24>;
1001 dma-names = "rx", "tx";
1002 pinctrl-names = "default";
1003 pinctrl-0 = <&spi1_pins>;
1004 resets = <&ccu RST_BUS_SPI1>;
1005 status = "disabled";
1007 #address-cells = <1>;
1011 emac: ethernet@1c30000 {
1012 compatible = "allwinner,sun50i-a64-emac";
1014 reg = <0x01c30000 0x10000>;
1015 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1016 interrupt-names = "macirq";
1017 resets = <&ccu RST_BUS_EMAC>;
1018 reset-names = "stmmaceth";
1019 clocks = <&ccu CLK_BUS_EMAC>;
1020 clock-names = "stmmaceth";
1021 status = "disabled";
1024 compatible = "snps,dwmac-mdio";
1025 #address-cells = <1>;
1031 compatible = "allwinner,sun50i-a64-mali", "arm,mali-400";
1032 reg = <0x01c40000 0x10000>;
1033 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1034 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1035 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1036 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1037 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1038 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1039 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1040 interrupt-names = "gp",
1047 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
1048 clock-names = "bus", "core";
1049 resets = <&ccu RST_BUS_GPU>;
1052 gic: interrupt-controller@1c81000 {
1053 compatible = "arm,gic-400";
1054 reg = <0x01c81000 0x1000>,
1055 <0x01c82000 0x2000>,
1056 <0x01c84000 0x2000>,
1057 <0x01c86000 0x2000>;
1058 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1059 interrupt-controller;
1060 #interrupt-cells = <3>;
1064 compatible = "allwinner,sun50i-a64-pwm",
1065 "allwinner,sun5i-a13-pwm";
1066 reg = <0x01c21400 0x400>;
1068 pinctrl-names = "default";
1069 pinctrl-0 = <&pwm_pin>;
1071 status = "disabled";
1074 mbus: dram-controller@1c62000 {
1075 compatible = "allwinner,sun50i-a64-mbus";
1076 reg = <0x01c62000 0x1000>;
1077 clocks = <&ccu 112>;
1078 #address-cells = <1>;
1080 dma-ranges = <0x00000000 0x40000000 0xc0000000>;
1081 #interconnect-cells = <1>;
1085 compatible = "allwinner,sun50i-a64-csi";
1086 reg = <0x01cb0000 0x1000>;
1087 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1088 clocks = <&ccu CLK_BUS_CSI>,
1089 <&ccu CLK_CSI_SCLK>,
1090 <&ccu CLK_DRAM_CSI>;
1091 clock-names = "bus", "mod", "ram";
1092 resets = <&ccu RST_BUS_CSI>;
1093 pinctrl-names = "default";
1094 pinctrl-0 = <&csi_pins>;
1095 status = "disabled";
1099 compatible = "allwinner,sun50i-a64-mipi-dsi";
1100 reg = <0x01ca0000 0x1000>;
1101 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1102 clocks = <&ccu CLK_BUS_MIPI_DSI>;
1103 resets = <&ccu RST_BUS_MIPI_DSI>;
1106 status = "disabled";
1107 #address-cells = <1>;
1111 dsi_in_tcon0: endpoint {
1112 remote-endpoint = <&tcon0_out_dsi>;
1117 dphy: d-phy@1ca1000 {
1118 compatible = "allwinner,sun50i-a64-mipi-dphy",
1119 "allwinner,sun6i-a31-mipi-dphy";
1120 reg = <0x01ca1000 0x1000>;
1121 clocks = <&ccu CLK_BUS_MIPI_DSI>,
1122 <&ccu CLK_DSI_DPHY>;
1123 clock-names = "bus", "mod";
1124 resets = <&ccu RST_BUS_MIPI_DSI>;
1125 status = "disabled";
1129 deinterlace: deinterlace@1e00000 {
1130 compatible = "allwinner,sun50i-a64-deinterlace",
1131 "allwinner,sun8i-h3-deinterlace";
1132 reg = <0x01e00000 0x20000>;
1133 clocks = <&ccu CLK_BUS_DEINTERLACE>,
1134 <&ccu CLK_DEINTERLACE>,
1135 <&ccu CLK_DRAM_DEINTERLACE>;
1136 clock-names = "bus", "mod", "ram";
1137 resets = <&ccu RST_BUS_DEINTERLACE>;
1138 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1139 interconnects = <&mbus 9>;
1140 interconnect-names = "dma-mem";
1143 hdmi: hdmi@1ee0000 {
1144 compatible = "allwinner,sun50i-a64-dw-hdmi",
1145 "allwinner,sun8i-a83t-dw-hdmi";
1146 reg = <0x01ee0000 0x10000>;
1148 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1149 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
1151 clock-names = "iahb", "isfr", "tmds";
1152 resets = <&ccu RST_BUS_HDMI1>;
1153 reset-names = "ctrl";
1156 status = "disabled";
1159 #address-cells = <1>;
1165 hdmi_in_tcon1: endpoint {
1166 remote-endpoint = <&tcon1_out_hdmi>;
1176 hdmi_phy: hdmi-phy@1ef0000 {
1177 compatible = "allwinner,sun50i-a64-hdmi-phy";
1178 reg = <0x01ef0000 0x10000>;
1179 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
1180 <&ccu CLK_PLL_VIDEO0>;
1181 clock-names = "bus", "mod", "pll-0";
1182 resets = <&ccu RST_BUS_HDMI0>;
1183 reset-names = "phy";
1188 compatible = "allwinner,sun50i-a64-rtc",
1189 "allwinner,sun8i-h3-rtc";
1190 reg = <0x01f00000 0x400>;
1191 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1192 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1193 clock-output-names = "osc32k", "osc32k-out", "iosc";
1198 r_intc: interrupt-controller@1f00c00 {
1199 compatible = "allwinner,sun50i-a64-r-intc",
1200 "allwinner,sun6i-a31-r-intc";
1201 interrupt-controller;
1202 #interrupt-cells = <2>;
1203 reg = <0x01f00c00 0x400>;
1204 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1207 r_ccu: clock@1f01400 {
1208 compatible = "allwinner,sun50i-a64-r-ccu";
1209 reg = <0x01f01400 0x100>;
1210 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
1211 <&ccu CLK_PLL_PERIPH0>;
1212 clock-names = "hosc", "losc", "iosc", "pll-periph";
1217 codec_analog: codec-analog@1f015c0 {
1218 compatible = "allwinner,sun50i-a64-codec-analog";
1219 reg = <0x01f015c0 0x4>;
1220 status = "disabled";
1223 r_i2c: i2c@1f02400 {
1224 compatible = "allwinner,sun50i-a64-i2c",
1225 "allwinner,sun6i-a31-i2c";
1226 reg = <0x01f02400 0x400>;
1227 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1228 clocks = <&r_ccu CLK_APB0_I2C>;
1229 resets = <&r_ccu RST_APB0_I2C>;
1230 status = "disabled";
1231 #address-cells = <1>;
1236 compatible = "allwinner,sun50i-a64-ir",
1237 "allwinner,sun6i-a31-ir";
1238 reg = <0x01f02000 0x400>;
1239 clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
1240 clock-names = "apb", "ir";
1241 resets = <&r_ccu RST_APB0_IR>;
1242 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1243 pinctrl-names = "default";
1244 pinctrl-0 = <&r_ir_rx_pin>;
1245 status = "disabled";
1248 r_pwm: pwm@1f03800 {
1249 compatible = "allwinner,sun50i-a64-pwm",
1250 "allwinner,sun5i-a13-pwm";
1251 reg = <0x01f03800 0x400>;
1253 pinctrl-names = "default";
1254 pinctrl-0 = <&r_pwm_pin>;
1256 status = "disabled";
1259 r_pio: pinctrl@1f02c00 {
1260 compatible = "allwinner,sun50i-a64-r-pinctrl";
1261 reg = <0x01f02c00 0x400>;
1262 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1263 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
1264 clock-names = "apb", "hosc", "losc";
1267 interrupt-controller;
1268 #interrupt-cells = <3>;
1270 r_i2c_pl89_pins: r-i2c-pl89-pins {
1271 pins = "PL8", "PL9";
1275 r_ir_rx_pin: r-ir-rx-pin {
1277 function = "s_cir_rx";
1280 r_pwm_pin: r-pwm-pin {
1285 r_rsb_pins: r-rsb-pins {
1286 pins = "PL0", "PL1";
1291 r_rsb: rsb@1f03400 {
1292 compatible = "allwinner,sun8i-a23-rsb";
1293 reg = <0x01f03400 0x400>;
1294 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1295 clocks = <&r_ccu 6>;
1296 clock-frequency = <3000000>;
1297 resets = <&r_ccu 2>;
1298 pinctrl-names = "default";
1299 pinctrl-0 = <&r_rsb_pins>;
1300 status = "disabled";
1301 #address-cells = <1>;
1305 wdt0: watchdog@1c20ca0 {
1306 compatible = "allwinner,sun50i-a64-wdt",
1307 "allwinner,sun6i-a31-wdt";
1308 reg = <0x01c20ca0 0x20>;
1309 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;