arch/arm/dts/sun50i-a64.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 // Copyright (C) 2016 ARM Ltd.
   3 // based on the Allwinner H3 dtsi:
   4 //    Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
   5
   6 #include <dt-bindings/clock/sun50i-a64-ccu.h>
   7 #include <dt-bindings/clock/sun8i-de2.h>
   8 #include <dt-bindings/clock/sun8i-r-ccu.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/reset/sun50i-a64-ccu.h>
  11 #include <dt-bindings/reset/sun8i-de2.h>
  12 #include <dt-bindings/reset/sun8i-r-ccu.h>
  13 #include <dt-bindings/thermal/thermal.h>
  14
  15 / {
  16         interrupt-parent = <&gic>;
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         chosen {
  21                 #address-cells = <1>;
  22                 #size-cells = <1>;
  23                 ranges;
  24
  25                 simplefb_lcd: framebuffer-lcd {
  26                         compatible = "allwinner,simple-framebuffer",
  27                                      "simple-framebuffer";
  28                         allwinner,pipeline = "mixer0-lcd0";
  29                         clocks = <&ccu CLK_TCON0>,
  30                                  <&display_clocks CLK_MIXER0>;
  31                         status = "disabled";
  32                 };
  33
  34                 simplefb_hdmi: framebuffer-hdmi {
  35                         compatible = "allwinner,simple-framebuffer",
  36                                      "simple-framebuffer";
  37                         allwinner,pipeline = "mixer1-lcd1-hdmi";
  38                         clocks = <&display_clocks CLK_MIXER1>,
  39                                  <&ccu CLK_TCON1>, <&ccu CLK_HDMI>;
  40                         status = "disabled";
  41                 };
  42         };
  43
  44         cpus {
  45                 #address-cells = <1>;
  46                 #size-cells = <0>;
  47
  48                 cpu0: cpu@0 {
  49                         compatible = "arm,cortex-a53";
  50                         device_type = "cpu";
  51                         reg = <0>;
  52                         enable-method = "psci";
  53                         next-level-cache = <&L2>;
  54                         clocks = <&ccu CLK_CPUX>;
  55                         clock-names = "cpu";
  56                         #cooling-cells = <2>;
  57                 };
  58
  59                 cpu1: cpu@1 {
  60                         compatible = "arm,cortex-a53";
  61                         device_type = "cpu";
  62                         reg = <1>;
  63                         enable-method = "psci";
  64                         next-level-cache = <&L2>;
  65                         clocks = <&ccu CLK_CPUX>;
  66                         clock-names = "cpu";
  67                         #cooling-cells = <2>;
  68                 };
  69
  70                 cpu2: cpu@2 {
  71                         compatible = "arm,cortex-a53";
  72                         device_type = "cpu";
  73                         reg = <2>;
  74                         enable-method = "psci";
  75                         next-level-cache = <&L2>;
  76                         clocks = <&ccu CLK_CPUX>;
  77                         clock-names = "cpu";
  78                         #cooling-cells = <2>;
  79                 };
  80
  81                 cpu3: cpu@3 {
  82                         compatible = "arm,cortex-a53";
  83                         device_type = "cpu";
  84                         reg = <3>;
  85                         enable-method = "psci";
  86                         next-level-cache = <&L2>;
  87                         clocks = <&ccu CLK_CPUX>;
  88                         clock-names = "cpu";
  89                         #cooling-cells = <2>;
  90                 };
  91
  92                 L2: l2-cache {
  93                         compatible = "cache";
  94                         cache-level = <2>;
  95                 };
  96         };
  97
  98         de: display-engine {
  99                 compatible = "allwinner,sun50i-a64-display-engine";
 100                 allwinner,pipelines = <&mixer0>,
 101                                       <&mixer1>;
 102                 status = "disabled";
 103         };
 104
 105         osc24M: osc24M_clk {
 106                 #clock-cells = <0>;
 107                 compatible = "fixed-clock";
 108                 clock-frequency = <24000000>;
 109                 clock-output-names = "osc24M";
 110         };
 111
 112         osc32k: osc32k_clk {
 113                 #clock-cells = <0>;
 114                 compatible = "fixed-clock";
 115                 clock-frequency = <32768>;
 116                 clock-output-names = "ext-osc32k";
 117         };
 118
 119         pmu {
 120                 compatible = "arm,cortex-a53-pmu";
 121                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 122                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 123                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 124                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 125                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 126         };
 127
 128         psci {
 129                 compatible = "arm,psci-0.2";
 130                 method = "smc";
 131         };
 132
 133         sound: sound {
 134                 compatible = "simple-audio-card";
 135                 simple-audio-card,name = "sun50i-a64-audio";
 136                 simple-audio-card,format = "i2s";
 137                 simple-audio-card,frame-master = <&cpudai>;
 138                 simple-audio-card,bitclock-master = <&cpudai>;
 139                 simple-audio-card,mclk-fs = <128>;
 140                 simple-audio-card,aux-devs = <&codec_analog>;
 141                 simple-audio-card,routing =
 142                                 "Left DAC", "DACL",
 143                                 "Right DAC", "DACR",
 144                                 "ADCL", "Left ADC",
 145                                 "ADCR", "Right ADC";
 146                 status = "disabled";
 147
 148                 cpudai: simple-audio-card,cpu {
 149                         sound-dai = <&dai>;
 150                 };
 151
 152                 link_codec: simple-audio-card,codec {
 153                         sound-dai = <&codec>;
 154                 };
 155         };
 156
 157         timer {
 158                 compatible = "arm,armv8-timer";
 159                 allwinner,erratum-unknown1;
 160                 arm,no-tick-in-suspend;
 161                 interrupts = <GIC_PPI 13
 162                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 163                              <GIC_PPI 14
 164                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 165                              <GIC_PPI 11
 166                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 167                              <GIC_PPI 10
 168                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 169         };
 170
 171         thermal-zones {
 172                 cpu_thermal: cpu0-thermal {
 173                         /* milliseconds */
 174                         polling-delay-passive = <0>;
 175                         polling-delay = <0>;
 176                         thermal-sensors = <&ths 0>;
 177
 178                         cooling-maps {
 179                                 map0 {
 180                                         trip = <&cpu_alert0>;
 181                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 182                                                          <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 183                                                          <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 184                                                          <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 185                                 };
 186                                 map1 {
 187                                         trip = <&cpu_alert1>;
 188                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 189                                                          <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 190                                                          <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 191                                                          <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 192                                 };
 193                         };
 194
 195                         trips {
 196                                 cpu_alert0: cpu_alert0 {
 197                                         /* milliCelsius */
 198                                         temperature = <75000>;
 199                                         hysteresis = <2000>;
 200                                         type = "passive";
 201                                 };
 202
 203                                 cpu_alert1: cpu_alert1 {
 204                                         /* milliCelsius */
 205                                         temperature = <90000>;
 206                                         hysteresis = <2000>;
 207                                         type = "hot";
 208                                 };
 209
 210                                 cpu_crit: cpu_crit {
 211                                         /* milliCelsius */
 212                                         temperature = <110000>;
 213                                         hysteresis = <2000>;
 214                                         type = "critical";
 215                                 };
 216                         };
 217                 };
 218
 219                 gpu0_thermal: gpu0-thermal {
 220                         /* milliseconds */
 221                         polling-delay-passive = <0>;
 222                         polling-delay = <0>;
 223                         thermal-sensors = <&ths 1>;
 224                 };
 225
 226                 gpu1_thermal: gpu1-thermal {
 227                         /* milliseconds */
 228                         polling-delay-passive = <0>;
 229                         polling-delay = <0>;
 230                         thermal-sensors = <&ths 2>;
 231                 };
 232         };
 233
 234         soc {
 235                 compatible = "simple-bus";
 236                 #address-cells = <1>;
 237                 #size-cells = <1>;
 238                 ranges;
 239
 240                 bus@1000000 {
 241                         compatible = "allwinner,sun50i-a64-de2";
 242                         reg = <0x1000000 0x400000>;
 243                         allwinner,sram = <&de2_sram 1>;
 244                         #address-cells = <1>;
 245                         #size-cells = <1>;
 246                         ranges = <0 0x1000000 0x400000>;
 247
 248                         display_clocks: clock@0 {
 249                                 compatible = "allwinner,sun50i-a64-de2-clk";
 250                                 reg = <0x0 0x10000>;
 251                                 clocks = <&ccu CLK_BUS_DE>,
 252                                          <&ccu CLK_DE>;
 253                                 clock-names = "bus",
 254                                               "mod";
 255                                 resets = <&ccu RST_BUS_DE>;
 256                                 #clock-cells = <1>;
 257                                 #reset-cells = <1>;
 258                         };
 259
 260                         rotate: rotate@20000 {
 261                                 compatible = "allwinner,sun50i-a64-de2-rotate",
 262                                              "allwinner,sun8i-a83t-de2-rotate";
 263                                 reg = <0x20000 0x10000>;
 264                                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 265                                 clocks = <&display_clocks CLK_BUS_ROT>,
 266                                          <&display_clocks CLK_ROT>;
 267                                 clock-names = "bus",
 268                                               "mod";
 269                                 resets = <&display_clocks RST_ROT>;
 270                         };
 271
 272                         mixer0: mixer@100000 {
 273                                 compatible = "allwinner,sun50i-a64-de2-mixer-0";
 274                                 reg = <0x100000 0x100000>;
 275                                 clocks = <&display_clocks CLK_BUS_MIXER0>,
 276                                          <&display_clocks CLK_MIXER0>;
 277                                 clock-names = "bus",
 278                                               "mod";
 279                                 resets = <&display_clocks RST_MIXER0>;
 280
 281                                 ports {
 282                                         #address-cells = <1>;
 283                                         #size-cells = <0>;
 284
 285                                         mixer0_out: port@1 {
 286                                                 #address-cells = <1>;
 287                                                 #size-cells = <0>;
 288                                                 reg = <1>;
 289
 290                                                 mixer0_out_tcon0: endpoint@0 {
 291                                                         reg = <0>;
 292                                                         remote-endpoint = <&tcon0_in_mixer0>;
 293                                                 };
 294
 295                                                 mixer0_out_tcon1: endpoint@1 {
 296                                                         reg = <1>;
 297                                                         remote-endpoint = <&tcon1_in_mixer0>;
 298                                                 };
 299                                         };
 300                                 };
 301                         };
 302
 303                         mixer1: mixer@200000 {
 304                                 compatible = "allwinner,sun50i-a64-de2-mixer-1";
 305                                 reg = <0x200000 0x100000>;
 306                                 clocks = <&display_clocks CLK_BUS_MIXER1>,
 307                                          <&display_clocks CLK_MIXER1>;
 308                                 clock-names = "bus",
 309                                               "mod";
 310                                 resets = <&display_clocks RST_MIXER1>;
 311
 312                                 ports {
 313                                         #address-cells = <1>;
 314                                         #size-cells = <0>;
 315
 316                                         mixer1_out: port@1 {
 317                                                 #address-cells = <1>;
 318                                                 #size-cells = <0>;
 319                                                 reg = <1>;
 320
 321                                                 mixer1_out_tcon0: endpoint@0 {
 322                                                         reg = <0>;
 323                                                         remote-endpoint = <&tcon0_in_mixer1>;
 324                                                 };
 325
 326                                                 mixer1_out_tcon1: endpoint@1 {
 327                                                         reg = <1>;
 328                                                         remote-endpoint = <&tcon1_in_mixer1>;
 329                                                 };
 330                                         };
 331                                 };
 332                         };
 333                 };
 334
 335                 syscon: syscon@1c00000 {
 336                         compatible = "allwinner,sun50i-a64-system-control";
 337                         reg = <0x01c00000 0x1000>;
 338                         #address-cells = <1>;
 339                         #size-cells = <1>;
 340                         ranges;
 341
 342                         sram_c: sram@18000 {
 343                                 compatible = "mmio-sram";
 344                                 reg = <0x00018000 0x28000>;
 345                                 #address-cells = <1>;
 346                                 #size-cells = <1>;
 347                                 ranges = <0 0x00018000 0x28000>;
 348
 349                                 de2_sram: sram-section@0 {
 350                                         compatible = "allwinner,sun50i-a64-sram-c";
 351                                         reg = <0x0000 0x28000>;
 352                                 };
 353                         };
 354
 355                         sram_c1: sram@1d00000 {
 356                                 compatible = "mmio-sram";
 357                                 reg = <0x01d00000 0x40000>;
 358                                 #address-cells = <1>;
 359                                 #size-cells = <1>;
 360                                 ranges = <0 0x01d00000 0x40000>;
 361
 362                                 ve_sram: sram-section@0 {
 363                                         compatible = "allwinner,sun50i-a64-sram-c1",
 364                                                      "allwinner,sun4i-a10-sram-c1";
 365                                         reg = <0x000000 0x40000>;
 366                                 };
 367                         };
 368                 };
 369
 370                 dma: dma-controller@1c02000 {
 371                         compatible = "allwinner,sun50i-a64-dma";
 372                         reg = <0x01c02000 0x1000>;
 373                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 374                         clocks = <&ccu CLK_BUS_DMA>;
 375                         dma-channels = <8>;
 376                         dma-requests = <27>;
 377                         resets = <&ccu RST_BUS_DMA>;
 378                         #dma-cells = <1>;
 379                 };
 380
 381                 tcon0: lcd-controller@1c0c000 {
 382                         compatible = "allwinner,sun50i-a64-tcon-lcd",
 383                                      "allwinner,sun8i-a83t-tcon-lcd";
 384                         reg = <0x01c0c000 0x1000>;
 385                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 386                         clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
 387                         clock-names = "ahb", "tcon-ch0";
 388                         clock-output-names = "tcon-pixel-clock";
 389                         #clock-cells = <0>;
 390                         resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
 391                         reset-names = "lcd", "lvds";
 392
 393                         ports {
 394                                 #address-cells = <1>;
 395                                 #size-cells = <0>;
 396
 397                                 tcon0_in: port@0 {
 398                                         #address-cells = <1>;
 399                                         #size-cells = <0>;
 400                                         reg = <0>;
 401
 402                                         tcon0_in_mixer0: endpoint@0 {
 403                                                 reg = <0>;
 404                                                 remote-endpoint = <&mixer0_out_tcon0>;
 405                                         };
 406
 407                                         tcon0_in_mixer1: endpoint@1 {
 408                                                 reg = <1>;
 409                                                 remote-endpoint = <&mixer1_out_tcon0>;
 410                                         };
 411                                 };
 412
 413                                 tcon0_out: port@1 {
 414                                         #address-cells = <1>;
 415                                         #size-cells = <0>;
 416                                         reg = <1>;
 417
 418                                         tcon0_out_dsi: endpoint@1 {
 419                                                 reg = <1>;
 420                                                 remote-endpoint = <&dsi_in_tcon0>;
 421                                                 allwinner,tcon-channel = <1>;
 422                                         };
 423                                 };
 424                         };
 425                 };
 426
 427                 tcon1: lcd-controller@1c0d000 {
 428                         compatible = "allwinner,sun50i-a64-tcon-tv",
 429                                      "allwinner,sun8i-a83t-tcon-tv";
 430                         reg = <0x01c0d000 0x1000>;
 431                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 432                         clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
 433                         clock-names = "ahb", "tcon-ch1";
 434                         resets = <&ccu RST_BUS_TCON1>;
 435                         reset-names = "lcd";
 436
 437                         ports {
 438                                 #address-cells = <1>;
 439                                 #size-cells = <0>;
 440
 441                                 tcon1_in: port@0 {
 442                                         #address-cells = <1>;
 443                                         #size-cells = <0>;
 444                                         reg = <0>;
 445
 446                                         tcon1_in_mixer0: endpoint@0 {
 447                                                 reg = <0>;
 448                                                 remote-endpoint = <&mixer0_out_tcon1>;
 449                                         };
 450
 451                                         tcon1_in_mixer1: endpoint@1 {
 452                                                 reg = <1>;
 453                                                 remote-endpoint = <&mixer1_out_tcon1>;
 454                                         };
 455                                 };
 456
 457                                 tcon1_out: port@1 {
 458                                         #address-cells = <1>;
 459                                         #size-cells = <0>;
 460                                         reg = <1>;
 461
 462                                         tcon1_out_hdmi: endpoint@1 {
 463                                                 reg = <1>;
 464                                                 remote-endpoint = <&hdmi_in_tcon1>;
 465                                         };
 466                                 };
 467                         };
 468                 };
 469
 470                 video-codec@1c0e000 {
 471                         compatible = "allwinner,sun50i-a64-video-engine";
 472                         reg = <0x01c0e000 0x1000>;
 473                         clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
 474                                  <&ccu CLK_DRAM_VE>;
 475                         clock-names = "ahb", "mod", "ram";
 476                         resets = <&ccu RST_BUS_VE>;
 477                         interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 478                         allwinner,sram = <&ve_sram 1>;
 479                 };
 480
 481                 mmc0: mmc@1c0f000 {
 482                         compatible = "allwinner,sun50i-a64-mmc";
 483                         reg = <0x01c0f000 0x1000>;
 484                         clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
 485                         clock-names = "ahb", "mmc";
 486                         resets = <&ccu RST_BUS_MMC0>;
 487                         reset-names = "ahb";
 488                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 489                         max-frequency = <150000000>;
 490                         status = "disabled";
 491                         #address-cells = <1>;
 492                         #size-cells = <0>;
 493                 };
 494
 495                 mmc1: mmc@1c10000 {
 496                         compatible = "allwinner,sun50i-a64-mmc";
 497                         reg = <0x01c10000 0x1000>;
 498                         clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
 499                         clock-names = "ahb", "mmc";
 500                         resets = <&ccu RST_BUS_MMC1>;
 501                         reset-names = "ahb";
 502                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 503                         max-frequency = <150000000>;
 504                         status = "disabled";
 505                         #address-cells = <1>;
 506                         #size-cells = <0>;
 507                 };
 508
 509                 mmc2: mmc@1c11000 {
 510                         compatible = "allwinner,sun50i-a64-emmc";
 511                         reg = <0x01c11000 0x1000>;
 512                         clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
 513                         clock-names = "ahb", "mmc";
 514                         resets = <&ccu RST_BUS_MMC2>;
 515                         reset-names = "ahb";
 516                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 517                         max-frequency = <150000000>;
 518                         status = "disabled";
 519                         #address-cells = <1>;
 520                         #size-cells = <0>;
 521                 };
 522
 523                 sid: eeprom@1c14000 {
 524                         compatible = "allwinner,sun50i-a64-sid";
 525                         reg = <0x1c14000 0x400>;
 526                         #address-cells = <1>;
 527                         #size-cells = <1>;
 528
 529                         ths_calibration: thermal-sensor-calibration@34 {
 530                                 reg = <0x34 0x8>;
 531                         };
 532                 };
 533
 534                 crypto: crypto@1c15000 {
 535                         compatible = "allwinner,sun50i-a64-crypto";
 536                         reg = <0x01c15000 0x1000>;
 537                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 538                         clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
 539                         clock-names = "bus", "mod";
 540                         resets = <&ccu RST_BUS_CE>;
 541                 };
 542
 543                 msgbox: mailbox@1c17000 {
 544                         compatible = "allwinner,sun50i-a64-msgbox",
 545                                      "allwinner,sun6i-a31-msgbox";
 546                         reg = <0x01c17000 0x1000>;
 547                         clocks = <&ccu CLK_BUS_MSGBOX>;
 548                         resets = <&ccu RST_BUS_MSGBOX>;
 549                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 550                         #mbox-cells = <1>;
 551                 };
 552
 553                 usb_otg: usb@1c19000 {
 554                         compatible = "allwinner,sun8i-a33-musb";
 555                         reg = <0x01c19000 0x0400>;
 556                         clocks = <&ccu CLK_BUS_OTG>;
 557                         resets = <&ccu RST_BUS_OTG>;
 558                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 559                         interrupt-names = "mc";
 560                         phys = <&usbphy 0>;
 561                         phy-names = "usb";
 562                         extcon = <&usbphy 0>;
 563                         dr_mode = "otg";
 564                         status = "disabled";
 565                 };
 566
 567                 usbphy: phy@1c19400 {
 568                         compatible = "allwinner,sun50i-a64-usb-phy";
 569                         reg = <0x01c19400 0x14>,
 570                               <0x01c1a800 0x4>,
 571                               <0x01c1b800 0x4>;
 572                         reg-names = "phy_ctrl",
 573                                     "pmu0",
 574                                     "pmu1";
 575                         clocks = <&ccu CLK_USB_PHY0>,
 576                                  <&ccu CLK_USB_PHY1>;
 577                         clock-names = "usb0_phy",
 578                                       "usb1_phy";
 579                         resets = <&ccu RST_USB_PHY0>,
 580                                  <&ccu RST_USB_PHY1>;
 581                         reset-names = "usb0_reset",
 582                                       "usb1_reset";
 583                         status = "disabled";
 584                         #phy-cells = <1>;
 585                 };
 586
 587                 ehci0: usb@1c1a000 {
 588                         compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
 589                         reg = <0x01c1a000 0x100>;
 590                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 591                         clocks = <&ccu CLK_BUS_OHCI0>,
 592                                  <&ccu CLK_BUS_EHCI0>,
 593                                  <&ccu CLK_USB_OHCI0>;
 594                         resets = <&ccu RST_BUS_OHCI0>,
 595                                  <&ccu RST_BUS_EHCI0>;
 596                         phys = <&usbphy 0>;
 597                         phy-names = "usb";
 598                         status = "disabled";
 599                 };
 600
 601                 ohci0: usb@1c1a400 {
 602                         compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
 603                         reg = <0x01c1a400 0x100>;
 604                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 605                         clocks = <&ccu CLK_BUS_OHCI0>,
 606                                  <&ccu CLK_USB_OHCI0>;
 607                         resets = <&ccu RST_BUS_OHCI0>;
 608                         phys = <&usbphy 0>;
 609                         phy-names = "usb";
 610                         status = "disabled";
 611                 };
 612
 613                 ehci1: usb@1c1b000 {
 614                         compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
 615                         reg = <0x01c1b000 0x100>;
 616                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 617                         clocks = <&ccu CLK_BUS_OHCI1>,
 618                                  <&ccu CLK_BUS_EHCI1>,
 619                                  <&ccu CLK_USB_OHCI1>;
 620                         resets = <&ccu RST_BUS_OHCI1>,
 621                                  <&ccu RST_BUS_EHCI1>;
 622                         phys = <&usbphy 1>;
 623                         phy-names = "usb";
 624                         status = "disabled";
 625                 };
 626
 627                 ohci1: usb@1c1b400 {
 628                         compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
 629                         reg = <0x01c1b400 0x100>;
 630                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 631                         clocks = <&ccu CLK_BUS_OHCI1>,
 632                                  <&ccu CLK_USB_OHCI1>;
 633                         resets = <&ccu RST_BUS_OHCI1>;
 634                         phys = <&usbphy 1>;
 635                         phy-names = "usb";
 636                         status = "disabled";
 637                 };
 638
 639                 ccu: clock@1c20000 {
 640                         compatible = "allwinner,sun50i-a64-ccu";
 641                         reg = <0x01c20000 0x400>;
 642                         clocks = <&osc24M>, <&rtc 0>;
 643                         clock-names = "hosc", "losc";
 644                         #clock-cells = <1>;
 645                         #reset-cells = <1>;
 646                 };
 647
 648                 pio: pinctrl@1c20800 {
 649                         compatible = "allwinner,sun50i-a64-pinctrl";
 650                         reg = <0x01c20800 0x400>;
 651                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 652                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 653                                      <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 654                         clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
 655                         clock-names = "apb", "hosc", "losc";
 656                         gpio-controller;
 657                         #gpio-cells = <3>;
 658                         interrupt-controller;
 659                         #interrupt-cells = <3>;
 660
 661                         csi_pins: csi-pins {
 662                                 pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6",
 663                                        "PE7", "PE8", "PE9", "PE10", "PE11";
 664                                 function = "csi";
 665                         };
 666
 667                         /omit-if-no-ref/
 668                         csi_mclk_pin: csi-mclk-pin {
 669                                 pins = "PE1";
 670                                 function = "csi";
 671                         };
 672
 673                         i2c0_pins: i2c0-pins {
 674                                 pins = "PH0", "PH1";
 675                                 function = "i2c0";
 676                         };
 677
 678                         i2c1_pins: i2c1-pins {
 679                                 pins = "PH2", "PH3";
 680                                 function = "i2c1";
 681                         };
 682
 683                         i2c2_pins: i2c2-pins {
 684                                 pins = "PE14", "PE15";
 685                                 function = "i2c2";
 686                         };
 687
 688                         /omit-if-no-ref/
 689                         lcd_rgb666_pins: lcd-rgb666-pins {
 690                                 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
 691                                        "PD5", "PD6", "PD7", "PD8", "PD9",
 692                                        "PD10", "PD11", "PD12", "PD13",
 693                                        "PD14", "PD15", "PD16", "PD17",
 694                                        "PD18", "PD19", "PD20", "PD21";
 695                                 function = "lcd0";
 696                         };
 697
 698                         mmc0_pins: mmc0-pins {
 699                                 pins = "PF0", "PF1", "PF2", "PF3",
 700                                        "PF4", "PF5";
 701                                 function = "mmc0";
 702                                 drive-strength = <30>;
 703                                 bias-pull-up;
 704                         };
 705
 706                         mmc1_pins: mmc1-pins {
 707                                 pins = "PG0", "PG1", "PG2", "PG3",
 708                                        "PG4", "PG5";
 709                                 function = "mmc1";
 710                                 drive-strength = <30>;
 711                                 bias-pull-up;
 712                         };
 713
 714                         mmc2_pins: mmc2-pins {
 715                                 pins = "PC5", "PC6", "PC8", "PC9",
 716                                        "PC10","PC11", "PC12", "PC13",
 717                                        "PC14", "PC15", "PC16";
 718                                 function = "mmc2";
 719                                 drive-strength = <30>;
 720                                 bias-pull-up;
 721                         };
 722
 723                         mmc2_ds_pin: mmc2-ds-pin {
 724                                 pins = "PC1";
 725                                 function = "mmc2";
 726                                 drive-strength = <30>;
 727                                 bias-pull-up;
 728                         };
 729
 730                         pwm_pin: pwm-pin {
 731                                 pins = "PD22";
 732                                 function = "pwm";
 733                         };
 734
 735                         rmii_pins: rmii-pins {
 736                                 pins = "PD10", "PD11", "PD13", "PD14", "PD17",
 737                                        "PD18", "PD19", "PD20", "PD22", "PD23";
 738                                 function = "emac";
 739                                 drive-strength = <40>;
 740                         };
 741
 742                         rgmii_pins: rgmii-pins {
 743                                 pins = "PD8", "PD9", "PD10", "PD11", "PD12",
 744                                        "PD13", "PD15", "PD16", "PD17", "PD18",
 745                                        "PD19", "PD20", "PD21", "PD22", "PD23";
 746                                 function = "emac";
 747                                 drive-strength = <40>;
 748                         };
 749
 750                         spdif_tx_pin: spdif-tx-pin {
 751                                 pins = "PH8";
 752                                 function = "spdif";
 753                         };
 754
 755                         spi0_pins: spi0-pins {
 756                                 pins = "PC0", "PC1", "PC2", "PC3";
 757                                 function = "spi0";
 758                         };
 759
 760                         spi1_pins: spi1-pins {
 761                                 pins = "PD0", "PD1", "PD2", "PD3";
 762                                 function = "spi1";
 763                         };
 764
 765                         uart0_pb_pins: uart0-pb-pins {
 766                                 pins = "PB8", "PB9";
 767                                 function = "uart0";
 768                         };
 769
 770                         uart1_pins: uart1-pins {
 771                                 pins = "PG6", "PG7";
 772                                 function = "uart1";
 773                         };
 774
 775                         uart1_rts_cts_pins: uart1-rts-cts-pins {
 776                                 pins = "PG8", "PG9";
 777                                 function = "uart1";
 778                         };
 779
 780                         uart2_pins: uart2-pins {
 781                                 pins = "PB0", "PB1";
 782                                 function = "uart2";
 783                         };
 784
 785                         uart3_pins: uart3-pins {
 786                                 pins = "PD0", "PD1";
 787                                 function = "uart3";
 788                         };
 789
 790                         uart4_pins: uart4-pins {
 791                                 pins = "PD2", "PD3";
 792                                 function = "uart4";
 793                         };
 794
 795                         uart4_rts_cts_pins: uart4-rts-cts-pins {
 796                                 pins = "PD4", "PD5";
 797                                 function = "uart4";
 798                         };
 799                 };
 800
 801                 spdif: spdif@1c21000 {
 802                         #sound-dai-cells = <0>;
 803                         compatible = "allwinner,sun50i-a64-spdif",
 804                                      "allwinner,sun8i-h3-spdif";
 805                         reg = <0x01c21000 0x400>;
 806                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 807                         clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
 808                         resets = <&ccu RST_BUS_SPDIF>;
 809                         clock-names = "apb", "spdif";
 810                         dmas = <&dma 2>;
 811                         dma-names = "tx";
 812                         pinctrl-names = "default";
 813                         pinctrl-0 = <&spdif_tx_pin>;
 814                         status = "disabled";
 815                 };
 816
 817                 lradc: lradc@1c21800 {
 818                         compatible = "allwinner,sun50i-a64-lradc",
 819                                      "allwinner,sun8i-a83t-r-lradc";
 820                         reg = <0x01c21800 0x400>;
 821                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 822                         status = "disabled";
 823                 };
 824
 825                 i2s0: i2s@1c22000 {
 826                         #sound-dai-cells = <0>;
 827                         compatible = "allwinner,sun50i-a64-i2s",
 828                                      "allwinner,sun8i-h3-i2s";
 829                         reg = <0x01c22000 0x400>;
 830                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 831                         clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
 832                         clock-names = "apb", "mod";
 833                         resets = <&ccu RST_BUS_I2S0>;
 834                         dma-names = "rx", "tx";
 835                         dmas = <&dma 3>, <&dma 3>;
 836                         status = "disabled";
 837                 };
 838
 839                 i2s1: i2s@1c22400 {
 840                         #sound-dai-cells = <0>;
 841                         compatible = "allwinner,sun50i-a64-i2s",
 842                                      "allwinner,sun8i-h3-i2s";
 843                         reg = <0x01c22400 0x400>;
 844                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 845                         clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
 846                         clock-names = "apb", "mod";
 847                         resets = <&ccu RST_BUS_I2S1>;
 848                         dma-names = "rx", "tx";
 849                         dmas = <&dma 4>, <&dma 4>;
 850                         status = "disabled";
 851                 };
 852
 853                 i2s2: i2s@1c22800 {
 854                         #sound-dai-cells = <0>;
 855                         compatible = "allwinner,sun50i-a64-i2s",
 856                                      "allwinner,sun8i-h3-i2s";
 857                         reg = <0x01c22800 0x400>;
 858                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 859                         clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
 860                         clock-names = "apb", "mod";
 861                         resets = <&ccu RST_BUS_I2S2>;
 862                         dma-names = "rx", "tx";
 863                         dmas = <&dma 27>, <&dma 27>;
 864                         status = "disabled";
 865                 };
 866
 867                 dai: dai@1c22c00 {
 868                         #sound-dai-cells = <0>;
 869                         compatible = "allwinner,sun50i-a64-codec-i2s";
 870                         reg = <0x01c22c00 0x200>;
 871                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 872                         clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
 873                         clock-names = "apb", "mod";
 874                         resets = <&ccu RST_BUS_CODEC>;
 875                         dmas = <&dma 15>, <&dma 15>;
 876                         dma-names = "rx", "tx";
 877                         status = "disabled";
 878                 };
 879
 880                 codec: codec@1c22e00 {
 881                         #sound-dai-cells = <0>;
 882                         compatible = "allwinner,sun50i-a64-codec",
 883                                      "allwinner,sun8i-a33-codec";
 884                         reg = <0x01c22e00 0x600>;
 885                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 886                         clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
 887                         clock-names = "bus", "mod";
 888                         status = "disabled";
 889                 };
 890
 891                 ths: thermal-sensor@1c25000 {
 892                         compatible = "allwinner,sun50i-a64-ths";
 893                         reg = <0x01c25000 0x100>;
 894                         clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
 895                         clock-names = "bus", "mod";
 896                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 897                         resets = <&ccu RST_BUS_THS>;
 898                         nvmem-cells = <&ths_calibration>;
 899                         nvmem-cell-names = "calibration";
 900                         #thermal-sensor-cells = <1>;
 901                 };
 902
 903                 uart0: serial@1c28000 {
 904                         compatible = "snps,dw-apb-uart";
 905                         reg = <0x01c28000 0x400>;
 906                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 907                         reg-shift = <2>;
 908                         reg-io-width = <4>;
 909                         clocks = <&ccu CLK_BUS_UART0>;
 910                         resets = <&ccu RST_BUS_UART0>;
 911                         status = "disabled";
 912                 };
 913
 914                 uart1: serial@1c28400 {
 915                         compatible = "snps,dw-apb-uart";
 916                         reg = <0x01c28400 0x400>;
 917                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 918                         reg-shift = <2>;
 919                         reg-io-width = <4>;
 920                         clocks = <&ccu CLK_BUS_UART1>;
 921                         resets = <&ccu RST_BUS_UART1>;
 922                         status = "disabled";
 923                 };
 924
 925                 uart2: serial@1c28800 {
 926                         compatible = "snps,dw-apb-uart";
 927                         reg = <0x01c28800 0x400>;
 928                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 929                         reg-shift = <2>;
 930                         reg-io-width = <4>;
 931                         clocks = <&ccu CLK_BUS_UART2>;
 932                         resets = <&ccu RST_BUS_UART2>;
 933                         status = "disabled";
 934                 };
 935
 936                 uart3: serial@1c28c00 {
 937                         compatible = "snps,dw-apb-uart";
 938                         reg = <0x01c28c00 0x400>;
 939                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 940                         reg-shift = <2>;
 941                         reg-io-width = <4>;
 942                         clocks = <&ccu CLK_BUS_UART3>;
 943                         resets = <&ccu RST_BUS_UART3>;
 944                         status = "disabled";
 945                 };
 946
 947                 uart4: serial@1c29000 {
 948                         compatible = "snps,dw-apb-uart";
 949                         reg = <0x01c29000 0x400>;
 950                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 951                         reg-shift = <2>;
 952                         reg-io-width = <4>;
 953                         clocks = <&ccu CLK_BUS_UART4>;
 954                         resets = <&ccu RST_BUS_UART4>;
 955                         status = "disabled";
 956                 };
 957
 958                 i2c0: i2c@1c2ac00 {
 959                         compatible = "allwinner,sun6i-a31-i2c";
 960                         reg = <0x01c2ac00 0x400>;
 961                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 962                         clocks = <&ccu CLK_BUS_I2C0>;
 963                         resets = <&ccu RST_BUS_I2C0>;
 964                         pinctrl-names = "default";
 965                         pinctrl-0 = <&i2c0_pins>;
 966                         status = "disabled";
 967                         #address-cells = <1>;
 968                         #size-cells = <0>;
 969                 };
 970
 971                 i2c1: i2c@1c2b000 {
 972                         compatible = "allwinner,sun6i-a31-i2c";
 973                         reg = <0x01c2b000 0x400>;
 974                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 975                         clocks = <&ccu CLK_BUS_I2C1>;
 976                         resets = <&ccu RST_BUS_I2C1>;
 977                         pinctrl-names = "default";
 978                         pinctrl-0 = <&i2c1_pins>;
 979                         status = "disabled";
 980                         #address-cells = <1>;
 981                         #size-cells = <0>;
 982                 };
 983
 984                 i2c2: i2c@1c2b400 {
 985                         compatible = "allwinner,sun6i-a31-i2c";
 986                         reg = <0x01c2b400 0x400>;
 987                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 988                         clocks = <&ccu CLK_BUS_I2C2>;
 989                         resets = <&ccu RST_BUS_I2C2>;
 990                         pinctrl-names = "default";
 991                         pinctrl-0 = <&i2c2_pins>;
 992                         status = "disabled";
 993                         #address-cells = <1>;
 994                         #size-cells = <0>;
 995                 };
 996
 997                 spi0: spi@1c68000 {
 998                         compatible = "allwinner,sun8i-h3-spi";
 999                         reg = <0x01c68000 0x1000>;
1000                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
1001                         clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
1002                         clock-names = "ahb", "mod";
1003                         dmas = <&dma 23>, <&dma 23>;
1004                         dma-names = "rx", "tx";
1005                         pinctrl-names = "default";
1006                         pinctrl-0 = <&spi0_pins>;
1007                         resets = <&ccu RST_BUS_SPI0>;
1008                         status = "disabled";
1009                         num-cs = <1>;
1010                         #address-cells = <1>;
1011                         #size-cells = <0>;
1012                 };
1013
1014                 spi1: spi@1c69000 {
1015                         compatible = "allwinner,sun8i-h3-spi";
1016                         reg = <0x01c69000 0x1000>;
1017                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1018                         clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
1019                         clock-names = "ahb", "mod";
1020                         dmas = <&dma 24>, <&dma 24>;
1021                         dma-names = "rx", "tx";
1022                         pinctrl-names = "default";
1023                         pinctrl-0 = <&spi1_pins>;
1024                         resets = <&ccu RST_BUS_SPI1>;
1025                         status = "disabled";
1026                         num-cs = <1>;
1027                         #address-cells = <1>;
1028                         #size-cells = <0>;
1029                 };
1030
1031                 emac: ethernet@1c30000 {
1032                         compatible = "allwinner,sun50i-a64-emac";
1033                         syscon = <&syscon>;
1034                         reg = <0x01c30000 0x10000>;
1035                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1036                         interrupt-names = "macirq";
1037                         resets = <&ccu RST_BUS_EMAC>;
1038                         reset-names = "stmmaceth";
1039                         clocks = <&ccu CLK_BUS_EMAC>;
1040                         clock-names = "stmmaceth";
1041                         status = "disabled";
1042
1043                         mdio: mdio {
1044                                 compatible = "snps,dwmac-mdio";
1045                                 #address-cells = <1>;
1046                                 #size-cells = <0>;
1047                         };
1048                 };
1049
1050                 mali: gpu@1c40000 {
1051                         compatible = "allwinner,sun50i-a64-mali", "arm,mali-400";
1052                         reg = <0x01c40000 0x10000>;
1053                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1054                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1055                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1056                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1057                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1058                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1059                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1060                         interrupt-names = "gp",
1061                                           "gpmmu",
1062                                           "pp0",
1063                                           "ppmmu0",
1064                                           "pp1",
1065                                           "ppmmu1",
1066                                           "pmu";
1067                         clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
1068                         clock-names = "bus", "core";
1069                         resets = <&ccu RST_BUS_GPU>;
1070                 };
1071
1072                 gic: interrupt-controller@1c81000 {
1073                         compatible = "arm,gic-400";
1074                         reg = <0x01c81000 0x1000>,
1075                               <0x01c82000 0x2000>,
1076                               <0x01c84000 0x2000>,
1077                               <0x01c86000 0x2000>;
1078                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1079                         interrupt-controller;
1080                         #interrupt-cells = <3>;
1081                 };
1082
1083                 pwm: pwm@1c21400 {
1084                         compatible = "allwinner,sun50i-a64-pwm",
1085                                      "allwinner,sun5i-a13-pwm";
1086                         reg = <0x01c21400 0x400>;
1087                         clocks = <&osc24M>;
1088                         pinctrl-names = "default";
1089                         pinctrl-0 = <&pwm_pin>;
1090                         #pwm-cells = <3>;
1091                         status = "disabled";
1092                 };
1093
1094                 mbus: dram-controller@1c62000 {
1095                         compatible = "allwinner,sun50i-a64-mbus";
1096                         reg = <0x01c62000 0x1000>;
1097                         clocks = <&ccu 112>;
1098                         #address-cells = <1>;
1099                         #size-cells = <1>;
1100                         dma-ranges = <0x00000000 0x40000000 0xc0000000>;
1101                         #interconnect-cells = <1>;
1102                 };
1103
1104                 csi: csi@1cb0000 {
1105                         compatible = "allwinner,sun50i-a64-csi";
1106                         reg = <0x01cb0000 0x1000>;
1107                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1108                         clocks = <&ccu CLK_BUS_CSI>,
1109                                  <&ccu CLK_CSI_SCLK>,
1110                                  <&ccu CLK_DRAM_CSI>;
1111                         clock-names = "bus", "mod", "ram";
1112                         resets = <&ccu RST_BUS_CSI>;
1113                         pinctrl-names = "default";
1114                         pinctrl-0 = <&csi_pins>;
1115                         status = "disabled";
1116                 };
1117
1118                 dsi: dsi@1ca0000 {
1119                         compatible = "allwinner,sun50i-a64-mipi-dsi";
1120                         reg = <0x01ca0000 0x1000>;
1121                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1122                         clocks = <&ccu CLK_BUS_MIPI_DSI>;
1123                         resets = <&ccu RST_BUS_MIPI_DSI>;
1124                         phys = <&dphy>;
1125                         phy-names = "dphy";
1126                         status = "disabled";
1127                         #address-cells = <1>;
1128                         #size-cells = <0>;
1129
1130                         port {
1131                                 dsi_in_tcon0: endpoint {
1132                                         remote-endpoint = <&tcon0_out_dsi>;
1133                                 };
1134                         };
1135                 };
1136
1137                 dphy: d-phy@1ca1000 {
1138                         compatible = "allwinner,sun50i-a64-mipi-dphy",
1139                                      "allwinner,sun6i-a31-mipi-dphy";
1140                         reg = <0x01ca1000 0x1000>;
1141                         clocks = <&ccu CLK_BUS_MIPI_DSI>,
1142                                  <&ccu CLK_DSI_DPHY>;
1143                         clock-names = "bus", "mod";
1144                         resets = <&ccu RST_BUS_MIPI_DSI>;
1145                         status = "disabled";
1146                         #phy-cells = <0>;
1147                 };
1148
1149                 deinterlace: deinterlace@1e00000 {
1150                         compatible = "allwinner,sun50i-a64-deinterlace",
1151                                      "allwinner,sun8i-h3-deinterlace";
1152                         reg = <0x01e00000 0x20000>;
1153                         clocks = <&ccu CLK_BUS_DEINTERLACE>,
1154                                  <&ccu CLK_DEINTERLACE>,
1155                                  <&ccu CLK_DRAM_DEINTERLACE>;
1156                         clock-names = "bus", "mod", "ram";
1157                         resets = <&ccu RST_BUS_DEINTERLACE>;
1158                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1159                         interconnects = <&mbus 9>;
1160                         interconnect-names = "dma-mem";
1161                 };
1162
1163                 hdmi: hdmi@1ee0000 {
1164                         compatible = "allwinner,sun50i-a64-dw-hdmi",
1165                                      "allwinner,sun8i-a83t-dw-hdmi";
1166                         reg = <0x01ee0000 0x10000>;
1167                         reg-io-width = <1>;
1168                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1169                         clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
1170                                  <&ccu CLK_HDMI>;
1171                         clock-names = "iahb", "isfr", "tmds";
1172                         resets = <&ccu RST_BUS_HDMI1>;
1173                         reset-names = "ctrl";
1174                         phys = <&hdmi_phy>;
1175                         phy-names = "phy";
1176                         status = "disabled";
1177
1178                         ports {
1179                                 #address-cells = <1>;
1180                                 #size-cells = <0>;
1181
1182                                 hdmi_in: port@0 {
1183                                         reg = <0>;
1184
1185                                         hdmi_in_tcon1: endpoint {
1186                                                 remote-endpoint = <&tcon1_out_hdmi>;
1187                                         };
1188                                 };
1189
1190                                 hdmi_out: port@1 {
1191                                         reg = <1>;
1192                                 };
1193                         };
1194                 };
1195
1196                 hdmi_phy: hdmi-phy@1ef0000 {
1197                         compatible = "allwinner,sun50i-a64-hdmi-phy";
1198                         reg = <0x01ef0000 0x10000>;
1199                         clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
1200                                  <&ccu CLK_PLL_VIDEO0>;
1201                         clock-names = "bus", "mod", "pll-0";
1202                         resets = <&ccu RST_BUS_HDMI0>;
1203                         reset-names = "phy";
1204                         #phy-cells = <0>;
1205                 };
1206
1207                 rtc: rtc@1f00000 {
1208                         compatible = "allwinner,sun50i-a64-rtc",
1209                                      "allwinner,sun8i-h3-rtc";
1210                         reg = <0x01f00000 0x400>;
1211                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1212                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1213                         clock-output-names = "osc32k", "osc32k-out", "iosc";
1214                         clocks = <&osc32k>;
1215                         #clock-cells = <1>;
1216                 };
1217
1218                 r_intc: interrupt-controller@1f00c00 {
1219                         compatible = "allwinner,sun50i-a64-r-intc",
1220                                      "allwinner,sun6i-a31-r-intc";
1221                         interrupt-controller;
1222                         #interrupt-cells = <2>;
1223                         reg = <0x01f00c00 0x400>;
1224                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1225                 };
1226
1227                 r_ccu: clock@1f01400 {
1228                         compatible = "allwinner,sun50i-a64-r-ccu";
1229                         reg = <0x01f01400 0x100>;
1230                         clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
1231                                  <&ccu CLK_PLL_PERIPH0>;
1232                         clock-names = "hosc", "losc", "iosc", "pll-periph";
1233                         #clock-cells = <1>;
1234                         #reset-cells = <1>;
1235                 };
1236
1237                 codec_analog: codec-analog@1f015c0 {
1238                         compatible = "allwinner,sun50i-a64-codec-analog";
1239                         reg = <0x01f015c0 0x4>;
1240                         status = "disabled";
1241                 };
1242
1243                 r_i2c: i2c@1f02400 {
1244                         compatible = "allwinner,sun50i-a64-i2c",
1245                                      "allwinner,sun6i-a31-i2c";
1246                         reg = <0x01f02400 0x400>;
1247                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1248                         clocks = <&r_ccu CLK_APB0_I2C>;
1249                         resets = <&r_ccu RST_APB0_I2C>;
1250                         status = "disabled";
1251                         #address-cells = <1>;
1252                         #size-cells = <0>;
1253                 };
1254
1255                 r_ir: ir@1f02000 {
1256                         compatible = "allwinner,sun50i-a64-ir",
1257                                      "allwinner,sun6i-a31-ir";
1258                         reg = <0x01f02000 0x400>;
1259                         clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
1260                         clock-names = "apb", "ir";
1261                         resets = <&r_ccu RST_APB0_IR>;
1262                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1263                         pinctrl-names = "default";
1264                         pinctrl-0 = <&r_ir_rx_pin>;
1265                         status = "disabled";
1266                 };
1267
1268                 r_pwm: pwm@1f03800 {
1269                         compatible = "allwinner,sun50i-a64-pwm",
1270                                      "allwinner,sun5i-a13-pwm";
1271                         reg = <0x01f03800 0x400>;
1272                         clocks = <&osc24M>;
1273                         pinctrl-names = "default";
1274                         pinctrl-0 = <&r_pwm_pin>;
1275                         #pwm-cells = <3>;
1276                         status = "disabled";
1277                 };
1278
1279                 r_pio: pinctrl@1f02c00 {
1280                         compatible = "allwinner,sun50i-a64-r-pinctrl";
1281                         reg = <0x01f02c00 0x400>;
1282                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1283                         clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
1284                         clock-names = "apb", "hosc", "losc";
1285                         gpio-controller;
1286                         #gpio-cells = <3>;
1287                         interrupt-controller;
1288                         #interrupt-cells = <3>;
1289
1290                         r_i2c_pl89_pins: r-i2c-pl89-pins {
1291                                 pins = "PL8", "PL9";
1292                                 function = "s_i2c";
1293                         };
1294
1295                         r_ir_rx_pin: r-ir-rx-pin {
1296                                 pins = "PL11";
1297                                 function = "s_cir_rx";
1298                         };
1299
1300                         r_pwm_pin: r-pwm-pin {
1301                                 pins = "PL10";
1302                                 function = "s_pwm";
1303                         };
1304
1305                         r_rsb_pins: r-rsb-pins {
1306                                 pins = "PL0", "PL1";
1307                                 function = "s_rsb";
1308                         };
1309                 };
1310
1311                 r_rsb: rsb@1f03400 {
1312                         compatible = "allwinner,sun8i-a23-rsb";
1313                         reg = <0x01f03400 0x400>;
1314                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1315                         clocks = <&r_ccu 6>;
1316                         clock-frequency = <3000000>;
1317                         resets = <&r_ccu 2>;
1318                         pinctrl-names = "default";
1319                         pinctrl-0 = <&r_rsb_pins>;
1320                         status = "disabled";
1321                         #address-cells = <1>;
1322                         #size-cells = <0>;
1323                 };
1324
1325                 wdt0: watchdog@1c20ca0 {
1326                         compatible = "allwinner,sun50i-a64-wdt",
1327                                      "allwinner,sun6i-a31-wdt";
1328                         reg = <0x01c20ca0 0x20>;
1329                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1330                         clocks = <&osc24M>;
1331                 };
1332         };
1333 };