2 * Copyright 2012 Stefan Roese
3 * Stefan Roese <sr@denx.de>
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
10 * a) This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
44 #include <dt-bindings/thermal/thermal.h>
45 #include <dt-bindings/dma/sun4i-a10.h>
46 #include <dt-bindings/clock/sun4i-a10-ccu.h>
47 #include <dt-bindings/reset/sun4i-a10-ccu.h>
52 interrupt-parent = <&intc>;
63 framebuffer-lcd0-hdmi {
64 compatible = "allwinner,simple-framebuffer",
66 allwinner,pipeline = "de_be0-lcd0-hdmi";
67 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
68 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
69 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>;
73 framebuffer-fe0-lcd0-hdmi {
74 compatible = "allwinner,simple-framebuffer",
76 allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
77 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
78 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
79 <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>,
80 <&ccu CLK_TCON0_CH1>, <&ccu CLK_HDMI>,
81 <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
85 framebuffer-fe0-lcd0 {
86 compatible = "allwinner,simple-framebuffer",
88 allwinner,pipeline = "de_fe0-de_be0-lcd0";
89 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>,
90 <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_BE0>,
91 <&ccu CLK_DE_FE0>, <&ccu CLK_TCON0_CH0>,
92 <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
96 framebuffer-fe0-lcd0-tve0 {
97 compatible = "allwinner,simple-framebuffer",
99 allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0";
100 clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>,
101 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
102 <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>,
103 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_TVE0>,
104 <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
110 #address-cells = <1>;
114 compatible = "arm,cortex-a8";
116 clocks = <&ccu CLK_CPU>;
117 clock-latency = <244144>; /* 8 32k periods */
124 #cooling-cells = <2>;
131 polling-delay-passive = <250>;
132 polling-delay = <1000>;
133 thermal-sensors = <&rtp>;
137 trip = <&cpu_alert0>;
138 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
143 cpu_alert0: cpu-alert0 {
145 temperature = <85000>;
152 temperature = <100000>;
161 #address-cells = <1>;
167 compatible = "fixed-clock";
168 clock-frequency = <24000000>;
169 clock-output-names = "osc24M";
174 compatible = "fixed-clock";
175 clock-frequency = <32768>;
176 clock-output-names = "osc32k";
181 compatible = "allwinner,sun4i-a10-display-engine";
182 allwinner,pipelines = <&fe0>, <&fe1>;
187 compatible = "arm,cortex-a8-pmu";
192 #address-cells = <1>;
196 /* Address must be kept in the lower 256 MiBs of DRAM for VE. */
198 compatible = "shared-dma-pool";
200 alloc-ranges = <0x40000000 0x10000000>;
207 compatible = "simple-bus";
208 #address-cells = <1>;
212 system-control@1c00000 {
213 compatible = "allwinner,sun4i-a10-system-control";
214 reg = <0x01c00000 0x30>;
215 #address-cells = <1>;
220 compatible = "mmio-sram";
221 reg = <0x00000000 0xc000>;
222 #address-cells = <1>;
224 ranges = <0 0x00000000 0xc000>;
226 emac_sram: sram-section@8000 {
227 compatible = "allwinner,sun4i-a10-sram-a3-a4";
228 reg = <0x8000 0x4000>;
234 compatible = "mmio-sram";
235 reg = <0x00010000 0x1000>;
236 #address-cells = <1>;
238 ranges = <0 0x00010000 0x1000>;
240 otg_sram: sram-section@0 {
241 compatible = "allwinner,sun4i-a10-sram-d";
242 reg = <0x0000 0x1000>;
247 sram_c: sram@1d00000 {
248 compatible = "mmio-sram";
249 reg = <0x01d00000 0xd0000>;
250 #address-cells = <1>;
252 ranges = <0 0x01d00000 0xd0000>;
254 ve_sram: sram-section@0 {
255 compatible = "allwinner,sun4i-a10-sram-c1";
256 reg = <0x000000 0x80000>;
261 dma: dma-controller@1c02000 {
262 compatible = "allwinner,sun4i-a10-dma";
263 reg = <0x01c02000 0x1000>;
265 clocks = <&ccu CLK_AHB_DMA>;
269 nfc: nand-controller@1c03000 {
270 compatible = "allwinner,sun4i-a10-nand";
271 reg = <0x01c03000 0x1000>;
273 clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
274 clock-names = "ahb", "mod";
275 dmas = <&dma SUN4I_DMA_DEDICATED 3>;
278 #address-cells = <1>;
283 compatible = "allwinner,sun4i-a10-spi";
284 reg = <0x01c05000 0x1000>;
286 clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
287 clock-names = "ahb", "mod";
288 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
289 <&dma SUN4I_DMA_DEDICATED 26>;
290 dma-names = "rx", "tx";
292 #address-cells = <1>;
297 compatible = "allwinner,sun4i-a10-spi";
298 reg = <0x01c06000 0x1000>;
300 clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
301 clock-names = "ahb", "mod";
302 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
303 <&dma SUN4I_DMA_DEDICATED 8>;
304 dma-names = "rx", "tx";
305 pinctrl-names = "default";
306 pinctrl-0 = <&spi1_pins>, <&spi1_cs0_pin>;
308 #address-cells = <1>;
312 emac: ethernet@1c0b000 {
313 compatible = "allwinner,sun4i-a10-emac";
314 reg = <0x01c0b000 0x1000>;
316 clocks = <&ccu CLK_AHB_EMAC>;
317 allwinner,sram = <&emac_sram 1>;
318 pinctrl-names = "default";
319 pinctrl-0 = <&emac_pins>;
324 compatible = "allwinner,sun4i-a10-mdio";
325 reg = <0x01c0b080 0x14>;
327 #address-cells = <1>;
331 tcon0: lcd-controller@1c0c000 {
332 compatible = "allwinner,sun4i-a10-tcon";
333 reg = <0x01c0c000 0x1000>;
335 resets = <&ccu RST_TCON0>;
337 clocks = <&ccu CLK_AHB_LCD0>,
338 <&ccu CLK_TCON0_CH0>,
339 <&ccu CLK_TCON0_CH1>;
343 clock-output-names = "tcon0-pixel-clock";
345 dmas = <&dma SUN4I_DMA_DEDICATED 14>;
348 #address-cells = <1>;
352 #address-cells = <1>;
356 tcon0_in_be0: endpoint@0 {
358 remote-endpoint = <&be0_out_tcon0>;
361 tcon0_in_be1: endpoint@1 {
363 remote-endpoint = <&be1_out_tcon0>;
368 #address-cells = <1>;
372 tcon0_out_hdmi: endpoint@1 {
374 remote-endpoint = <&hdmi_in_tcon0>;
375 allwinner,tcon-channel = <1>;
381 tcon1: lcd-controller@1c0d000 {
382 compatible = "allwinner,sun4i-a10-tcon";
383 reg = <0x01c0d000 0x1000>;
385 resets = <&ccu RST_TCON1>;
387 clocks = <&ccu CLK_AHB_LCD1>,
388 <&ccu CLK_TCON1_CH0>,
389 <&ccu CLK_TCON1_CH1>;
393 clock-output-names = "tcon1-pixel-clock";
395 dmas = <&dma SUN4I_DMA_DEDICATED 15>;
398 #address-cells = <1>;
402 #address-cells = <1>;
406 tcon1_in_be0: endpoint@0 {
408 remote-endpoint = <&be0_out_tcon1>;
411 tcon1_in_be1: endpoint@1 {
413 remote-endpoint = <&be1_out_tcon1>;
418 #address-cells = <1>;
422 tcon1_out_hdmi: endpoint@1 {
424 remote-endpoint = <&hdmi_in_tcon1>;
425 allwinner,tcon-channel = <1>;
431 video-codec@1c0e000 {
432 compatible = "allwinner,sun4i-a10-video-engine";
433 reg = <0x01c0e000 0x1000>;
434 clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
436 clock-names = "ahb", "mod", "ram";
437 resets = <&ccu RST_VE>;
439 allwinner,sram = <&ve_sram 1>;
443 compatible = "allwinner,sun4i-a10-mmc";
444 reg = <0x01c0f000 0x1000>;
445 clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>;
446 clock-names = "ahb", "mmc";
448 pinctrl-names = "default";
449 pinctrl-0 = <&mmc0_pins>;
451 #address-cells = <1>;
456 compatible = "allwinner,sun4i-a10-mmc";
457 reg = <0x01c10000 0x1000>;
458 clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>;
459 clock-names = "ahb", "mmc";
462 #address-cells = <1>;
467 compatible = "allwinner,sun4i-a10-mmc";
468 reg = <0x01c11000 0x1000>;
469 clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>;
470 clock-names = "ahb", "mmc";
473 #address-cells = <1>;
478 compatible = "allwinner,sun4i-a10-mmc";
479 reg = <0x01c12000 0x1000>;
480 clocks = <&ccu CLK_AHB_MMC3>, <&ccu CLK_MMC3>;
481 clock-names = "ahb", "mmc";
484 #address-cells = <1>;
488 usb_otg: usb@1c13000 {
489 compatible = "allwinner,sun4i-a10-musb";
490 reg = <0x01c13000 0x0400>;
491 clocks = <&ccu CLK_AHB_OTG>;
493 interrupt-names = "mc";
496 extcon = <&usbphy 0>;
497 allwinner,sram = <&otg_sram 1>;
502 usbphy: phy@1c13400 {
504 compatible = "allwinner,sun4i-a10-usb-phy";
505 reg = <0x01c13400 0x10>, <0x01c14800 0x4>, <0x01c1c800 0x4>;
506 reg-names = "phy_ctrl", "pmu1", "pmu2";
507 clocks = <&ccu CLK_USB_PHY>;
508 clock-names = "usb_phy";
509 resets = <&ccu RST_USB_PHY0>,
512 reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
517 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
518 reg = <0x01c14000 0x100>;
520 clocks = <&ccu CLK_AHB_EHCI0>;
527 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
528 reg = <0x01c14400 0x100>;
530 clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>;
536 crypto: crypto-engine@1c15000 {
537 compatible = "allwinner,sun4i-a10-crypto";
538 reg = <0x01c15000 0x1000>;
540 clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
541 clock-names = "ahb", "mod";
545 compatible = "allwinner,sun4i-a10-hdmi";
546 reg = <0x01c16000 0x1000>;
548 clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>,
549 <&ccu CLK_PLL_VIDEO0_2X>,
550 <&ccu CLK_PLL_VIDEO1_2X>;
551 clock-names = "ahb", "mod", "pll-0", "pll-1";
552 dmas = <&dma SUN4I_DMA_NORMAL 16>,
553 <&dma SUN4I_DMA_NORMAL 16>,
554 <&dma SUN4I_DMA_DEDICATED 24>;
555 dma-names = "ddc-tx", "ddc-rx", "audio-tx";
559 #address-cells = <1>;
563 #address-cells = <1>;
567 hdmi_in_tcon0: endpoint@0 {
569 remote-endpoint = <&tcon0_out_hdmi>;
572 hdmi_in_tcon1: endpoint@1 {
574 remote-endpoint = <&tcon1_out_hdmi>;
585 compatible = "allwinner,sun4i-a10-spi";
586 reg = <0x01c17000 0x1000>;
588 clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
589 clock-names = "ahb", "mod";
590 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
591 <&dma SUN4I_DMA_DEDICATED 28>;
592 dma-names = "rx", "tx";
594 #address-cells = <1>;
599 compatible = "allwinner,sun4i-a10-ahci";
600 reg = <0x01c18000 0x1000>;
602 clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>;
607 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
608 reg = <0x01c1c000 0x100>;
610 clocks = <&ccu CLK_AHB_EHCI1>;
617 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
618 reg = <0x01c1c400 0x100>;
620 clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>;
627 compatible = "allwinner,sun4i-a10-csi1";
628 reg = <0x01c1d000 0x1000>;
630 clocks = <&ccu CLK_AHB_CSI1>, <&ccu CLK_DRAM_CSI1>;
631 clock-names = "bus", "ram";
632 resets = <&ccu RST_CSI1>;
637 compatible = "allwinner,sun4i-a10-spi";
638 reg = <0x01c1f000 0x1000>;
640 clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>;
641 clock-names = "ahb", "mod";
642 dmas = <&dma SUN4I_DMA_DEDICATED 31>,
643 <&dma SUN4I_DMA_DEDICATED 30>;
644 dma-names = "rx", "tx";
646 #address-cells = <1>;
651 compatible = "allwinner,sun4i-a10-ccu";
652 reg = <0x01c20000 0x400>;
653 clocks = <&osc24M>, <&osc32k>;
654 clock-names = "hosc", "losc";
659 intc: interrupt-controller@1c20400 {
660 compatible = "allwinner,sun4i-a10-ic";
661 reg = <0x01c20400 0x400>;
662 interrupt-controller;
663 #interrupt-cells = <1>;
666 pio: pinctrl@1c20800 {
667 compatible = "allwinner,sun4i-a10-pinctrl";
668 reg = <0x01c20800 0x400>;
670 clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
671 clock-names = "apb", "hosc", "losc";
673 interrupt-controller;
674 #interrupt-cells = <3>;
677 can0_ph_pins: can0-ph-pins {
678 pins = "PH20", "PH21";
683 csi1_8bits_pg_pins: csi1-8bits-pg-pins {
684 pins = "PG0", "PG2", "PG3", "PG4", "PG5",
685 "PG6", "PG7", "PG8", "PG9", "PG10",
691 csi1_24bits_ph_pins: csi1-24bits-ph-pins {
692 pins = "PH0", "PH1", "PH2", "PH3", "PH4",
693 "PH5", "PH6", "PH7", "PH8", "PH9",
694 "PH10", "PH11", "PH12", "PH13", "PH14",
695 "PH15", "PH16", "PH17", "PH18", "PH19",
696 "PH20", "PH21", "PH22", "PH23", "PH24",
697 "PH25", "PH26", "PH27";
702 csi1_clk_pg_pin: csi1-clk-pg-pin {
707 emac_pins: emac0-pins {
708 pins = "PA0", "PA1", "PA2",
709 "PA3", "PA4", "PA5", "PA6",
710 "PA7", "PA8", "PA9", "PA10",
711 "PA11", "PA12", "PA13", "PA14",
716 i2c0_pins: i2c0-pins {
721 i2c1_pins: i2c1-pins {
722 pins = "PB18", "PB19";
726 i2c2_pins: i2c2-pins {
727 pins = "PB20", "PB21";
731 ir0_rx_pins: ir0-rx-pin {
736 ir0_tx_pins: ir0-tx-pin {
741 ir1_rx_pins: ir1-rx-pin {
746 ir1_tx_pins: ir1-tx-pin {
751 mmc0_pins: mmc0-pins {
752 pins = "PF0", "PF1", "PF2",
755 drive-strength = <30>;
759 ps2_ch0_pins: ps2-ch0-pins {
760 pins = "PI20", "PI21";
764 ps2_ch1_ph_pins: ps2-ch1-ph-pins {
765 pins = "PH12", "PH13";
779 spdif_tx_pin: spdif-tx-pin {
785 spi0_pi_pins: spi0-pi-pins {
786 pins = "PI11", "PI12", "PI13";
790 spi0_cs0_pi_pin: spi0-cs0-pi-pin {
795 spi1_pins: spi1-pins {
796 pins = "PI17", "PI18", "PI19";
800 spi1_cs0_pin: spi1-cs0-pin {
805 spi2_pb_pins: spi2-pb-pins {
806 pins = "PB15", "PB16", "PB17";
810 spi2_pc_pins: spi2-pc-pins {
811 pins = "PC20", "PC21", "PC22";
815 spi2_cs0_pb_pin: spi2-cs0-pb-pin {
820 spi2_cs0_pc_pins: spi2-cs0-pc-pin {
825 uart0_pb_pins: uart0-pb-pins {
826 pins = "PB22", "PB23";
830 uart0_pf_pins: uart0-pf-pins {
835 uart1_pins: uart1-pins {
836 pins = "PA10", "PA11";
842 compatible = "allwinner,sun4i-a10-timer";
843 reg = <0x01c20c00 0x90>;
853 wdt: watchdog@1c20c90 {
854 compatible = "allwinner,sun4i-a10-wdt";
855 reg = <0x01c20c90 0x10>;
861 compatible = "allwinner,sun4i-a10-rtc";
862 reg = <0x01c20d00 0x20>;
867 compatible = "allwinner,sun4i-a10-pwm";
868 reg = <0x01c20e00 0xc>;
874 spdif: spdif@1c21000 {
875 #sound-dai-cells = <0>;
876 compatible = "allwinner,sun4i-a10-spdif";
877 reg = <0x01c21000 0x400>;
879 clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>;
880 clock-names = "apb", "spdif";
881 dmas = <&dma SUN4I_DMA_NORMAL 2>,
882 <&dma SUN4I_DMA_NORMAL 2>;
883 dma-names = "rx", "tx";
888 compatible = "allwinner,sun4i-a10-ir";
889 clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>;
890 clock-names = "apb", "ir";
892 reg = <0x01c21800 0x40>;
897 compatible = "allwinner,sun4i-a10-ir";
898 clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>;
899 clock-names = "apb", "ir";
901 reg = <0x01c21c00 0x40>;
906 #sound-dai-cells = <0>;
907 compatible = "allwinner,sun4i-a10-i2s";
908 reg = <0x01c22400 0x400>;
910 clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>;
911 clock-names = "apb", "mod";
912 dmas = <&dma SUN4I_DMA_NORMAL 3>,
913 <&dma SUN4I_DMA_NORMAL 3>;
914 dma-names = "rx", "tx";
918 lradc: lradc@1c22800 {
919 compatible = "allwinner,sun4i-a10-lradc-keys";
920 reg = <0x01c22800 0x100>;
925 codec: codec@1c22c00 {
926 #sound-dai-cells = <0>;
927 compatible = "allwinner,sun4i-a10-codec";
928 reg = <0x01c22c00 0x40>;
930 clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
931 clock-names = "apb", "codec";
932 dmas = <&dma SUN4I_DMA_NORMAL 19>,
933 <&dma SUN4I_DMA_NORMAL 19>;
934 dma-names = "rx", "tx";
938 sid: eeprom@1c23800 {
939 compatible = "allwinner,sun4i-a10-sid";
940 reg = <0x01c23800 0x10>;
944 compatible = "allwinner,sun4i-a10-ts";
945 reg = <0x01c25000 0x100>;
947 #thermal-sensor-cells = <0>;
950 uart0: serial@1c28000 {
951 compatible = "snps,dw-apb-uart";
952 reg = <0x01c28000 0x400>;
956 clocks = <&ccu CLK_APB1_UART0>;
960 uart1: serial@1c28400 {
961 compatible = "snps,dw-apb-uart";
962 reg = <0x01c28400 0x400>;
966 clocks = <&ccu CLK_APB1_UART1>;
970 uart2: serial@1c28800 {
971 compatible = "snps,dw-apb-uart";
972 reg = <0x01c28800 0x400>;
976 clocks = <&ccu CLK_APB1_UART2>;
980 uart3: serial@1c28c00 {
981 compatible = "snps,dw-apb-uart";
982 reg = <0x01c28c00 0x400>;
986 clocks = <&ccu CLK_APB1_UART3>;
990 uart4: serial@1c29000 {
991 compatible = "snps,dw-apb-uart";
992 reg = <0x01c29000 0x400>;
996 clocks = <&ccu CLK_APB1_UART4>;
1000 uart5: serial@1c29400 {
1001 compatible = "snps,dw-apb-uart";
1002 reg = <0x01c29400 0x400>;
1006 clocks = <&ccu CLK_APB1_UART5>;
1007 status = "disabled";
1010 uart6: serial@1c29800 {
1011 compatible = "snps,dw-apb-uart";
1012 reg = <0x01c29800 0x400>;
1016 clocks = <&ccu CLK_APB1_UART6>;
1017 status = "disabled";
1020 uart7: serial@1c29c00 {
1021 compatible = "snps,dw-apb-uart";
1022 reg = <0x01c29c00 0x400>;
1026 clocks = <&ccu CLK_APB1_UART7>;
1027 status = "disabled";
1031 compatible = "allwinner,sun4i-a10-ps2";
1032 reg = <0x01c2a000 0x400>;
1034 clocks = <&ccu CLK_APB1_PS20>;
1035 status = "disabled";
1039 compatible = "allwinner,sun4i-a10-ps2";
1040 reg = <0x01c2a400 0x400>;
1042 clocks = <&ccu CLK_APB1_PS21>;
1043 status = "disabled";
1047 compatible = "allwinner,sun4i-a10-i2c";
1048 reg = <0x01c2ac00 0x400>;
1050 clocks = <&ccu CLK_APB1_I2C0>;
1051 pinctrl-names = "default";
1052 pinctrl-0 = <&i2c0_pins>;
1053 status = "disabled";
1054 #address-cells = <1>;
1059 compatible = "allwinner,sun4i-a10-i2c";
1060 reg = <0x01c2b000 0x400>;
1062 clocks = <&ccu CLK_APB1_I2C1>;
1063 pinctrl-names = "default";
1064 pinctrl-0 = <&i2c1_pins>;
1065 status = "disabled";
1066 #address-cells = <1>;
1071 compatible = "allwinner,sun4i-a10-i2c";
1072 reg = <0x01c2b400 0x400>;
1074 clocks = <&ccu CLK_APB1_I2C2>;
1075 pinctrl-names = "default";
1076 pinctrl-0 = <&i2c2_pins>;
1077 status = "disabled";
1078 #address-cells = <1>;
1083 compatible = "allwinner,sun4i-a10-can";
1084 reg = <0x01c2bc00 0x400>;
1086 clocks = <&ccu CLK_APB1_CAN>;
1087 status = "disabled";
1091 compatible = "allwinner,sun4i-a10-mali", "arm,mali-400";
1092 reg = <0x01c40000 0x10000>;
1098 interrupt-names = "gp",
1103 clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>;
1104 clock-names = "bus", "core";
1105 resets = <&ccu RST_GPU>;
1107 assigned-clocks = <&ccu CLK_GPU>;
1108 assigned-clock-rates = <384000000>;
1111 fe0: display-frontend@1e00000 {
1112 compatible = "allwinner,sun4i-a10-display-frontend";
1113 reg = <0x01e00000 0x20000>;
1115 clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>,
1116 <&ccu CLK_DRAM_DE_FE0>;
1117 clock-names = "ahb", "mod",
1119 resets = <&ccu RST_DE_FE0>;
1122 #address-cells = <1>;
1126 #address-cells = <1>;
1130 fe0_out_be0: endpoint@0 {
1132 remote-endpoint = <&be0_in_fe0>;
1135 fe0_out_be1: endpoint@1 {
1137 remote-endpoint = <&be1_in_fe0>;
1143 fe1: display-frontend@1e20000 {
1144 compatible = "allwinner,sun4i-a10-display-frontend";
1145 reg = <0x01e20000 0x20000>;
1147 clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>,
1148 <&ccu CLK_DRAM_DE_FE1>;
1149 clock-names = "ahb", "mod",
1151 resets = <&ccu RST_DE_FE1>;
1154 #address-cells = <1>;
1158 #address-cells = <1>;
1162 fe1_out_be0: endpoint@0 {
1164 remote-endpoint = <&be0_in_fe1>;
1167 fe1_out_be1: endpoint@1 {
1169 remote-endpoint = <&be1_in_fe1>;
1175 be1: display-backend@1e40000 {
1176 compatible = "allwinner,sun4i-a10-display-backend";
1177 reg = <0x01e40000 0x10000>;
1179 clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>,
1180 <&ccu CLK_DRAM_DE_BE1>;
1181 clock-names = "ahb", "mod",
1183 resets = <&ccu RST_DE_BE1>;
1186 #address-cells = <1>;
1190 #address-cells = <1>;
1194 be1_in_fe0: endpoint@0 {
1196 remote-endpoint = <&fe0_out_be1>;
1199 be1_in_fe1: endpoint@1 {
1201 remote-endpoint = <&fe1_out_be1>;
1206 #address-cells = <1>;
1210 be1_out_tcon0: endpoint@0 {
1212 remote-endpoint = <&tcon0_in_be1>;
1215 be1_out_tcon1: endpoint@1 {
1217 remote-endpoint = <&tcon1_in_be1>;
1223 be0: display-backend@1e60000 {
1224 compatible = "allwinner,sun4i-a10-display-backend";
1225 reg = <0x01e60000 0x10000>;
1227 clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
1228 <&ccu CLK_DRAM_DE_BE0>;
1229 clock-names = "ahb", "mod",
1231 resets = <&ccu RST_DE_BE0>;
1234 #address-cells = <1>;
1238 #address-cells = <1>;
1242 be0_in_fe0: endpoint@0 {
1244 remote-endpoint = <&fe0_out_be0>;
1247 be0_in_fe1: endpoint@1 {
1249 remote-endpoint = <&fe1_out_be0>;
1254 #address-cells = <1>;
1258 be0_out_tcon0: endpoint@0 {
1260 remote-endpoint = <&tcon0_in_be0>;
1263 be0_out_tcon1: endpoint@1 {
1265 remote-endpoint = <&tcon1_in_be0>;