arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
   2 /*
   3  * Copyright : STMicroelectronics 2018
   4  *
   5  * Copyright (C) Linaro Ltd 2019 - All Rights Reserved
   6  * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
   7  * Copyright (C) 2020 Marek Vasut <marex@denx.de>
   8  */
   9
  10 #include <dt-bindings/clock/stm32mp1-clksrc.h>
  11 #include "stm32mp15-u-boot.dtsi"
  12 #include "stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi"
  13 #include "stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi"
  14 #include "stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi"
  15
  16 / {
  17         bootph-all;
  18
  19         aliases {
  20                 eeprom0 = &eeprom0;
  21         };
  22
  23         config {
  24                 dh,ddr3-coding-gpios = <&gpiog 0 0>, <&gpiog 1 0>;
  25                 dh,som-coding-gpios = <&gpioz 7 0>, <&gpiof 3 0>;
  26         };
  27 };
  28
  29 &flash0 {
  30         bootph-pre-ram;
  31
  32         partitions {
  33                 compatible = "fixed-partitions";
  34                 #address-cells = <1>;
  35                 #size-cells = <1>;
  36
  37                 partition@0 {
  38                         label = "fsbl1";
  39                         reg = <0x00000000 0x00040000>;
  40                 };
  41                 partition@40000 {
  42                         label = "fsbl2";
  43                         reg = <0x00040000 0x00040000>;
  44                 };
  45                 partition@500000 {
  46                         label = "uboot";
  47                         reg = <0x00080000 0x00160000>;
  48                 };
  49                 partition@900000 {
  50                         label = "env1";
  51                         reg = <0x001E0000 0x00010000>;
  52                 };
  53                 partition@980000 {
  54                         label = "env2";
  55                         reg = <0x001F0000 0x00010000>;
  56                 };
  57         };
  58 };
  59
  60 &i2c4 {
  61         bootph-all;
  62         bootph-pre-ram;
  63
  64         eeprom0: eeprom@53 {
  65         };
  66 };
  67
  68 &i2c4_pins_a {
  69         bootph-all;
  70         pins {
  71                 bootph-all;
  72         };
  73 };
  74
  75 &pmic {
  76         bootph-all;
  77         bootph-pre-ram;
  78
  79         regulators {
  80                 bootph-pre-ram;
  81         };
  82 };
  83
  84 &pwr_regulators {
  85         bootph-pre-ram;
  86 };
  87
  88 &qspi {
  89         bootph-pre-ram;
  90 };
  91
  92 &qspi_clk_pins_a {
  93         bootph-pre-ram;
  94         pins {
  95                 bootph-pre-ram;
  96         };
  97 };
  98
  99 &qspi_bk1_pins_a {
 100         bootph-pre-ram;
 101         pins1 {
 102                 bootph-pre-ram;
 103         };
 104         pins2 {
 105                 bootph-pre-ram;
 106         };
 107 };
 108
 109 &rcc {
 110         st,clksrc = <
 111                 CLK_MPU_PLL1P
 112                 CLK_AXI_PLL2P
 113                 CLK_MCU_PLL3P
 114                 CLK_PLL12_HSE
 115                 CLK_PLL3_HSE
 116                 CLK_PLL4_HSE
 117                 CLK_RTC_LSE
 118                 CLK_MCO1_DISABLED
 119                 CLK_MCO2_DISABLED
 120         >;
 121
 122         st,clkdiv = <
 123                 1 /*MPU*/
 124                 0 /*AXI*/
 125                 0 /*MCU*/
 126                 1 /*APB1*/
 127                 1 /*APB2*/
 128                 1 /*APB3*/
 129                 1 /*APB4*/
 130                 2 /*APB5*/
 131                 23 /*RTC*/
 132                 0 /*MCO1*/
 133                 0 /*MCO2*/
 134         >;
 135
 136         st,pkcs = <
 137                 CLK_CKPER_HSE
 138                 CLK_FMC_ACLK
 139                 CLK_QSPI_ACLK
 140                 CLK_ETH_DISABLED
 141                 CLK_SDMMC12_PLL4P
 142                 CLK_DSI_DSIPLL
 143                 CLK_STGEN_HSE
 144                 CLK_USBPHY_HSE
 145                 CLK_SPI2S1_PLL3Q
 146                 CLK_SPI2S23_PLL3Q
 147                 CLK_SPI45_HSI
 148                 CLK_SPI6_HSI
 149                 CLK_I2C46_HSI
 150                 CLK_SDMMC3_PLL4P
 151                 CLK_USBO_USBPHY
 152                 CLK_ADC_CKPER
 153                 CLK_CEC_LSE
 154                 CLK_I2C12_HSI
 155                 CLK_I2C35_HSI
 156                 CLK_UART1_HSI
 157                 CLK_UART24_HSI
 158                 CLK_UART35_HSI
 159                 CLK_UART6_HSI
 160                 CLK_UART78_HSI
 161                 CLK_SPDIF_PLL4P
 162                 CLK_FDCAN_PLL4R
 163                 CLK_SAI1_PLL3Q
 164                 CLK_SAI2_PLL3Q
 165                 CLK_SAI3_PLL3Q
 166                 CLK_SAI4_PLL3Q
 167                 CLK_RNG1_LSI
 168                 CLK_RNG2_LSI
 169                 CLK_LPTIM1_PCLK1
 170                 CLK_LPTIM23_PCLK3
 171                 CLK_LPTIM45_LSE
 172         >;
 173
 174         /*
 175          * cfg = < DIVM1 DIVN P Q R PQR(p,q,r) >;
 176          * frac = < f >;
 177          *
 178          * PRQ(p,q,r) ... for p,q,r: 0-output disabled / 1-output enabled
 179          * DIVN ... actually multiplier, but RCC_PLL1CFGR1 calls the field DIVN
 180          * m ... for PLL1,2: m=2 ; for PLL3,4: m=1
 181          * XTAL = 24 MHz
 182          *
 183          * VCO = ( XTAL / (DIVM1 + 1) ) * m * ( DIVN + 1 + ( f / 8192 ) )
 184          *   P = VCO / (P + 1)
 185          *   Q = VCO / (Q + 1)
 186          *   R = VCO / (R + 1)
 187          */
 188
 189         /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
 190         pll2: st,pll@1 {
 191                 compatible = "st,stm32mp1-pll";
 192                 reg = <1>;
 193                 cfg = < 2 65 1 0 0 PQR(1,1,1) >;
 194                 frac = < 0x1400 >;
 195                 bootph-all;
 196         };
 197
 198         /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
 199         pll3: st,pll@2 {
 200                 compatible = "st,stm32mp1-pll";
 201                 reg = <2>;
 202                 cfg = < 1 33 1 16 36 PQR(1,1,1) >;
 203                 frac = < 0x1a04 >;
 204                 bootph-all;
 205         };
 206
 207         /* VCO = 594.0 MHz => P = 99, Q = 74, R = 99 */
 208         pll4: st,pll@3 {
 209                 compatible = "st,stm32mp1-pll";
 210                 reg = <3>;
 211                 cfg = < 3 98 5 7 5 PQR(1,1,1) >;
 212                 bootph-all;
 213         };
 214 };
 215
 216 &reg11 {
 217         bootph-pre-ram;
 218 };
 219
 220 &reg18 {
 221         bootph-pre-ram;
 222 };
 223
 224 &usb33 {
 225         bootph-pre-ram;
 226 };
 227
 228 &usbotg_hs_pins_a {
 229         bootph-pre-ram;
 230 };
 231
 232 &usbotg_hs {
 233         bootph-pre-ram;
 234 };
 235
 236 &usbphyc {
 237         bootph-pre-ram;
 238 };
 239
 240 &usbphyc_port0 {
 241         bootph-pre-ram;
 242 };
 243
 244 &usbphyc_port1 {
 245         bootph-pre-ram;
 246 };
 247
 248 &vdd_usb {
 249         bootph-pre-ram;
 250 };