arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
   2 /*
   3  * Copyright : STMicroelectronics 2018
   4  *
   5  * Copyright (C) Linaro Ltd 2019 - All Rights Reserved
   6  * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
   7  * Copyright (C) 2020 Marek Vasut <marex@denx.de>
   8  */
   9
  10 #include <dt-bindings/clock/stm32mp1-clksrc.h>
  11 #include "stm32mp15-u-boot.dtsi"
  12 #include "stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi"
  13 #include "stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi"
  14 #include "stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi"
  15
  16 / {
  17         u-boot,dm-pre-reloc;
  18         config {
  19                 dh,ddr3-coding-gpios = <&gpiog 0 0>, <&gpiog 1 0>;
  20                 dh,som-coding-gpios = <&gpioz 7 0>, <&gpiof 3 0>;
  21         };
  22 };
  23
  24 &flash0 {
  25         u-boot,dm-spl;
  26 };
  27
  28 &gpiof {
  29         snor-nwp {
  30                 gpio-hog;
  31                 gpios = <7 0>;
  32                 output-high;
  33                 line-name = "spi-nor-nwp";
  34         };
  35 };
  36
  37 &i2c4 {
  38         u-boot,dm-pre-reloc;
  39 };
  40
  41 &i2c4_pins_a {
  42         u-boot,dm-pre-reloc;
  43         pins {
  44                 u-boot,dm-pre-reloc;
  45         };
  46 };
  47
  48 &pmic {
  49         u-boot,dm-pre-reloc;
  50 };
  51
  52 &qspi {
  53         u-boot,dm-spl;
  54 };
  55
  56 &qspi_clk_pins_a {
  57         u-boot,dm-spl;
  58         pins {
  59                 u-boot,dm-spl;
  60         };
  61 };
  62
  63 &qspi_bk1_pins_a {
  64         u-boot,dm-spl;
  65         pins1 {
  66                 u-boot,dm-spl;
  67         };
  68         pins2 {
  69                 u-boot,dm-spl;
  70         };
  71 };
  72
  73 &rcc {
  74         st,clksrc = <
  75                 CLK_MPU_PLL1P
  76                 CLK_AXI_PLL2P
  77                 CLK_MCU_PLL3P
  78                 CLK_PLL12_HSE
  79                 CLK_PLL3_HSE
  80                 CLK_PLL4_HSE
  81                 CLK_RTC_LSE
  82                 CLK_MCO1_DISABLED
  83                 CLK_MCO2_DISABLED
  84         >;
  85
  86         st,clkdiv = <
  87                 1 /*MPU*/
  88                 0 /*AXI*/
  89                 0 /*MCU*/
  90                 1 /*APB1*/
  91                 1 /*APB2*/
  92                 1 /*APB3*/
  93                 1 /*APB4*/
  94                 2 /*APB5*/
  95                 23 /*RTC*/
  96                 0 /*MCO1*/
  97                 0 /*MCO2*/
  98         >;
  99
 100         st,pkcs = <
 101                 CLK_CKPER_HSE
 102                 CLK_FMC_ACLK
 103                 CLK_QSPI_ACLK
 104                 CLK_ETH_DISABLED
 105                 CLK_SDMMC12_PLL4P
 106                 CLK_DSI_DSIPLL
 107                 CLK_STGEN_HSE
 108                 CLK_USBPHY_HSE
 109                 CLK_SPI2S1_PLL3Q
 110                 CLK_SPI2S23_PLL3Q
 111                 CLK_SPI45_HSI
 112                 CLK_SPI6_HSI
 113                 CLK_I2C46_HSI
 114                 CLK_SDMMC3_PLL4P
 115                 CLK_USBO_USBPHY
 116                 CLK_ADC_CKPER
 117                 CLK_CEC_LSE
 118                 CLK_I2C12_HSI
 119                 CLK_I2C35_HSI
 120                 CLK_UART1_HSI
 121                 CLK_UART24_HSI
 122                 CLK_UART35_HSI
 123                 CLK_UART6_HSI
 124                 CLK_UART78_HSI
 125                 CLK_SPDIF_PLL4P
 126                 CLK_FDCAN_PLL4R
 127                 CLK_SAI1_PLL3Q
 128                 CLK_SAI2_PLL3Q
 129                 CLK_SAI3_PLL3Q
 130                 CLK_SAI4_PLL3Q
 131                 CLK_RNG1_LSI
 132                 CLK_RNG2_LSI
 133                 CLK_LPTIM1_PCLK1
 134                 CLK_LPTIM23_PCLK3
 135                 CLK_LPTIM45_LSE
 136         >;
 137
 138         /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
 139         pll2: st,pll@1 {
 140                 compatible = "st,stm32mp1-pll";
 141                 reg = <1>;
 142                 cfg = < 2 65 1 0 0 PQR(1,1,1) >;
 143                 frac = < 0x1400 >;
 144                 u-boot,dm-pre-reloc;
 145         };
 146
 147         /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
 148         pll3: st,pll@2 {
 149                 compatible = "st,stm32mp1-pll";
 150                 reg = <2>;
 151                 cfg = < 1 33 1 16 36 PQR(1,1,1) >;
 152                 frac = < 0x1a04 >;
 153                 u-boot,dm-pre-reloc;
 154         };
 155
 156         /* VCO = 600.0 MHz => P = 99, Q = 74, R = 99 */
 157         pll4: st,pll@3 {
 158                 compatible = "st,stm32mp1-pll";
 159                 reg = <3>;
 160                 cfg = < 3 98 5 7 5 PQR(1,1,1) >;
 161                 u-boot,dm-pre-reloc;
 162         };
 163 };