arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
   2 /*
   3  * Copyright : STMicroelectronics 2018
   4  *
   5  * Copyright (C) Linaro Ltd 2019 - All Rights Reserved
   6  * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
   7  * Copyright (C) 2020 Marek Vasut <marex@denx.de>
   8  */
   9
  10 #include <dt-bindings/clock/stm32mp1-clksrc.h>
  11 #include "stm32mp15-u-boot.dtsi"
  12 #include "stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi"
  13 #include "stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi"
  14 #include "stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi"
  15
  16 / {
  17         u-boot,dm-pre-reloc;
  18         config {
  19                 dh,ddr3-coding-gpios = <&gpiog 0 0>, <&gpiog 1 0>;
  20                 dh,som-coding-gpios = <&gpioz 7 0>, <&gpiof 3 0>;
  21         };
  22 };
  23
  24 &flash0 {
  25         u-boot,dm-spl;
  26 };
  27
  28 &i2c4 {
  29         u-boot,dm-pre-reloc;
  30         u-boot,dm-spl;
  31 };
  32
  33 &i2c4_pins_a {
  34         u-boot,dm-pre-reloc;
  35         pins {
  36                 u-boot,dm-pre-reloc;
  37         };
  38 };
  39
  40 &pmic {
  41         u-boot,dm-pre-reloc;
  42         u-boot,dm-spl;
  43
  44         regulators {
  45                 u-boot,dm-spl;
  46         };
  47 };
  48
  49 &pwr_regulators {
  50         u-boot,dm-spl;
  51 };
  52
  53 &qspi {
  54         u-boot,dm-spl;
  55 };
  56
  57 &qspi_clk_pins_a {
  58         u-boot,dm-spl;
  59         pins {
  60                 u-boot,dm-spl;
  61         };
  62 };
  63
  64 &qspi_bk1_pins_a {
  65         u-boot,dm-spl;
  66         pins1 {
  67                 u-boot,dm-spl;
  68         };
  69         pins2 {
  70                 u-boot,dm-spl;
  71         };
  72 };
  73
  74 &rcc {
  75         st,clksrc = <
  76                 CLK_MPU_PLL1P
  77                 CLK_AXI_PLL2P
  78                 CLK_MCU_PLL3P
  79                 CLK_PLL12_HSE
  80                 CLK_PLL3_HSE
  81                 CLK_PLL4_HSE
  82                 CLK_RTC_LSE
  83                 CLK_MCO1_DISABLED
  84                 CLK_MCO2_DISABLED
  85         >;
  86
  87         st,clkdiv = <
  88                 1 /*MPU*/
  89                 0 /*AXI*/
  90                 0 /*MCU*/
  91                 1 /*APB1*/
  92                 1 /*APB2*/
  93                 1 /*APB3*/
  94                 1 /*APB4*/
  95                 2 /*APB5*/
  96                 23 /*RTC*/
  97                 0 /*MCO1*/
  98                 0 /*MCO2*/
  99         >;
 100
 101         st,pkcs = <
 102                 CLK_CKPER_HSE
 103                 CLK_FMC_ACLK
 104                 CLK_QSPI_ACLK
 105                 CLK_ETH_DISABLED
 106                 CLK_SDMMC12_PLL4P
 107                 CLK_DSI_DSIPLL
 108                 CLK_STGEN_HSE
 109                 CLK_USBPHY_HSE
 110                 CLK_SPI2S1_PLL3Q
 111                 CLK_SPI2S23_PLL3Q
 112                 CLK_SPI45_HSI
 113                 CLK_SPI6_HSI
 114                 CLK_I2C46_HSI
 115                 CLK_SDMMC3_PLL4P
 116                 CLK_USBO_USBPHY
 117                 CLK_ADC_CKPER
 118                 CLK_CEC_LSE
 119                 CLK_I2C12_HSI
 120                 CLK_I2C35_HSI
 121                 CLK_UART1_HSI
 122                 CLK_UART24_HSI
 123                 CLK_UART35_HSI
 124                 CLK_UART6_HSI
 125                 CLK_UART78_HSI
 126                 CLK_SPDIF_PLL4P
 127                 CLK_FDCAN_PLL4R
 128                 CLK_SAI1_PLL3Q
 129                 CLK_SAI2_PLL3Q
 130                 CLK_SAI3_PLL3Q
 131                 CLK_SAI4_PLL3Q
 132                 CLK_RNG1_LSI
 133                 CLK_RNG2_LSI
 134                 CLK_LPTIM1_PCLK1
 135                 CLK_LPTIM23_PCLK3
 136                 CLK_LPTIM45_LSE
 137         >;
 138
 139         /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
 140         pll2: st,pll@1 {
 141                 compatible = "st,stm32mp1-pll";
 142                 reg = <1>;
 143                 cfg = < 2 65 1 0 0 PQR(1,1,1) >;
 144                 frac = < 0x1400 >;
 145                 u-boot,dm-pre-reloc;
 146         };
 147
 148         /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
 149         pll3: st,pll@2 {
 150                 compatible = "st,stm32mp1-pll";
 151                 reg = <2>;
 152                 cfg = < 1 33 1 16 36 PQR(1,1,1) >;
 153                 frac = < 0x1a04 >;
 154                 u-boot,dm-pre-reloc;
 155         };
 156
 157         /* VCO = 600.0 MHz => P = 99, Q = 74, R = 99 */
 158         pll4: st,pll@3 {
 159                 compatible = "st,stm32mp1-pll";
 160                 reg = <3>;
 161                 cfg = < 3 98 5 7 5 PQR(1,1,1) >;
 162                 u-boot,dm-pre-reloc;
 163         };
 164 };
 165
 166 &reg11 {
 167         u-boot,dm-spl;
 168 };
 169
 170 &reg18 {
 171         u-boot,dm-spl;
 172 };
 173
 174 &usbotg_hs {
 175         u-boot,dm-spl;
 176 };
 177
 178 &usbphyc {
 179         u-boot,dm-spl;
 180 };
 181
 182 &usbphyc_port0 {
 183         u-boot,dm-spl;
 184 };
 185
 186 &usbphyc_port1 {
 187         u-boot,dm-spl;
 188 };
 189
 190 &vdd_io {
 191         u-boot,dm-spl;
 192 };
 193
 194 &vdd_usb {
 195         u-boot,dm-spl;
 196 };