arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
   2 /*
   3  * Copyright : STMicroelectronics 2018
   4  *
   5  * Copyright (C) Linaro Ltd 2019 - All Rights Reserved
   6  * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
   7  * Copyright (C) 2020 Marek Vasut <marex@denx.de>
   8  */
   9
  10 #include <dt-bindings/clock/stm32mp1-clksrc.h>
  11 #include "stm32mp15-u-boot.dtsi"
  12 #include "stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi"
  13 #include "stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi"
  14 #include "stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi"
  15
  16 / {
  17         u-boot,dm-pre-reloc;
  18         config {
  19                 dh,ddr3-coding-gpios = <&gpiog 0 0>, <&gpiog 1 0>;
  20                 dh,som-coding-gpios = <&gpioz 7 0>, <&gpiof 3 0>;
  21         };
  22 };
  23
  24 &flash0 {
  25         u-boot,dm-spl;
  26 };
  27
  28 &i2c4 {
  29         u-boot,dm-pre-reloc;
  30 };
  31
  32 &i2c4_pins_a {
  33         u-boot,dm-pre-reloc;
  34         pins {
  35                 u-boot,dm-pre-reloc;
  36         };
  37 };
  38
  39 &pmic {
  40         u-boot,dm-pre-reloc;
  41 };
  42
  43 &qspi {
  44         u-boot,dm-spl;
  45 };
  46
  47 &qspi_clk_pins_a {
  48         u-boot,dm-spl;
  49         pins {
  50                 u-boot,dm-spl;
  51         };
  52 };
  53
  54 &qspi_bk1_pins_a {
  55         u-boot,dm-spl;
  56         pins1 {
  57                 u-boot,dm-spl;
  58         };
  59         pins2 {
  60                 u-boot,dm-spl;
  61         };
  62 };
  63
  64 &rcc {
  65         st,clksrc = <
  66                 CLK_MPU_PLL1P
  67                 CLK_AXI_PLL2P
  68                 CLK_MCU_PLL3P
  69                 CLK_PLL12_HSE
  70                 CLK_PLL3_HSE
  71                 CLK_PLL4_HSE
  72                 CLK_RTC_LSE
  73                 CLK_MCO1_DISABLED
  74                 CLK_MCO2_DISABLED
  75         >;
  76
  77         st,clkdiv = <
  78                 1 /*MPU*/
  79                 0 /*AXI*/
  80                 0 /*MCU*/
  81                 1 /*APB1*/
  82                 1 /*APB2*/
  83                 1 /*APB3*/
  84                 1 /*APB4*/
  85                 2 /*APB5*/
  86                 23 /*RTC*/
  87                 0 /*MCO1*/
  88                 0 /*MCO2*/
  89         >;
  90
  91         st,pkcs = <
  92                 CLK_CKPER_HSE
  93                 CLK_FMC_ACLK
  94                 CLK_QSPI_ACLK
  95                 CLK_ETH_DISABLED
  96                 CLK_SDMMC12_PLL4P
  97                 CLK_DSI_DSIPLL
  98                 CLK_STGEN_HSE
  99                 CLK_USBPHY_HSE
 100                 CLK_SPI2S1_PLL3Q
 101                 CLK_SPI2S23_PLL3Q
 102                 CLK_SPI45_HSI
 103                 CLK_SPI6_HSI
 104                 CLK_I2C46_HSI
 105                 CLK_SDMMC3_PLL4P
 106                 CLK_USBO_USBPHY
 107                 CLK_ADC_CKPER
 108                 CLK_CEC_LSE
 109                 CLK_I2C12_HSI
 110                 CLK_I2C35_HSI
 111                 CLK_UART1_HSI
 112                 CLK_UART24_HSI
 113                 CLK_UART35_HSI
 114                 CLK_UART6_HSI
 115                 CLK_UART78_HSI
 116                 CLK_SPDIF_PLL4P
 117                 CLK_FDCAN_PLL4R
 118                 CLK_SAI1_PLL3Q
 119                 CLK_SAI2_PLL3Q
 120                 CLK_SAI3_PLL3Q
 121                 CLK_SAI4_PLL3Q
 122                 CLK_RNG1_LSI
 123                 CLK_RNG2_LSI
 124                 CLK_LPTIM1_PCLK1
 125                 CLK_LPTIM23_PCLK3
 126                 CLK_LPTIM45_LSE
 127         >;
 128
 129         /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
 130         pll2: st,pll@1 {
 131                 compatible = "st,stm32mp1-pll";
 132                 reg = <1>;
 133                 cfg = < 2 65 1 0 0 PQR(1,1,1) >;
 134                 frac = < 0x1400 >;
 135                 u-boot,dm-pre-reloc;
 136         };
 137
 138         /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
 139         pll3: st,pll@2 {
 140                 compatible = "st,stm32mp1-pll";
 141                 reg = <2>;
 142                 cfg = < 1 33 1 16 36 PQR(1,1,1) >;
 143                 frac = < 0x1a04 >;
 144                 u-boot,dm-pre-reloc;
 145         };
 146
 147         /* VCO = 600.0 MHz => P = 99, Q = 74, R = 99 */
 148         pll4: st,pll@3 {
 149                 compatible = "st,stm32mp1-pll";
 150                 reg = <3>;
 151                 cfg = < 3 98 5 7 5 PQR(1,1,1) >;
 152                 u-boot,dm-pre-reloc;
 153         };
 154 };