arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
   2 /*
   3  * Copyright : STMicroelectronics 2018
   4  *
   5  * Copyright (C) Linaro Ltd 2019 - All Rights Reserved
   6  * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
   7  * Copyright (C) 2020 Marek Vasut <marex@denx.de>
   8  */
   9
  10 #include <dt-bindings/clock/stm32mp1-clksrc.h>
  11 #include "stm32mp15-u-boot.dtsi"
  12 #include "stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi"
  13 #include "stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi"
  14 #include "stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi"
  15
  16 / {
  17         u-boot,dm-pre-reloc;
  18
  19         aliases {
  20                 eeprom0 = &eeprom0;
  21         };
  22
  23         config {
  24                 dh,ddr3-coding-gpios = <&gpiog 0 0>, <&gpiog 1 0>;
  25                 dh,som-coding-gpios = <&gpioz 7 0>, <&gpiof 3 0>;
  26         };
  27 };
  28
  29 &flash0 {
  30         u-boot,dm-spl;
  31 };
  32
  33 &i2c4 {
  34         u-boot,dm-pre-reloc;
  35         u-boot,dm-spl;
  36
  37         eeprom0: eeprom@53 {
  38         };
  39 };
  40
  41 &i2c4_pins_a {
  42         u-boot,dm-pre-reloc;
  43         pins {
  44                 u-boot,dm-pre-reloc;
  45         };
  46 };
  47
  48 &pmic {
  49         u-boot,dm-pre-reloc;
  50         u-boot,dm-spl;
  51
  52         regulators {
  53                 u-boot,dm-spl;
  54         };
  55 };
  56
  57 &pwr_regulators {
  58         u-boot,dm-spl;
  59 };
  60
  61 &qspi {
  62         u-boot,dm-spl;
  63 };
  64
  65 &qspi_clk_pins_a {
  66         u-boot,dm-spl;
  67         pins {
  68                 u-boot,dm-spl;
  69         };
  70 };
  71
  72 &qspi_bk1_pins_a {
  73         u-boot,dm-spl;
  74         pins1 {
  75                 u-boot,dm-spl;
  76         };
  77         pins2 {
  78                 u-boot,dm-spl;
  79         };
  80 };
  81
  82 &rcc {
  83         st,clksrc = <
  84                 CLK_MPU_PLL1P
  85                 CLK_AXI_PLL2P
  86                 CLK_MCU_PLL3P
  87                 CLK_PLL12_HSE
  88                 CLK_PLL3_HSE
  89                 CLK_PLL4_HSE
  90                 CLK_RTC_LSE
  91                 CLK_MCO1_DISABLED
  92                 CLK_MCO2_DISABLED
  93         >;
  94
  95         st,clkdiv = <
  96                 1 /*MPU*/
  97                 0 /*AXI*/
  98                 0 /*MCU*/
  99                 1 /*APB1*/
 100                 1 /*APB2*/
 101                 1 /*APB3*/
 102                 1 /*APB4*/
 103                 2 /*APB5*/
 104                 23 /*RTC*/
 105                 0 /*MCO1*/
 106                 0 /*MCO2*/
 107         >;
 108
 109         st,pkcs = <
 110                 CLK_CKPER_HSE
 111                 CLK_FMC_ACLK
 112                 CLK_QSPI_ACLK
 113                 CLK_ETH_DISABLED
 114                 CLK_SDMMC12_PLL4P
 115                 CLK_DSI_DSIPLL
 116                 CLK_STGEN_HSE
 117                 CLK_USBPHY_HSE
 118                 CLK_SPI2S1_PLL3Q
 119                 CLK_SPI2S23_PLL3Q
 120                 CLK_SPI45_HSI
 121                 CLK_SPI6_HSI
 122                 CLK_I2C46_HSI
 123                 CLK_SDMMC3_PLL4P
 124                 CLK_USBO_USBPHY
 125                 CLK_ADC_CKPER
 126                 CLK_CEC_LSE
 127                 CLK_I2C12_HSI
 128                 CLK_I2C35_HSI
 129                 CLK_UART1_HSI
 130                 CLK_UART24_HSI
 131                 CLK_UART35_HSI
 132                 CLK_UART6_HSI
 133                 CLK_UART78_HSI
 134                 CLK_SPDIF_PLL4P
 135                 CLK_FDCAN_PLL4R
 136                 CLK_SAI1_PLL3Q
 137                 CLK_SAI2_PLL3Q
 138                 CLK_SAI3_PLL3Q
 139                 CLK_SAI4_PLL3Q
 140                 CLK_RNG1_LSI
 141                 CLK_RNG2_LSI
 142                 CLK_LPTIM1_PCLK1
 143                 CLK_LPTIM23_PCLK3
 144                 CLK_LPTIM45_LSE
 145         >;
 146
 147         /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
 148         pll2: st,pll@1 {
 149                 compatible = "st,stm32mp1-pll";
 150                 reg = <1>;
 151                 cfg = < 2 65 1 0 0 PQR(1,1,1) >;
 152                 frac = < 0x1400 >;
 153                 u-boot,dm-pre-reloc;
 154         };
 155
 156         /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
 157         pll3: st,pll@2 {
 158                 compatible = "st,stm32mp1-pll";
 159                 reg = <2>;
 160                 cfg = < 1 33 1 16 36 PQR(1,1,1) >;
 161                 frac = < 0x1a04 >;
 162                 u-boot,dm-pre-reloc;
 163         };
 164
 165         /* VCO = 600.0 MHz => P = 99, Q = 74, R = 99 */
 166         pll4: st,pll@3 {
 167                 compatible = "st,stm32mp1-pll";
 168                 reg = <3>;
 169                 cfg = < 3 98 5 7 5 PQR(1,1,1) >;
 170                 u-boot,dm-pre-reloc;
 171         };
 172 };
 173
 174 &reg11 {
 175         u-boot,dm-spl;
 176 };
 177
 178 &reg18 {
 179         u-boot,dm-spl;
 180 };
 181
 182 &usb33 {
 183         u-boot,dm-spl;
 184 };
 185
 186 &usbotg_hs_pins_a {
 187         u-boot,dm-spl;
 188 };
 189
 190 &usbotg_hs {
 191         u-boot,dm-spl;
 192 };
 193
 194 &usbphyc {
 195         u-boot,dm-spl;
 196 };
 197
 198 &usbphyc_port0 {
 199         u-boot,dm-spl;
 200 };
 201
 202 &usbphyc_port1 {
 203         u-boot,dm-spl;
 204 };
 205
 206 &vdd_usb {
 207         u-boot,dm-spl;
 208 };