1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2019 Marek Vasut <marex@denx.de>
6 #include <dt-bindings/clock/stm32mp1-clksrc.h>
7 #include "stm32mp15-u-boot.dtsi"
8 #include "stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi"
9 #include "stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi"
10 #include "stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi"
25 u-boot,boot-led = "heartbeat";
26 u-boot,error-led = "error";
27 dh,som-coding-gpios = <&gpiof 12 0>, <&gpiof 13 0>, <&gpiof 15 0>;
28 dh,ddr3-coding-gpios = <&gpioz 6 0>, <&gpioz 7 0>;
33 phy-reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>;
34 /delete-property/ st,eth-ref-clk-sel;
37 ðernet0_rmii_pins_a {
39 pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */
40 <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */
41 <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */
42 <STM32_PINMUX('A', 1, AF11)>, /* ETH1_RMII_REF_CLK */
43 <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */
44 <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */
64 /delete-property/ reset-gpios;
70 pinmux = <STM32_PINMUX('G', 2, AF1)>; /* MCO2 */
77 mco2_sleep_pins_a: mco2-sleep-0 {
79 pinmux = <STM32_PINMUX('G', 2, ANALOG)>; /* MCO2 */
97 compatible = "fixed-partitions";
103 reg = <0x00000000 0x00040000>;
107 reg = <0x00040000 0x00040000>;
111 reg = <0x00080000 0x00160000>;
115 reg = <0x001E0000 0x00010000>;
119 reg = <0x001F0000 0x00010000>;
157 * Reinstate clock names from stm32mp151.dtsi, the MCO2 trick
158 * used in stm32mp15xx-dhcom-som.dtsi is not supported by the
159 * U-Boot clock framework.
161 clock-names = "hse", "hsi", "csi", "lse", "lsi";
162 clocks = <&clk_hse>, <&clk_hsi>, <&clk_csi>,
163 <&clk_lse>, <&clk_lsi>;
165 /* The MCO2 is already configured correctly, remove those. */
166 /delete-property/ assigned-clocks;
167 /delete-property/ assigned-clock-parents;
168 /delete-property/ assigned-clock-rates;
235 * cfg = < DIVM1 DIVN P Q R PQR(p,q,r) >;
238 * PRQ(p,q,r) ... for p,q,r: 0-output disabled / 1-output enabled
239 * DIVN ... actually multiplier, but RCC_PLL1CFGR1 calls the field DIVN
240 * m ... for PLL1,2: m=2 ; for PLL3,4: m=1
243 * VCO = ( XTAL / (DIVM1 + 1) ) * m * ( DIVN + 1 + ( f / 8192 ) )
249 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
251 compatible = "st,stm32mp1-pll";
253 cfg = < 2 65 1 0 0 PQR(1,1,1) >;
258 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
260 compatible = "st,stm32mp1-pll";
262 cfg = < 1 33 1 16 36 PQR(1,1,1) >;
267 /* VCO = 600.0 MHz => P = 100, Q = 50, R = 50 */
269 compatible = "st,stm32mp1-pll";
271 cfg = < 1 49 5 11 11 PQR(1,1,1) >;
279 st,cmd-gpios = <&gpiod 2 0>;
280 st,ck-gpios = <&gpioc 12 0>;
281 st,ckin-gpios = <&gpioe 4 0>;
333 /* pull-up on rx to avoid floating level */