arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright (C) 2019 Marek Vasut <marex@denx.de>
   4  */
   5
   6 #include <dt-bindings/clock/stm32mp1-clksrc.h>
   7 #include "stm32mp15-u-boot.dtsi"
   8 #include "stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi"
   9 #include "stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi"
  10 #include "stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi"
  11
  12 / {
  13         aliases {
  14                 i2c1 = &i2c2;
  15                 i2c3 = &i2c4;
  16                 i2c4 = &i2c5;
  17                 mmc0 = &sdmmc1;
  18                 mmc1 = &sdmmc2;
  19                 spi0 = &qspi;
  20                 usb0 = &usbotg_hs;
  21                 eeprom0 = &eeprom0;
  22         };
  23
  24         config {
  25                 u-boot,boot-led = "heartbeat";
  26                 u-boot,error-led = "error";
  27                 dh,som-coding-gpios = <&gpiof 12 0>, <&gpiof 13 0>, <&gpiof 15 0>;
  28                 dh,ddr3-coding-gpios = <&gpioz 6 0>, <&gpioz 7 0>;
  29         };
  30 };
  31
  32 &ethernet0 {
  33         phy-reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>;
  34         /delete-property/ st,eth-ref-clk-sel;
  35 };
  36
  37 &ethernet0_rmii_pins_a {
  38         pins1 {
  39                 pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */
  40                          <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */
  41                          <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */
  42                          <STM32_PINMUX('A', 1, AF11)>,  /* ETH1_RMII_REF_CLK */
  43                          <STM32_PINMUX('A', 2, AF11)>,  /* ETH1_MDIO */
  44                          <STM32_PINMUX('C', 1, AF11)>;  /* ETH1_MDC */
  45         };
  46 };
  47
  48 &i2c4 {
  49         bootph-all;
  50         bootph-pre-ram;
  51
  52         eeprom0: eeprom@50 {
  53         };
  54 };
  55
  56 &i2c4_pins_a {
  57         bootph-all;
  58         pins {
  59                 bootph-all;
  60         };
  61 };
  62
  63 &phy0 {
  64         /delete-property/ reset-gpios;
  65 };
  66
  67 &pinctrl {
  68         mco2_pins_a: mco2-0 {
  69                 pins {
  70                         pinmux = <STM32_PINMUX('G', 2, AF1)>; /* MCO2 */
  71                         bias-disable;
  72                         drive-push-pull;
  73                         slew-rate = <2>;
  74                 };
  75         };
  76
  77         mco2_sleep_pins_a: mco2-sleep-0 {
  78                 pins {
  79                         pinmux = <STM32_PINMUX('G', 2, ANALOG)>; /* MCO2 */
  80                 };
  81         };
  82 };
  83
  84 &pmic {
  85         bootph-all;
  86         bootph-pre-ram;
  87
  88         regulators {
  89                 bootph-pre-ram;
  90         };
  91 };
  92
  93 &flash0 {
  94         bootph-pre-ram;
  95
  96         partitions {
  97                 compatible = "fixed-partitions";
  98                 #address-cells = <1>;
  99                 #size-cells = <1>;
 100
 101                 partition@0 {
 102                         label = "fsbl1";
 103                         reg = <0x00000000 0x00040000>;
 104                 };
 105                 partition@40000 {
 106                         label = "fsbl2";
 107                         reg = <0x00040000 0x00040000>;
 108                 };
 109                 partition@500000 {
 110                         label = "uboot";
 111                         reg = <0x00080000 0x00160000>;
 112                 };
 113                 partition@900000 {
 114                         label = "env1";
 115                         reg = <0x001E0000 0x00010000>;
 116                 };
 117                 partition@980000 {
 118                         label = "env2";
 119                         reg = <0x001F0000 0x00010000>;
 120                 };
 121         };
 122 };
 123
 124 &qspi {
 125         bootph-pre-ram;
 126 };
 127
 128 &qspi_clk_pins_a {
 129         bootph-pre-ram;
 130         pins {
 131                 bootph-pre-ram;
 132         };
 133 };
 134
 135 &qspi_bk1_pins_a {
 136         bootph-pre-ram;
 137         pins1 {
 138                 bootph-pre-ram;
 139         };
 140         pins2 {
 141                 bootph-pre-ram;
 142         };
 143 };
 144
 145 &qspi_bk2_pins_a {
 146         bootph-pre-ram;
 147         pins1 {
 148                 bootph-pre-ram;
 149         };
 150         pins2 {
 151                 bootph-pre-ram;
 152         };
 153 };
 154
 155 &rcc {
 156         /*
 157          * Reinstate clock names from stm32mp151.dtsi, the MCO2 trick
 158          * used in stm32mp15xx-dhcom-som.dtsi is not supported by the
 159          * U-Boot clock framework.
 160          */
 161         clock-names = "hse", "hsi", "csi", "lse", "lsi";
 162         clocks = <&clk_hse>, <&clk_hsi>, <&clk_csi>,
 163                  <&clk_lse>, <&clk_lsi>;
 164
 165         /* The MCO2 is already configured correctly, remove those. */
 166         /delete-property/ assigned-clocks;
 167         /delete-property/ assigned-clock-parents;
 168         /delete-property/ assigned-clock-rates;
 169
 170         st,clksrc = <
 171                 CLK_MPU_PLL1P
 172                 CLK_AXI_PLL2P
 173                 CLK_MCU_PLL3P
 174                 CLK_PLL12_HSE
 175                 CLK_PLL3_HSE
 176                 CLK_PLL4_HSE
 177                 CLK_RTC_LSE
 178                 CLK_MCO1_DISABLED
 179                 CLK_MCO2_PLL4P
 180         >;
 181
 182         st,clkdiv = <
 183                 1 /*MPU*/
 184                 0 /*AXI*/
 185                 0 /*MCU*/
 186                 1 /*APB1*/
 187                 1 /*APB2*/
 188                 1 /*APB3*/
 189                 1 /*APB4*/
 190                 2 /*APB5*/
 191                 23 /*RTC*/
 192                 0 /*MCO1*/
 193                 1 /*MCO2*/
 194         >;
 195
 196         st,pkcs = <
 197                 CLK_CKPER_HSE
 198                 CLK_FMC_ACLK
 199                 CLK_QSPI_ACLK
 200                 CLK_ETH_PLL4P
 201                 CLK_SDMMC12_PLL4P
 202                 CLK_DSI_DSIPLL
 203                 CLK_STGEN_HSE
 204                 CLK_USBPHY_HSE
 205                 CLK_SPI2S1_PLL3Q
 206                 CLK_SPI2S23_PLL3Q
 207                 CLK_SPI45_HSI
 208                 CLK_SPI6_HSI
 209                 CLK_I2C46_HSI
 210                 CLK_SDMMC3_PLL4P
 211                 CLK_USBO_USBPHY
 212                 CLK_ADC_CKPER
 213                 CLK_CEC_LSE
 214                 CLK_I2C12_HSI
 215                 CLK_I2C35_HSI
 216                 CLK_UART1_HSI
 217                 CLK_UART24_HSI
 218                 CLK_UART35_HSI
 219                 CLK_UART6_HSI
 220                 CLK_UART78_HSI
 221                 CLK_SPDIF_PLL4P
 222                 CLK_FDCAN_PLL4R
 223                 CLK_SAI1_PLL3Q
 224                 CLK_SAI2_PLL3Q
 225                 CLK_SAI3_PLL3Q
 226                 CLK_SAI4_PLL3Q
 227                 CLK_RNG1_LSI
 228                 CLK_RNG2_LSI
 229                 CLK_LPTIM1_PCLK1
 230                 CLK_LPTIM23_PCLK3
 231                 CLK_LPTIM45_LSE
 232         >;
 233
 234         /*
 235          * cfg = < DIVM1 DIVN P Q R PQR(p,q,r) >;
 236          * frac = < f >;
 237          *
 238          * PRQ(p,q,r) ... for p,q,r: 0-output disabled / 1-output enabled
 239          * DIVN ... actually multiplier, but RCC_PLL1CFGR1 calls the field DIVN
 240          * m ... for PLL1,2: m=2 ; for PLL3,4: m=1
 241          * XTAL = 24 MHz
 242          *
 243          * VCO = ( XTAL / (DIVM1 + 1) ) * m * ( DIVN + 1 + ( f / 8192 ) )
 244          *   P = VCO / (P + 1)
 245          *   Q = VCO / (Q + 1)
 246          *   R = VCO / (R + 1)
 247          */
 248
 249         /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
 250         pll2: st,pll@1 {
 251                 compatible = "st,stm32mp1-pll";
 252                 reg = <1>;
 253                 cfg = < 2 65 1 0 0 PQR(1,1,1) >;
 254                 frac = < 0x1400 >;
 255                 bootph-all;
 256         };
 257
 258         /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
 259         pll3: st,pll@2 {
 260                 compatible = "st,stm32mp1-pll";
 261                 reg = <2>;
 262                 cfg = < 1 33 1 16 36 PQR(1,1,1) >;
 263                 frac = < 0x1a04 >;
 264                 bootph-all;
 265         };
 266
 267         /* VCO = 600.0 MHz => P = 100, Q = 50, R = 50 */
 268         pll4: st,pll@3 {
 269                 compatible = "st,stm32mp1-pll";
 270                 reg = <3>;
 271                 cfg = < 1 49 5 11 11 PQR(1,1,1) >;
 272                 bootph-all;
 273         };
 274 };
 275
 276 &sdmmc1 {
 277         bootph-pre-ram;
 278         st,use-ckin;
 279         st,cmd-gpios = <&gpiod 2 0>;
 280         st,ck-gpios = <&gpioc 12 0>;
 281         st,ckin-gpios = <&gpioe 4 0>;
 282 };
 283
 284 &sdmmc1_b4_pins_a {
 285         bootph-pre-ram;
 286         pins1 {
 287                 bootph-pre-ram;
 288         };
 289         pins2 {
 290                 bootph-pre-ram;
 291         };
 292 };
 293
 294 &sdmmc1_dir_pins_a {
 295         bootph-pre-ram;
 296         pins1 {
 297                 bootph-pre-ram;
 298         };
 299         pins2 {
 300                 bootph-pre-ram;
 301         };
 302 };
 303
 304 &sdmmc2 {
 305         bootph-pre-ram;
 306 };
 307
 308 &sdmmc2_b4_pins_a {
 309         bootph-pre-ram;
 310         pins {
 311                 bootph-pre-ram;
 312         };
 313 };
 314
 315 &sdmmc2_d47_pins_a {
 316         bootph-pre-ram;
 317         pins {
 318                 bootph-pre-ram;
 319         };
 320 };
 321
 322 &uart4 {
 323         bootph-all;
 324 };
 325
 326 &uart4_pins_a {
 327         bootph-all;
 328         pins1 {
 329                 bootph-all;
 330         };
 331         pins2 {
 332                 bootph-all;
 333                 /* pull-up on rx to avoid floating level */
 334                 bias-pull-up;
 335         };
 336 };
 337
 338 &reg11 {
 339         bootph-pre-ram;
 340 };
 341
 342 &reg18 {
 343         bootph-pre-ram;
 344 };
 345
 346 &usb33 {
 347         bootph-pre-ram;
 348 };
 349
 350 &usbotg_hs_pins_a {
 351         bootph-pre-ram;
 352 };
 353
 354 &usbotg_hs {
 355         bootph-pre-ram;
 356 };
 357
 358 &usbphyc {
 359         bootph-pre-ram;
 360 };
 361
 362 &usbphyc_port0 {
 363         bootph-pre-ram;
 364 };
 365
 366 &usbphyc_port1 {
 367         bootph-pre-ram;
 368 };
 369
 370 &vdd_usb {
 371         bootph-pre-ram;
 372 };