arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright (C) 2019 Marek Vasut <marex@denx.de>
   4  */
   5
   6 #include <dt-bindings/clock/stm32mp1-clksrc.h>
   7 #include "stm32mp15-u-boot.dtsi"
   8 #include "stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi"
   9 #include "stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi"
  10 #include "stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi"
  11
  12 / {
  13         aliases {
  14                 i2c1 = &i2c2;
  15                 i2c3 = &i2c4;
  16                 i2c4 = &i2c5;
  17                 mmc0 = &sdmmc1;
  18                 mmc1 = &sdmmc2;
  19                 spi0 = &qspi;
  20                 usb0 = &usbotg_hs;
  21                 ethernet1 = &ksz8851;
  22         };
  23
  24         config {
  25                 u-boot,boot-led = "heartbeat";
  26                 u-boot,error-led = "error";
  27                 st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
  28                 st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
  29                 dh,som-coding-gpios = <&gpiof 12 0>, <&gpiof 13 0>, <&gpiof 15 0>;
  30                 dh,ddr3-coding-gpios = <&gpioz 6 0>, <&gpioz 7 0>;
  31         };
  32
  33         led {
  34                 red {
  35                         label = "error";
  36                         gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
  37                         default-state = "off";
  38                         status = "okay";
  39                 };
  40
  41                 blue {
  42                         default-state = "on";
  43                 };
  44         };
  45
  46         /* This is actually on FMC2, but we do not have bus driver for that */
  47         ksz8851: ks8851mll@64000000 {
  48                 compatible = "micrel,ks8851-mll";
  49                 reg = <0x64000000 0x20000>;
  50         };
  51 };
  52
  53 &gpiof {
  54         snor-nwp {
  55                 gpio-hog;
  56                 gpios = <7 0>;
  57                 output-high;
  58                 line-name = "spi-nor-nwp";
  59         };
  60 };
  61
  62 &i2c4 {
  63         u-boot,dm-pre-reloc;
  64 };
  65
  66 &i2c4_pins_a {
  67         u-boot,dm-pre-reloc;
  68         pins {
  69                 u-boot,dm-pre-reloc;
  70         };
  71 };
  72
  73 &pinctrl {
  74         /* These should bound to FMC2 bus driver, but we do not have one */
  75         pinctrl-0 = <&fmc_pins_b>;
  76         pinctrl-1 = <&fmc_sleep_pins_b>;
  77         pinctrl-names = "default", "sleep";
  78
  79         fmc_pins_b: fmc-0 {
  80                 pins1 {
  81                         pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
  82                                  <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */
  83                                  <STM32_PINMUX('B', 7, AF12)>, /* FMC_NL */
  84                                  <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */
  85                                  <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */
  86                                  <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */
  87                                  <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */
  88                                  <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */
  89                                  <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */
  90                                  <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */
  91                                  <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */
  92                                  <STM32_PINMUX('E', 11, AF12)>, /* FMC_D8 */
  93                                  <STM32_PINMUX('E', 12, AF12)>, /* FMC_D9 */
  94                                  <STM32_PINMUX('E', 13, AF12)>, /* FMC_D10 */
  95                                  <STM32_PINMUX('E', 14, AF12)>, /* FMC_D11 */
  96                                  <STM32_PINMUX('E', 15, AF12)>, /* FMC_D12 */
  97                                  <STM32_PINMUX('D', 8, AF12)>, /* FMC_D13 */
  98                                  <STM32_PINMUX('D', 9, AF12)>, /* FMC_D14 */
  99                                  <STM32_PINMUX('D', 10, AF12)>, /* FMC_D15 */
 100                                  <STM32_PINMUX('G', 9, AF12)>, /* FMC_NE2_FMC_NCE */
 101                                  <STM32_PINMUX('G', 12, AF12)>; /* FMC_NE4 */
 102                         bias-disable;
 103                         drive-push-pull;
 104                         slew-rate = <3>;
 105                 };
 106         };
 107
 108         fmc_sleep_pins_b: fmc-sleep-0 {
 109                 pins {
 110                         pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */
 111                                  <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */
 112                                  <STM32_PINMUX('B', 7, ANALOG)>, /* FMC_NL */
 113                                  <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */
 114                                  <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */
 115                                  <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */
 116                                  <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */
 117                                  <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */
 118                                  <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */
 119                                  <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */
 120                                  <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */
 121                                  <STM32_PINMUX('E', 11, ANALOG)>, /* FMC_D8 */
 122                                  <STM32_PINMUX('E', 12, ANALOG)>, /* FMC_D9 */
 123                                  <STM32_PINMUX('E', 13, ANALOG)>, /* FMC_D10 */
 124                                  <STM32_PINMUX('E', 14, ANALOG)>, /* FMC_D11 */
 125                                  <STM32_PINMUX('E', 15, ANALOG)>, /* FMC_D12 */
 126                                  <STM32_PINMUX('D', 8, ANALOG)>, /* FMC_D13 */
 127                                  <STM32_PINMUX('D', 9, ANALOG)>, /* FMC_D14 */
 128                                  <STM32_PINMUX('D', 10, ANALOG)>, /* FMC_D15 */
 129                                  <STM32_PINMUX('G', 9, ANALOG)>, /* FMC_NE2_FMC_NCE */
 130                                  <STM32_PINMUX('G', 12, ANALOG)>; /* FMC_NE4 */
 131                 };
 132         };
 133 };
 134
 135 &pmic {
 136         u-boot,dm-pre-reloc;
 137 };
 138
 139 &flash0 {
 140         u-boot,dm-spl;
 141 };
 142
 143 &qspi {
 144         u-boot,dm-spl;
 145 };
 146
 147 &qspi_clk_pins_a {
 148         u-boot,dm-spl;
 149         pins {
 150                 u-boot,dm-spl;
 151         };
 152 };
 153
 154 &qspi_bk1_pins_a {
 155         u-boot,dm-spl;
 156         pins1 {
 157                 u-boot,dm-spl;
 158         };
 159         pins2 {
 160                 u-boot,dm-spl;
 161         };
 162 };
 163
 164 &qspi_bk2_pins_a {
 165         u-boot,dm-spl;
 166         pins1 {
 167                 u-boot,dm-spl;
 168         };
 169         pins2 {
 170                 u-boot,dm-spl;
 171         };
 172 };
 173
 174 &rcc {
 175         st,clksrc = <
 176                 CLK_MPU_PLL1P
 177                 CLK_AXI_PLL2P
 178                 CLK_MCU_PLL3P
 179                 CLK_PLL12_HSE
 180                 CLK_PLL3_HSE
 181                 CLK_PLL4_HSE
 182                 CLK_RTC_LSE
 183                 CLK_MCO1_DISABLED
 184                 CLK_MCO2_DISABLED
 185         >;
 186
 187         st,clkdiv = <
 188                 1 /*MPU*/
 189                 0 /*AXI*/
 190                 0 /*MCU*/
 191                 1 /*APB1*/
 192                 1 /*APB2*/
 193                 1 /*APB3*/
 194                 1 /*APB4*/
 195                 2 /*APB5*/
 196                 23 /*RTC*/
 197                 0 /*MCO1*/
 198                 0 /*MCO2*/
 199         >;
 200
 201         st,pkcs = <
 202                 CLK_CKPER_HSE
 203                 CLK_FMC_ACLK
 204                 CLK_QSPI_ACLK
 205                 CLK_ETH_PLL4P
 206                 CLK_SDMMC12_PLL4P
 207                 CLK_DSI_DSIPLL
 208                 CLK_STGEN_HSE
 209                 CLK_USBPHY_HSE
 210                 CLK_SPI2S1_PLL3Q
 211                 CLK_SPI2S23_PLL3Q
 212                 CLK_SPI45_HSI
 213                 CLK_SPI6_HSI
 214                 CLK_I2C46_HSI
 215                 CLK_SDMMC3_PLL4P
 216                 CLK_USBO_USBPHY
 217                 CLK_ADC_CKPER
 218                 CLK_CEC_LSE
 219                 CLK_I2C12_HSI
 220                 CLK_I2C35_HSI
 221                 CLK_UART1_HSI
 222                 CLK_UART24_HSI
 223                 CLK_UART35_HSI
 224                 CLK_UART6_HSI
 225                 CLK_UART78_HSI
 226                 CLK_SPDIF_PLL4P
 227                 CLK_FDCAN_PLL4R
 228                 CLK_SAI1_PLL3Q
 229                 CLK_SAI2_PLL3Q
 230                 CLK_SAI3_PLL3Q
 231                 CLK_SAI4_PLL3Q
 232                 CLK_RNG1_LSI
 233                 CLK_RNG2_LSI
 234                 CLK_LPTIM1_PCLK1
 235                 CLK_LPTIM23_PCLK3
 236                 CLK_LPTIM45_LSE
 237         >;
 238
 239         /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
 240         pll2: st,pll@1 {
 241                 compatible = "st,stm32mp1-pll";
 242                 reg = <1>;
 243                 cfg = < 2 65 1 0 0 PQR(1,1,1) >;
 244                 frac = < 0x1400 >;
 245                 u-boot,dm-pre-reloc;
 246         };
 247
 248         /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
 249         pll3: st,pll@2 {
 250                 compatible = "st,stm32mp1-pll";
 251                 reg = <2>;
 252                 cfg = < 1 33 1 16 36 PQR(1,1,1) >;
 253                 frac = < 0x1a04 >;
 254                 u-boot,dm-pre-reloc;
 255         };
 256
 257         /* VCO = 600.0 MHz => P = 50, Q = 50, R = 50 */
 258         pll4: st,pll@3 {
 259                 compatible = "st,stm32mp1-pll";
 260                 reg = <3>;
 261                 cfg = < 1 49 11 11 11 PQR(1,1,1) >;
 262                 u-boot,dm-pre-reloc;
 263         };
 264 };
 265
 266 &sdmmc1 {
 267         u-boot,dm-spl;
 268 };
 269
 270 &sdmmc1_b4_pins_a {
 271         u-boot,dm-spl;
 272         pins1 {
 273                 u-boot,dm-spl;
 274         };
 275         pins2 {
 276                 u-boot,dm-spl;
 277         };
 278 };
 279
 280 &sdmmc1_dir_pins_a {
 281         u-boot,dm-spl;
 282         pins1 {
 283                 u-boot,dm-spl;
 284         };
 285         pins2 {
 286                 u-boot,dm-spl;
 287         };
 288 };
 289
 290 &sdmmc2 {
 291         u-boot,dm-spl;
 292 };
 293
 294 &sdmmc2_b4_pins_a {
 295         u-boot,dm-spl;
 296         pins {
 297                 u-boot,dm-spl;
 298         };
 299 };
 300
 301 &sdmmc2_d47_pins_a {
 302         u-boot,dm-spl;
 303         pins {
 304                 u-boot,dm-spl;
 305         };
 306 };
 307
 308 &uart4 {
 309         u-boot,dm-pre-reloc;
 310 };
 311
 312 &uart4_pins_a {
 313         u-boot,dm-pre-reloc;
 314         pins1 {
 315                 u-boot,dm-pre-reloc;
 316         };
 317         pins2 {
 318                 u-boot,dm-pre-reloc;
 319                 /* pull-up on rx to avoid floating level */
 320                 bias-pull-up;
 321         };
 322 };