arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright (C) 2019 Marek Vasut <marex@denx.de>
   4  */
   5
   6 #include <dt-bindings/clock/stm32mp1-clksrc.h>
   7 #include "stm32mp15-u-boot.dtsi"
   8 #include "stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi"
   9 #include "stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi"
  10 #include "stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi"
  11
  12 / {
  13         aliases {
  14                 i2c1 = &i2c2;
  15                 i2c3 = &i2c4;
  16                 i2c4 = &i2c5;
  17                 mmc0 = &sdmmc1;
  18                 mmc1 = &sdmmc2;
  19                 spi0 = &qspi;
  20                 usb0 = &usbotg_hs;
  21                 ethernet1 = &ksz8851;
  22         };
  23
  24         config {
  25                 u-boot,boot-led = "heartbeat";
  26                 u-boot,error-led = "error";
  27                 st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
  28                 st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
  29                 dh,som-coding-gpios = <&gpiof 12 0>, <&gpiof 13 0>, <&gpiof 15 0>;
  30                 dh,ddr3-coding-gpios = <&gpioz 6 0>, <&gpioz 7 0>;
  31         };
  32
  33         led {
  34                 red {
  35                         label = "error";
  36                         gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
  37                         default-state = "off";
  38                         status = "okay";
  39                 };
  40
  41                 blue {
  42                         default-state = "on";
  43                 };
  44         };
  45
  46         /* This is actually on FMC2, but we do not have bus driver for that */
  47         ksz8851: ks8851mll@64000000 {
  48                 compatible = "micrel,ks8851-mll";
  49                 reg = <0x64000000 0x20000>;
  50         };
  51 };
  52
  53 &i2c4 {
  54         u-boot,dm-pre-reloc;
  55 };
  56
  57 &i2c4_pins_a {
  58         u-boot,dm-pre-reloc;
  59         pins {
  60                 u-boot,dm-pre-reloc;
  61         };
  62 };
  63
  64 &pinctrl {
  65         /* These should bound to FMC2 bus driver, but we do not have one */
  66         pinctrl-0 = <&fmc_pins_b &mco2_pins_a>;
  67         pinctrl-1 = <&fmc_sleep_pins_b &mco2_sleep_pins_a>;
  68         pinctrl-names = "default", "sleep";
  69
  70         mco2_pins_a: mco2-0 {
  71                 pins {
  72                         pinmux = <STM32_PINMUX('G', 2, AF1)>; /* MCO2 */
  73                         bias-disable;
  74                         drive-push-pull;
  75                         slew-rate = <2>;
  76                 };
  77         };
  78
  79         mco2_sleep_pins_a: mco2-sleep-0 {
  80                 pins {
  81                         pinmux = <STM32_PINMUX('G', 2, ANALOG)>; /* MCO2 */
  82                 };
  83         };
  84 };
  85
  86 &pmic {
  87         u-boot,dm-pre-reloc;
  88 };
  89
  90 &flash0 {
  91         u-boot,dm-spl;
  92 };
  93
  94 &qspi {
  95         u-boot,dm-spl;
  96 };
  97
  98 &qspi_clk_pins_a {
  99         u-boot,dm-spl;
 100         pins {
 101                 u-boot,dm-spl;
 102         };
 103 };
 104
 105 &qspi_bk1_pins_a {
 106         u-boot,dm-spl;
 107         pins1 {
 108                 u-boot,dm-spl;
 109         };
 110         pins2 {
 111                 u-boot,dm-spl;
 112         };
 113 };
 114
 115 &qspi_bk2_pins_a {
 116         u-boot,dm-spl;
 117         pins1 {
 118                 u-boot,dm-spl;
 119         };
 120         pins2 {
 121                 u-boot,dm-spl;
 122         };
 123 };
 124
 125 &rcc {
 126         st,clksrc = <
 127                 CLK_MPU_PLL1P
 128                 CLK_AXI_PLL2P
 129                 CLK_MCU_PLL3P
 130                 CLK_PLL12_HSE
 131                 CLK_PLL3_HSE
 132                 CLK_PLL4_HSE
 133                 CLK_RTC_LSE
 134                 CLK_MCO1_DISABLED
 135                 CLK_MCO2_PLL4P
 136         >;
 137
 138         st,clkdiv = <
 139                 1 /*MPU*/
 140                 0 /*AXI*/
 141                 0 /*MCU*/
 142                 1 /*APB1*/
 143                 1 /*APB2*/
 144                 1 /*APB3*/
 145                 1 /*APB4*/
 146                 2 /*APB5*/
 147                 23 /*RTC*/
 148                 0 /*MCO1*/
 149                 1 /*MCO2*/
 150         >;
 151
 152         st,pkcs = <
 153                 CLK_CKPER_HSE
 154                 CLK_FMC_ACLK
 155                 CLK_QSPI_ACLK
 156                 CLK_ETH_PLL4P
 157                 CLK_SDMMC12_PLL4P
 158                 CLK_DSI_DSIPLL
 159                 CLK_STGEN_HSE
 160                 CLK_USBPHY_HSE
 161                 CLK_SPI2S1_PLL3Q
 162                 CLK_SPI2S23_PLL3Q
 163                 CLK_SPI45_HSI
 164                 CLK_SPI6_HSI
 165                 CLK_I2C46_HSI
 166                 CLK_SDMMC3_PLL4P
 167                 CLK_USBO_USBPHY
 168                 CLK_ADC_CKPER
 169                 CLK_CEC_LSE
 170                 CLK_I2C12_HSI
 171                 CLK_I2C35_HSI
 172                 CLK_UART1_HSI
 173                 CLK_UART24_HSI
 174                 CLK_UART35_HSI
 175                 CLK_UART6_HSI
 176                 CLK_UART78_HSI
 177                 CLK_SPDIF_PLL4P
 178                 CLK_FDCAN_PLL4R
 179                 CLK_SAI1_PLL3Q
 180                 CLK_SAI2_PLL3Q
 181                 CLK_SAI3_PLL3Q
 182                 CLK_SAI4_PLL3Q
 183                 CLK_RNG1_LSI
 184                 CLK_RNG2_LSI
 185                 CLK_LPTIM1_PCLK1
 186                 CLK_LPTIM23_PCLK3
 187                 CLK_LPTIM45_LSE
 188         >;
 189
 190         /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
 191         pll2: st,pll@1 {
 192                 compatible = "st,stm32mp1-pll";
 193                 reg = <1>;
 194                 cfg = < 2 65 1 0 0 PQR(1,1,1) >;
 195                 frac = < 0x1400 >;
 196                 u-boot,dm-pre-reloc;
 197         };
 198
 199         /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
 200         pll3: st,pll@2 {
 201                 compatible = "st,stm32mp1-pll";
 202                 reg = <2>;
 203                 cfg = < 1 33 1 16 36 PQR(1,1,1) >;
 204                 frac = < 0x1a04 >;
 205                 u-boot,dm-pre-reloc;
 206         };
 207
 208         /* VCO = 600.0 MHz => P = 50, Q = 50, R = 50 */
 209         pll4: st,pll@3 {
 210                 compatible = "st,stm32mp1-pll";
 211                 reg = <3>;
 212                 cfg = < 1 49 5 11 11 PQR(1,1,1) >;
 213                 u-boot,dm-pre-reloc;
 214         };
 215 };
 216
 217 &sdmmc1 {
 218         u-boot,dm-spl;
 219 };
 220
 221 &sdmmc1_b4_pins_a {
 222         u-boot,dm-spl;
 223         pins1 {
 224                 u-boot,dm-spl;
 225         };
 226         pins2 {
 227                 u-boot,dm-spl;
 228         };
 229 };
 230
 231 &sdmmc1_dir_pins_a {
 232         u-boot,dm-spl;
 233         pins1 {
 234                 u-boot,dm-spl;
 235         };
 236         pins2 {
 237                 u-boot,dm-spl;
 238         };
 239 };
 240
 241 &sdmmc2 {
 242         u-boot,dm-spl;
 243 };
 244
 245 &sdmmc2_b4_pins_a {
 246         u-boot,dm-spl;
 247         pins {
 248                 u-boot,dm-spl;
 249         };
 250 };
 251
 252 &sdmmc2_d47_pins_a {
 253         u-boot,dm-spl;
 254         pins {
 255                 u-boot,dm-spl;
 256         };
 257 };
 258
 259 &uart4 {
 260         u-boot,dm-pre-reloc;
 261 };
 262
 263 &uart4_pins_a {
 264         u-boot,dm-pre-reloc;
 265         pins1 {
 266                 u-boot,dm-pre-reloc;
 267         };
 268         pins2 {
 269                 u-boot,dm-pre-reloc;
 270                 /* pull-up on rx to avoid floating level */
 271                 bias-pull-up;
 272         };
 273 };