arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright (C) 2019 Marek Vasut <marex@denx.de>
   4  */
   5
   6 #include <dt-bindings/clock/stm32mp1-clksrc.h>
   7 #include "stm32mp15-u-boot.dtsi"
   8 #include "stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi"
   9 #include "stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi"
  10 #include "stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi"
  11
  12 / {
  13         aliases {
  14                 i2c1 = &i2c2;
  15                 i2c3 = &i2c4;
  16                 i2c4 = &i2c5;
  17                 mmc0 = &sdmmc1;
  18                 mmc1 = &sdmmc2;
  19                 spi0 = &qspi;
  20                 usb0 = &usbotg_hs;
  21                 ethernet1 = &ksz8851;
  22         };
  23
  24         config {
  25                 u-boot,boot-led = "heartbeat";
  26                 u-boot,error-led = "error";
  27                 st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
  28                 st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
  29                 dh,som-coding-gpios = <&gpiof 12 0>, <&gpiof 13 0>, <&gpiof 15 0>;
  30                 dh,ddr3-coding-gpios = <&gpioz 6 0>, <&gpioz 7 0>;
  31         };
  32
  33         led {
  34                 red {
  35                         label = "error";
  36                         gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
  37                         default-state = "off";
  38                         status = "okay";
  39                 };
  40
  41                 blue {
  42                         default-state = "on";
  43                 };
  44         };
  45
  46         /* This is actually on FMC2, but we do not have bus driver for that */
  47         ksz8851: ks8851mll@64000000 {
  48                 compatible = "micrel,ks8851-mll";
  49                 reg = <0x64000000 0x20000>;
  50         };
  51 };
  52
  53 &gpiof {
  54         snor-nwp {
  55                 gpio-hog;
  56                 gpios = <7 0>;
  57                 output-high;
  58                 line-name = "spi-nor-nwp";
  59         };
  60 };
  61
  62 &i2c4 {
  63         u-boot,dm-pre-reloc;
  64 };
  65
  66 &i2c4_pins_a {
  67         u-boot,dm-pre-reloc;
  68         pins {
  69                 u-boot,dm-pre-reloc;
  70         };
  71 };
  72
  73 &pinctrl {
  74         /* These should bound to FMC2 bus driver, but we do not have one */
  75         pinctrl-0 = <&fmc_pins_b &mco2_pins_a>;
  76         pinctrl-1 = <&fmc_sleep_pins_b &mco2_sleep_pins_a>;
  77         pinctrl-names = "default", "sleep";
  78
  79         mco2_pins_a: mco2-0 {
  80                 pins {
  81                         pinmux = <STM32_PINMUX('G', 2, AF1)>; /* MCO2 */
  82                         bias-disable;
  83                         drive-push-pull;
  84                         slew-rate = <2>;
  85                 };
  86         };
  87
  88         mco2_sleep_pins_a: mco2-sleep-0 {
  89                 pins {
  90                         pinmux = <STM32_PINMUX('G', 2, ANALOG)>; /* MCO2 */
  91                 };
  92         };
  93 };
  94
  95 &pmic {
  96         u-boot,dm-pre-reloc;
  97 };
  98
  99 &flash0 {
 100         u-boot,dm-spl;
 101 };
 102
 103 &qspi {
 104         u-boot,dm-spl;
 105 };
 106
 107 &qspi_clk_pins_a {
 108         u-boot,dm-spl;
 109         pins {
 110                 u-boot,dm-spl;
 111         };
 112 };
 113
 114 &qspi_bk1_pins_a {
 115         u-boot,dm-spl;
 116         pins1 {
 117                 u-boot,dm-spl;
 118         };
 119         pins2 {
 120                 u-boot,dm-spl;
 121         };
 122 };
 123
 124 &qspi_bk2_pins_a {
 125         u-boot,dm-spl;
 126         pins1 {
 127                 u-boot,dm-spl;
 128         };
 129         pins2 {
 130                 u-boot,dm-spl;
 131         };
 132 };
 133
 134 &rcc {
 135         st,clksrc = <
 136                 CLK_MPU_PLL1P
 137                 CLK_AXI_PLL2P
 138                 CLK_MCU_PLL3P
 139                 CLK_PLL12_HSE
 140                 CLK_PLL3_HSE
 141                 CLK_PLL4_HSE
 142                 CLK_RTC_LSE
 143                 CLK_MCO1_DISABLED
 144                 CLK_MCO2_PLL4P
 145         >;
 146
 147         st,clkdiv = <
 148                 1 /*MPU*/
 149                 0 /*AXI*/
 150                 0 /*MCU*/
 151                 1 /*APB1*/
 152                 1 /*APB2*/
 153                 1 /*APB3*/
 154                 1 /*APB4*/
 155                 2 /*APB5*/
 156                 23 /*RTC*/
 157                 0 /*MCO1*/
 158                 1 /*MCO2*/
 159         >;
 160
 161         st,pkcs = <
 162                 CLK_CKPER_HSE
 163                 CLK_FMC_ACLK
 164                 CLK_QSPI_ACLK
 165                 CLK_ETH_PLL4P
 166                 CLK_SDMMC12_PLL4P
 167                 CLK_DSI_DSIPLL
 168                 CLK_STGEN_HSE
 169                 CLK_USBPHY_HSE
 170                 CLK_SPI2S1_PLL3Q
 171                 CLK_SPI2S23_PLL3Q
 172                 CLK_SPI45_HSI
 173                 CLK_SPI6_HSI
 174                 CLK_I2C46_HSI
 175                 CLK_SDMMC3_PLL4P
 176                 CLK_USBO_USBPHY
 177                 CLK_ADC_CKPER
 178                 CLK_CEC_LSE
 179                 CLK_I2C12_HSI
 180                 CLK_I2C35_HSI
 181                 CLK_UART1_HSI
 182                 CLK_UART24_HSI
 183                 CLK_UART35_HSI
 184                 CLK_UART6_HSI
 185                 CLK_UART78_HSI
 186                 CLK_SPDIF_PLL4P
 187                 CLK_FDCAN_PLL4R
 188                 CLK_SAI1_PLL3Q
 189                 CLK_SAI2_PLL3Q
 190                 CLK_SAI3_PLL3Q
 191                 CLK_SAI4_PLL3Q
 192                 CLK_RNG1_LSI
 193                 CLK_RNG2_LSI
 194                 CLK_LPTIM1_PCLK1
 195                 CLK_LPTIM23_PCLK3
 196                 CLK_LPTIM45_LSE
 197         >;
 198
 199         /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
 200         pll2: st,pll@1 {
 201                 compatible = "st,stm32mp1-pll";
 202                 reg = <1>;
 203                 cfg = < 2 65 1 0 0 PQR(1,1,1) >;
 204                 frac = < 0x1400 >;
 205                 u-boot,dm-pre-reloc;
 206         };
 207
 208         /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
 209         pll3: st,pll@2 {
 210                 compatible = "st,stm32mp1-pll";
 211                 reg = <2>;
 212                 cfg = < 1 33 1 16 36 PQR(1,1,1) >;
 213                 frac = < 0x1a04 >;
 214                 u-boot,dm-pre-reloc;
 215         };
 216
 217         /* VCO = 600.0 MHz => P = 50, Q = 50, R = 50 */
 218         pll4: st,pll@3 {
 219                 compatible = "st,stm32mp1-pll";
 220                 reg = <3>;
 221                 cfg = < 1 49 5 11 11 PQR(1,1,1) >;
 222                 u-boot,dm-pre-reloc;
 223         };
 224 };
 225
 226 &sdmmc1 {
 227         u-boot,dm-spl;
 228 };
 229
 230 &sdmmc1_b4_pins_a {
 231         u-boot,dm-spl;
 232         pins1 {
 233                 u-boot,dm-spl;
 234         };
 235         pins2 {
 236                 u-boot,dm-spl;
 237         };
 238 };
 239
 240 &sdmmc1_dir_pins_a {
 241         u-boot,dm-spl;
 242         pins1 {
 243                 u-boot,dm-spl;
 244         };
 245         pins2 {
 246                 u-boot,dm-spl;
 247         };
 248 };
 249
 250 &sdmmc2 {
 251         u-boot,dm-spl;
 252 };
 253
 254 &sdmmc2_b4_pins_a {
 255         u-boot,dm-spl;
 256         pins {
 257                 u-boot,dm-spl;
 258         };
 259 };
 260
 261 &sdmmc2_d47_pins_a {
 262         u-boot,dm-spl;
 263         pins {
 264                 u-boot,dm-spl;
 265         };
 266 };
 267
 268 &uart4 {
 269         u-boot,dm-pre-reloc;
 270 };
 271
 272 &uart4_pins_a {
 273         u-boot,dm-pre-reloc;
 274         pins1 {
 275                 u-boot,dm-pre-reloc;
 276         };
 277         pins2 {
 278                 u-boot,dm-pre-reloc;
 279                 /* pull-up on rx to avoid floating level */
 280                 bias-pull-up;
 281         };
 282 };