arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright : STMicroelectronics 2018
   4  */
   5
   6 #include <dt-bindings/clock/stm32mp1-clksrc.h>
   7 #include "stm32mp15-u-boot.dtsi"
   8 #include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
   9
  10 / {
  11         aliases {
  12                 i2c3 = &i2c4;
  13                 mmc0 = &sdmmc1;
  14                 mmc1 = &sdmmc2;
  15         };
  16
  17         config {
  18                 u-boot,boot-led = "heartbeat";
  19                 u-boot,error-led = "error";
  20                 u-boot,mmc-env-partition = "ssbl";
  21                 st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
  22                 st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
  23         };
  24
  25         firmware {
  26                 optee {
  27                         compatible = "linaro,optee-tz";
  28                         method = "smc";
  29                 };
  30         };
  31
  32         reserved-memory {
  33                 optee@fe000000 {
  34                         reg = <0xfe000000 0x02000000>;
  35                         no-map;
  36                 };
  37         };
  38
  39         led {
  40                 red {
  41                         label = "error";
  42                         gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
  43                         default-state = "off";
  44                         status = "okay";
  45                 };
  46         };
  47 };
  48
  49 &clk_hse {
  50         st,digbypass;
  51 };
  52
  53 &i2c4 {
  54         u-boot,dm-pre-reloc;
  55 };
  56
  57 &i2c4_pins_a {
  58         u-boot,dm-pre-reloc;
  59         pins {
  60                 u-boot,dm-pre-reloc;
  61         };
  62 };
  63
  64 &pmic {
  65         u-boot,dm-pre-reloc;
  66 };
  67
  68 &rcc {
  69         st,clksrc = <
  70                 CLK_MPU_PLL1P
  71                 CLK_AXI_PLL2P
  72                 CLK_MCU_PLL3P
  73                 CLK_PLL12_HSE
  74                 CLK_PLL3_HSE
  75                 CLK_PLL4_HSE
  76                 CLK_RTC_LSE
  77                 CLK_MCO1_DISABLED
  78                 CLK_MCO2_DISABLED
  79         >;
  80
  81         st,clkdiv = <
  82                 1 /*MPU*/
  83                 0 /*AXI*/
  84                 0 /*MCU*/
  85                 1 /*APB1*/
  86                 1 /*APB2*/
  87                 1 /*APB3*/
  88                 1 /*APB4*/
  89                 2 /*APB5*/
  90                 23 /*RTC*/
  91                 0 /*MCO1*/
  92                 0 /*MCO2*/
  93         >;
  94
  95         st,pkcs = <
  96                 CLK_CKPER_HSE
  97                 CLK_FMC_ACLK
  98                 CLK_QSPI_ACLK
  99                 CLK_ETH_DISABLED
 100                 CLK_SDMMC12_PLL4P
 101                 CLK_DSI_DSIPLL
 102                 CLK_STGEN_HSE
 103                 CLK_USBPHY_HSE
 104                 CLK_SPI2S1_PLL3Q
 105                 CLK_SPI2S23_PLL3Q
 106                 CLK_SPI45_HSI
 107                 CLK_SPI6_HSI
 108                 CLK_I2C46_HSI
 109                 CLK_SDMMC3_PLL4P
 110                 CLK_USBO_USBPHY
 111                 CLK_ADC_CKPER
 112                 CLK_CEC_LSE
 113                 CLK_I2C12_HSI
 114                 CLK_I2C35_HSI
 115                 CLK_UART1_HSI
 116                 CLK_UART24_HSI
 117                 CLK_UART35_HSI
 118                 CLK_UART6_HSI
 119                 CLK_UART78_HSI
 120                 CLK_SPDIF_PLL4P
 121                 CLK_FDCAN_PLL4R
 122                 CLK_SAI1_PLL3Q
 123                 CLK_SAI2_PLL3Q
 124                 CLK_SAI3_PLL3Q
 125                 CLK_SAI4_PLL3Q
 126                 CLK_RNG1_LSI
 127                 CLK_RNG2_LSI
 128                 CLK_LPTIM1_PCLK1
 129                 CLK_LPTIM23_PCLK3
 130                 CLK_LPTIM45_LSE
 131         >;
 132
 133         /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
 134         pll2: st,pll@1 {
 135                 compatible = "st,stm32mp1-pll";
 136                 reg = <1>;
 137                 cfg = < 2 65 1 0 0 PQR(1,1,1) >;
 138                 frac = < 0x1400 >;
 139                 u-boot,dm-pre-reloc;
 140         };
 141
 142         /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
 143         pll3: st,pll@2 {
 144                 compatible = "st,stm32mp1-pll";
 145                 reg = <2>;
 146                 cfg = < 1 33 1 16 36 PQR(1,1,1) >;
 147                 frac = < 0x1a04 >;
 148                 u-boot,dm-pre-reloc;
 149         };
 150
 151         /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
 152         pll4: st,pll@3 {
 153                 compatible = "st,stm32mp1-pll";
 154                 reg = <3>;
 155                 cfg = < 3 98 5 7 7 PQR(1,1,1) >;
 156                 u-boot,dm-pre-reloc;
 157         };
 158 };
 159
 160 &sdmmc1 {
 161         u-boot,dm-spl;
 162 };
 163
 164 &sdmmc1_b4_pins_a {
 165         u-boot,dm-spl;
 166         pins1 {
 167                 u-boot,dm-spl;
 168         };
 169         pins2 {
 170                 u-boot,dm-spl;
 171         };
 172 };
 173
 174 &sdmmc1_dir_pins_a {
 175         u-boot,dm-spl;
 176         pins1 {
 177                 u-boot,dm-spl;
 178         };
 179         pins2 {
 180                 u-boot,dm-spl;
 181         };
 182 };
 183
 184 &sdmmc2 {
 185         u-boot,dm-spl;
 186 };
 187
 188 &sdmmc2_b4_pins_a {
 189         u-boot,dm-spl;
 190         pins1 {
 191                 u-boot,dm-spl;
 192         };
 193         pins2 {
 194                 u-boot,dm-spl;
 195         };
 196 };
 197
 198 &sdmmc2_d47_pins_a {
 199         u-boot,dm-spl;
 200         pins {
 201                 u-boot,dm-spl;
 202         };
 203 };
 204
 205 &uart4 {
 206         u-boot,dm-pre-reloc;
 207 };
 208
 209 &uart4_pins_a {
 210         u-boot,dm-pre-reloc;
 211         pins1 {
 212                 u-boot,dm-pre-reloc;
 213         };
 214         pins2 {
 215                 u-boot,dm-pre-reloc;
 216                 /* pull-up on rx to avoid floating level */
 217                 bias-pull-up;
 218         };
 219 };