arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright : STMicroelectronics 2018
   4  */
   5
   6 #include <dt-bindings/clock/stm32mp1-clksrc.h>
   7 #include "stm32mp157-u-boot.dtsi"
   8 #include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
   9
  10 / {
  11         aliases {
  12                 i2c3 = &i2c4;
  13                 mmc0 = &sdmmc1;
  14         };
  15         config {
  16                 u-boot,boot-led = "heartbeat";
  17                 u-boot,error-led = "error";
  18                 st,adc_usb_pd = <&adc1 18>, <&adc1 19>;
  19         };
  20         led {
  21                 red {
  22                         label = "error";
  23                         gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
  24                         default-state = "off";
  25                         status = "okay";
  26                 };
  27
  28                 blue {
  29                         default-state = "on";
  30                 };
  31         };
  32 };
  33
  34 &adc {
  35         pinctrl-names = "default";
  36         pinctrl-0 = <&adc12_usb_pwr_pins_a>;
  37         vdd-supply = <&vdd>;
  38         vdda-supply = <&vdd>;
  39         vref-supply = <&vrefbuf>;
  40         status = "okay";
  41         adc1: adc@0 {
  42                 /*
  43                  * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in18 & in19.
  44                  * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C:
  45                  * 5 * (56 + 47kOhms) * 5pF => 2.5us.
  46                  * Use arbitrary margin here (e.g. 5µs).
  47                  */
  48                 st,min-sample-time-nsecs = <5000>;
  49                 /* ANA0, ANA1, USB Type-C CC1 & CC2 */
  50                 st,adc-channels = <0 1 18 19>;
  51                 status = "okay";
  52         };
  53 };
  54
  55 &clk_hse {
  56         st,digbypass;
  57 };
  58
  59 &i2c4 {
  60         u-boot,dm-pre-reloc;
  61 };
  62
  63 &i2c4_pins_a {
  64         u-boot,dm-pre-reloc;
  65         pins {
  66                 u-boot,dm-pre-reloc;
  67         };
  68 };
  69
  70 &pmic {
  71         u-boot,dm-pre-reloc;
  72 };
  73
  74 &rcc {
  75         st,clksrc = <
  76                 CLK_MPU_PLL1P
  77                 CLK_AXI_PLL2P
  78                 CLK_MCU_PLL3P
  79                 CLK_PLL12_HSE
  80                 CLK_PLL3_HSE
  81                 CLK_PLL4_HSE
  82                 CLK_RTC_LSE
  83                 CLK_MCO1_DISABLED
  84                 CLK_MCO2_DISABLED
  85         >;
  86
  87         st,clkdiv = <
  88                 1 /*MPU*/
  89                 0 /*AXI*/
  90                 0 /*MCU*/
  91                 1 /*APB1*/
  92                 1 /*APB2*/
  93                 1 /*APB3*/
  94                 1 /*APB4*/
  95                 2 /*APB5*/
  96                 23 /*RTC*/
  97                 0 /*MCO1*/
  98                 0 /*MCO2*/
  99         >;
 100
 101         st,pkcs = <
 102                 CLK_CKPER_HSE
 103                 CLK_FMC_ACLK
 104                 CLK_QSPI_ACLK
 105                 CLK_ETH_DISABLED
 106                 CLK_SDMMC12_PLL4P
 107                 CLK_DSI_DSIPLL
 108                 CLK_STGEN_HSE
 109                 CLK_USBPHY_HSE
 110                 CLK_SPI2S1_PLL3Q
 111                 CLK_SPI2S23_PLL3Q
 112                 CLK_SPI45_HSI
 113                 CLK_SPI6_HSI
 114                 CLK_I2C46_HSI
 115                 CLK_SDMMC3_PLL4P
 116                 CLK_USBO_USBPHY
 117                 CLK_ADC_CKPER
 118                 CLK_CEC_LSE
 119                 CLK_I2C12_HSI
 120                 CLK_I2C35_HSI
 121                 CLK_UART1_HSI
 122                 CLK_UART24_HSI
 123                 CLK_UART35_HSI
 124                 CLK_UART6_HSI
 125                 CLK_UART78_HSI
 126                 CLK_SPDIF_PLL4P
 127                 CLK_FDCAN_PLL4Q
 128                 CLK_SAI1_PLL3Q
 129                 CLK_SAI2_PLL3Q
 130                 CLK_SAI3_PLL3Q
 131                 CLK_SAI4_PLL3Q
 132                 CLK_RNG1_LSI
 133                 CLK_RNG2_LSI
 134                 CLK_LPTIM1_PCLK1
 135                 CLK_LPTIM23_PCLK3
 136                 CLK_LPTIM45_LSE
 137         >;
 138
 139         /* VCO = 1300.0 MHz => P = 650 (CPU) */
 140         pll1: st,pll@0 {
 141                 cfg = < 2 80 0 0 0 PQR(1,0,0) >;
 142                 frac = < 0x800 >;
 143                 u-boot,dm-pre-reloc;
 144         };
 145
 146         /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
 147         pll2: st,pll@1 {
 148                 cfg = < 2 65 1 0 0 PQR(1,1,1) >;
 149                 frac = < 0x1400 >;
 150                 u-boot,dm-pre-reloc;
 151         };
 152
 153         /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
 154         pll3: st,pll@2 {
 155                 cfg = < 1 33 1 16 36 PQR(1,1,1) >;
 156                 frac = < 0x1a04 >;
 157                 u-boot,dm-pre-reloc;
 158         };
 159
 160         /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
 161         pll4: st,pll@3 {
 162                 cfg = < 3 98 5 7 7 PQR(1,1,1) >;
 163                 u-boot,dm-pre-reloc;
 164         };
 165 };
 166
 167 &sdmmc1 {
 168         u-boot,dm-spl;
 169 };
 170
 171 &sdmmc1_b4_pins_a {
 172         u-boot,dm-spl;
 173         pins {
 174                 u-boot,dm-spl;
 175         };
 176 };
 177
 178 &uart4 {
 179         u-boot,dm-pre-reloc;
 180 };
 181
 182 &uart4_pins_a {
 183         u-boot,dm-pre-reloc;
 184         pins1 {
 185                 u-boot,dm-pre-reloc;
 186         };
 187         pins2 {
 188                 u-boot,dm-pre-reloc;
 189         };
 190 };
 191
 192 &usbotg_hs {
 193         usb1600;
 194         hnp-srp-disable;
 195 };
 196
 197 &v3v3 {
 198         regulator-always-on;
 199 };