arch/arm/dts/stm32mp151.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /*
   3  * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
   4  * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
   5  */
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/stm32mp1-clks.h>
   8 #include <dt-bindings/reset/stm32mp1-resets.h>
   9
  10 / {
  11         #address-cells = <1>;
  12         #size-cells = <1>;
  13
  14         cpus {
  15                 #address-cells = <1>;
  16                 #size-cells = <0>;
  17
  18                 cpu0: cpu@0 {
  19                         compatible = "arm,cortex-a7";
  20                         clock-frequency = <650000000>;
  21                         device_type = "cpu";
  22                         reg = <0>;
  23                         operating-points-v2 = <&cpu0_opp_table>;
  24                         nvmem-cells = <&part_number_otp>;
  25                         nvmem-cell-names = "part_number";
  26                 };
  27         };
  28
  29         cpu0_opp_table: cpu0-opp-table {
  30                 compatible = "operating-points-v2";
  31                 opp-shared;
  32                 opp-650000000 {
  33                         opp-hz = /bits/ 64 <650000000>;
  34                         opp-microvolt = <1200000>;
  35                         opp-supported-hw = <0x1>;
  36                 };
  37                 opp-800000000 {
  38                         opp-hz = /bits/ 64 <800000000>;
  39                         opp-microvolt = <1350000>;
  40                         opp-supported-hw = <0x2>;
  41                 };
  42         };
  43
  44         arm-pmu {
  45                 compatible = "arm,cortex-a7-pmu";
  46                 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
  47                 interrupt-affinity = <&cpu0>;
  48                 interrupt-parent = <&intc>;
  49         };
  50
  51         psci {
  52                 compatible = "arm,psci-1.0";
  53                 method = "smc";
  54         };
  55
  56         intc: interrupt-controller@a0021000 {
  57                 compatible = "arm,cortex-a7-gic";
  58                 #interrupt-cells = <3>;
  59                 interrupt-controller;
  60                 reg = <0xa0021000 0x1000>,
  61                       <0xa0022000 0x2000>;
  62         };
  63
  64         timer {
  65                 compatible = "arm,armv7-timer";
  66                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
  67                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
  68                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
  69                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
  70                 interrupt-parent = <&intc>;
  71         };
  72
  73         clocks {
  74                 clk_hse: clk-hse {
  75                         #clock-cells = <0>;
  76                         compatible = "fixed-clock";
  77                         clock-frequency = <24000000>;
  78                 };
  79
  80                 clk_hsi: clk-hsi {
  81                         #clock-cells = <0>;
  82                         compatible = "fixed-clock";
  83                         clock-frequency = <64000000>;
  84                 };
  85
  86                 clk_lse: clk-lse {
  87                         #clock-cells = <0>;
  88                         compatible = "fixed-clock";
  89                         clock-frequency = <32768>;
  90                 };
  91
  92                 clk_lsi: clk-lsi {
  93                         #clock-cells = <0>;
  94                         compatible = "fixed-clock";
  95                         clock-frequency = <32000>;
  96                 };
  97
  98                 clk_csi: clk-csi {
  99                         #clock-cells = <0>;
 100                         compatible = "fixed-clock";
 101                         clock-frequency = <4000000>;
 102                 };
 103         };
 104
 105         thermal-zones {
 106                 cpu_thermal: cpu-thermal {
 107                         polling-delay-passive = <0>;
 108                         polling-delay = <0>;
 109                         thermal-sensors = <&dts>;
 110
 111                         trips {
 112                                 cpu_alert1: cpu-alert1 {
 113                                         temperature = <85000>;
 114                                         hysteresis = <0>;
 115                                         type = "passive";
 116                                 };
 117
 118                                 cpu-crit {
 119                                         temperature = <120000>;
 120                                         hysteresis = <0>;
 121                                         type = "critical";
 122                                 };
 123                         };
 124
 125                         cooling-maps {
 126                         };
 127                 };
 128         };
 129
 130         booster: regulator-booster {
 131                 compatible = "st,stm32mp1-booster";
 132                 st,syscfg = <&syscfg>;
 133                 status = "disabled";
 134         };
 135
 136         soc {
 137                 compatible = "simple-bus";
 138                 #address-cells = <1>;
 139                 #size-cells = <1>;
 140                 interrupt-parent = <&intc>;
 141                 ranges;
 142
 143                 timers2: timer@40000000 {
 144                         #address-cells = <1>;
 145                         #size-cells = <0>;
 146                         compatible = "st,stm32-timers";
 147                         reg = <0x40000000 0x400>;
 148                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 149                         interrupt-names = "global";
 150                         clocks = <&rcc TIM2_K>;
 151                         clock-names = "int";
 152                         dmas = <&dmamux1 18 0x400 0x1>,
 153                                <&dmamux1 19 0x400 0x1>,
 154                                <&dmamux1 20 0x400 0x1>,
 155                                <&dmamux1 21 0x400 0x1>,
 156                                <&dmamux1 22 0x400 0x1>;
 157                         dma-names = "ch1", "ch2", "ch3", "ch4", "up";
 158                         status = "disabled";
 159
 160                         pwm {
 161                                 compatible = "st,stm32-pwm";
 162                                 #pwm-cells = <3>;
 163                                 status = "disabled";
 164                         };
 165
 166                         timer@1 {
 167                                 compatible = "st,stm32h7-timer-trigger";
 168                                 reg = <1>;
 169                                 status = "disabled";
 170                         };
 171
 172                         counter {
 173                                 compatible = "st,stm32-timer-counter";
 174                                 status = "disabled";
 175                         };
 176                 };
 177
 178                 timers3: timer@40001000 {
 179                         #address-cells = <1>;
 180                         #size-cells = <0>;
 181                         compatible = "st,stm32-timers";
 182                         reg = <0x40001000 0x400>;
 183                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 184                         interrupt-names = "global";
 185                         clocks = <&rcc TIM3_K>;
 186                         clock-names = "int";
 187                         dmas = <&dmamux1 23 0x400 0x1>,
 188                                <&dmamux1 24 0x400 0x1>,
 189                                <&dmamux1 25 0x400 0x1>,
 190                                <&dmamux1 26 0x400 0x1>,
 191                                <&dmamux1 27 0x400 0x1>,
 192                                <&dmamux1 28 0x400 0x1>;
 193                         dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
 194                         status = "disabled";
 195
 196                         pwm {
 197                                 compatible = "st,stm32-pwm";
 198                                 #pwm-cells = <3>;
 199                                 status = "disabled";
 200                         };
 201
 202                         timer@2 {
 203                                 compatible = "st,stm32h7-timer-trigger";
 204                                 reg = <2>;
 205                                 status = "disabled";
 206                         };
 207
 208                         counter {
 209                                 compatible = "st,stm32-timer-counter";
 210                                 status = "disabled";
 211                         };
 212                 };
 213
 214                 timers4: timer@40002000 {
 215                         #address-cells = <1>;
 216                         #size-cells = <0>;
 217                         compatible = "st,stm32-timers";
 218                         reg = <0x40002000 0x400>;
 219                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 220                         interrupt-names = "global";
 221                         clocks = <&rcc TIM4_K>;
 222                         clock-names = "int";
 223                         dmas = <&dmamux1 29 0x400 0x1>,
 224                                <&dmamux1 30 0x400 0x1>,
 225                                <&dmamux1 31 0x400 0x1>,
 226                                <&dmamux1 32 0x400 0x1>;
 227                         dma-names = "ch1", "ch2", "ch3", "ch4";
 228                         status = "disabled";
 229
 230                         pwm {
 231                                 compatible = "st,stm32-pwm";
 232                                 #pwm-cells = <3>;
 233                                 status = "disabled";
 234                         };
 235
 236                         timer@3 {
 237                                 compatible = "st,stm32h7-timer-trigger";
 238                                 reg = <3>;
 239                                 status = "disabled";
 240                         };
 241
 242                         counter {
 243                                 compatible = "st,stm32-timer-counter";
 244                                 status = "disabled";
 245                         };
 246                 };
 247
 248                 timers5: timer@40003000 {
 249                         #address-cells = <1>;
 250                         #size-cells = <0>;
 251                         compatible = "st,stm32-timers";
 252                         reg = <0x40003000 0x400>;
 253                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 254                         interrupt-names = "global";
 255                         clocks = <&rcc TIM5_K>;
 256                         clock-names = "int";
 257                         dmas = <&dmamux1 55 0x400 0x1>,
 258                                <&dmamux1 56 0x400 0x1>,
 259                                <&dmamux1 57 0x400 0x1>,
 260                                <&dmamux1 58 0x400 0x1>,
 261                                <&dmamux1 59 0x400 0x1>,
 262                                <&dmamux1 60 0x400 0x1>;
 263                         dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
 264                         status = "disabled";
 265
 266                         pwm {
 267                                 compatible = "st,stm32-pwm";
 268                                 #pwm-cells = <3>;
 269                                 status = "disabled";
 270                         };
 271
 272                         timer@4 {
 273                                 compatible = "st,stm32h7-timer-trigger";
 274                                 reg = <4>;
 275                                 status = "disabled";
 276                         };
 277
 278                         counter {
 279                                 compatible = "st,stm32-timer-counter";
 280                                 status = "disabled";
 281                         };
 282                 };
 283
 284                 timers6: timer@40004000 {
 285                         #address-cells = <1>;
 286                         #size-cells = <0>;
 287                         compatible = "st,stm32-timers";
 288                         reg = <0x40004000 0x400>;
 289                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 290                         interrupt-names = "global";
 291                         clocks = <&rcc TIM6_K>;
 292                         clock-names = "int";
 293                         dmas = <&dmamux1 69 0x400 0x1>;
 294                         dma-names = "up";
 295                         status = "disabled";
 296
 297                         timer@5 {
 298                                 compatible = "st,stm32h7-timer-trigger";
 299                                 reg = <5>;
 300                                 status = "disabled";
 301                         };
 302                 };
 303
 304                 timers7: timer@40005000 {
 305                         #address-cells = <1>;
 306                         #size-cells = <0>;
 307                         compatible = "st,stm32-timers";
 308                         reg = <0x40005000 0x400>;
 309                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 310                         interrupt-names = "global";
 311                         clocks = <&rcc TIM7_K>;
 312                         clock-names = "int";
 313                         dmas = <&dmamux1 70 0x400 0x1>;
 314                         dma-names = "up";
 315                         status = "disabled";
 316
 317                         timer@6 {
 318                                 compatible = "st,stm32h7-timer-trigger";
 319                                 reg = <6>;
 320                                 status = "disabled";
 321                         };
 322                 };
 323
 324                 timers12: timer@40006000 {
 325                         #address-cells = <1>;
 326                         #size-cells = <0>;
 327                         compatible = "st,stm32-timers";
 328                         reg = <0x40006000 0x400>;
 329                         interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 330                         interrupt-names = "global";
 331                         clocks = <&rcc TIM12_K>;
 332                         clock-names = "int";
 333                         status = "disabled";
 334
 335                         pwm {
 336                                 compatible = "st,stm32-pwm";
 337                                 #pwm-cells = <3>;
 338                                 status = "disabled";
 339                         };
 340
 341                         timer@11 {
 342                                 compatible = "st,stm32h7-timer-trigger";
 343                                 reg = <11>;
 344                                 status = "disabled";
 345                         };
 346                 };
 347
 348                 timers13: timer@40007000 {
 349                         #address-cells = <1>;
 350                         #size-cells = <0>;
 351                         compatible = "st,stm32-timers";
 352                         reg = <0x40007000 0x400>;
 353                         interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
 354                         interrupt-names = "global";
 355                         clocks = <&rcc TIM13_K>;
 356                         clock-names = "int";
 357                         status = "disabled";
 358
 359                         pwm {
 360                                 compatible = "st,stm32-pwm";
 361                                 #pwm-cells = <3>;
 362                                 status = "disabled";
 363                         };
 364
 365                         timer@12 {
 366                                 compatible = "st,stm32h7-timer-trigger";
 367                                 reg = <12>;
 368                                 status = "disabled";
 369                         };
 370                 };
 371
 372                 timers14: timer@40008000 {
 373                         #address-cells = <1>;
 374                         #size-cells = <0>;
 375                         compatible = "st,stm32-timers";
 376                         reg = <0x40008000 0x400>;
 377                         interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
 378                         interrupt-names = "global";
 379                         clocks = <&rcc TIM14_K>;
 380                         clock-names = "int";
 381                         status = "disabled";
 382
 383                         pwm {
 384                                 compatible = "st,stm32-pwm";
 385                                 #pwm-cells = <3>;
 386                                 status = "disabled";
 387                         };
 388
 389                         timer@13 {
 390                                 compatible = "st,stm32h7-timer-trigger";
 391                                 reg = <13>;
 392                                 status = "disabled";
 393                         };
 394                 };
 395
 396                 lptimer1: timer@40009000 {
 397                         #address-cells = <1>;
 398                         #size-cells = <0>;
 399                         compatible = "st,stm32-lptimer";
 400                         reg = <0x40009000 0x400>;
 401                         interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>;
 402                         clocks = <&rcc LPTIM1_K>;
 403                         clock-names = "mux";
 404                         wakeup-source;
 405                         status = "disabled";
 406
 407                         pwm {
 408                                 compatible = "st,stm32-pwm-lp";
 409                                 #pwm-cells = <3>;
 410                                 status = "disabled";
 411                         };
 412
 413                         trigger@0 {
 414                                 compatible = "st,stm32-lptimer-trigger";
 415                                 reg = <0>;
 416                                 status = "disabled";
 417                         };
 418
 419                         counter {
 420                                 compatible = "st,stm32-lptimer-counter";
 421                                 status = "disabled";
 422                         };
 423                 };
 424
 425                 spi2: spi@4000b000 {
 426                         #address-cells = <1>;
 427                         #size-cells = <0>;
 428                         compatible = "st,stm32h7-spi";
 429                         reg = <0x4000b000 0x400>;
 430                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 431                         clocks = <&rcc SPI2_K>;
 432                         resets = <&rcc SPI2_R>;
 433                         dmas = <&dmamux1 39 0x400 0x05>,
 434                                <&dmamux1 40 0x400 0x05>;
 435                         dma-names = "rx", "tx";
 436                         status = "disabled";
 437                 };
 438
 439                 i2s2: audio-controller@4000b000 {
 440                         compatible = "st,stm32h7-i2s";
 441                         #sound-dai-cells = <0>;
 442                         reg = <0x4000b000 0x400>;
 443                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 444                         dmas = <&dmamux1 39 0x400 0x01>,
 445                                <&dmamux1 40 0x400 0x01>;
 446                         dma-names = "rx", "tx";
 447                         status = "disabled";
 448                 };
 449
 450                 spi3: spi@4000c000 {
 451                         #address-cells = <1>;
 452                         #size-cells = <0>;
 453                         compatible = "st,stm32h7-spi";
 454                         reg = <0x4000c000 0x400>;
 455                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 456                         clocks = <&rcc SPI3_K>;
 457                         resets = <&rcc SPI3_R>;
 458                         dmas = <&dmamux1 61 0x400 0x05>,
 459                                <&dmamux1 62 0x400 0x05>;
 460                         dma-names = "rx", "tx";
 461                         status = "disabled";
 462                 };
 463
 464                 i2s3: audio-controller@4000c000 {
 465                         compatible = "st,stm32h7-i2s";
 466                         #sound-dai-cells = <0>;
 467                         reg = <0x4000c000 0x400>;
 468                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 469                         dmas = <&dmamux1 61 0x400 0x01>,
 470                                <&dmamux1 62 0x400 0x01>;
 471                         dma-names = "rx", "tx";
 472                         status = "disabled";
 473                 };
 474
 475                 spdifrx: audio-controller@4000d000 {
 476                         compatible = "st,stm32h7-spdifrx";
 477                         #sound-dai-cells = <0>;
 478                         reg = <0x4000d000 0x400>;
 479                         clocks = <&rcc SPDIF_K>;
 480                         clock-names = "kclk";
 481                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 482                         dmas = <&dmamux1 93 0x400 0x01>,
 483                                <&dmamux1 94 0x400 0x01>;
 484                         dma-names = "rx", "rx-ctrl";
 485                         status = "disabled";
 486                 };
 487
 488                 usart2: serial@4000e000 {
 489                         compatible = "st,stm32h7-uart";
 490                         reg = <0x4000e000 0x400>;
 491                         interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
 492                         clocks = <&rcc USART2_K>;
 493                         wakeup-source;
 494                         dmas = <&dmamux1 43 0x400 0x15>,
 495                                <&dmamux1 44 0x400 0x11>;
 496                         dma-names = "rx", "tx";
 497                         status = "disabled";
 498                 };
 499
 500                 usart3: serial@4000f000 {
 501                         compatible = "st,stm32h7-uart";
 502                         reg = <0x4000f000 0x400>;
 503                         interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
 504                         clocks = <&rcc USART3_K>;
 505                         wakeup-source;
 506                         dmas = <&dmamux1 45 0x400 0x15>,
 507                                <&dmamux1 46 0x400 0x11>;
 508                         dma-names = "rx", "tx";
 509                         status = "disabled";
 510                 };
 511
 512                 uart4: serial@40010000 {
 513                         compatible = "st,stm32h7-uart";
 514                         reg = <0x40010000 0x400>;
 515                         interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
 516                         clocks = <&rcc UART4_K>;
 517                         wakeup-source;
 518                         dmas = <&dmamux1 63 0x400 0x15>,
 519                                <&dmamux1 64 0x400 0x11>;
 520                         dma-names = "rx", "tx";
 521                         status = "disabled";
 522                 };
 523
 524                 uart5: serial@40011000 {
 525                         compatible = "st,stm32h7-uart";
 526                         reg = <0x40011000 0x400>;
 527                         interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
 528                         clocks = <&rcc UART5_K>;
 529                         wakeup-source;
 530                         dmas = <&dmamux1 65 0x400 0x15>,
 531                                <&dmamux1 66 0x400 0x11>;
 532                         dma-names = "rx", "tx";
 533                         status = "disabled";
 534                 };
 535
 536                 i2c1: i2c@40012000 {
 537                         compatible = "st,stm32mp15-i2c";
 538                         reg = <0x40012000 0x400>;
 539                         interrupt-names = "event", "error";
 540                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
 541                                      <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 542                         clocks = <&rcc I2C1_K>;
 543                         resets = <&rcc I2C1_R>;
 544                         #address-cells = <1>;
 545                         #size-cells = <0>;
 546                         st,syscfg-fmp = <&syscfg 0x4 0x1>;
 547                         wakeup-source;
 548                         i2c-analog-filter;
 549                         status = "disabled";
 550                 };
 551
 552                 i2c2: i2c@40013000 {
 553                         compatible = "st,stm32mp15-i2c";
 554                         reg = <0x40013000 0x400>;
 555                         interrupt-names = "event", "error";
 556                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 557                                      <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 558                         clocks = <&rcc I2C2_K>;
 559                         resets = <&rcc I2C2_R>;
 560                         #address-cells = <1>;
 561                         #size-cells = <0>;
 562                         st,syscfg-fmp = <&syscfg 0x4 0x2>;
 563                         wakeup-source;
 564                         i2c-analog-filter;
 565                         status = "disabled";
 566                 };
 567
 568                 i2c3: i2c@40014000 {
 569                         compatible = "st,stm32mp15-i2c";
 570                         reg = <0x40014000 0x400>;
 571                         interrupt-names = "event", "error";
 572                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 573                                      <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 574                         clocks = <&rcc I2C3_K>;
 575                         resets = <&rcc I2C3_R>;
 576                         #address-cells = <1>;
 577                         #size-cells = <0>;
 578                         st,syscfg-fmp = <&syscfg 0x4 0x4>;
 579                         wakeup-source;
 580                         i2c-analog-filter;
 581                         status = "disabled";
 582                 };
 583
 584                 i2c5: i2c@40015000 {
 585                         compatible = "st,stm32mp15-i2c";
 586                         reg = <0x40015000 0x400>;
 587                         interrupt-names = "event", "error";
 588                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 589                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 590                         clocks = <&rcc I2C5_K>;
 591                         resets = <&rcc I2C5_R>;
 592                         #address-cells = <1>;
 593                         #size-cells = <0>;
 594                         st,syscfg-fmp = <&syscfg 0x4 0x10>;
 595                         wakeup-source;
 596                         i2c-analog-filter;
 597                         status = "disabled";
 598                 };
 599
 600                 cec: cec@40016000 {
 601                         compatible = "st,stm32-cec";
 602                         reg = <0x40016000 0x400>;
 603                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 604                         clocks = <&rcc CEC_K>, <&rcc CEC>;
 605                         clock-names = "cec", "hdmi-cec";
 606                         status = "disabled";
 607                 };
 608
 609                 dac: dac@40017000 {
 610                         compatible = "st,stm32h7-dac-core";
 611                         reg = <0x40017000 0x400>;
 612                         clocks = <&rcc DAC12>;
 613                         clock-names = "pclk";
 614                         #address-cells = <1>;
 615                         #size-cells = <0>;
 616                         status = "disabled";
 617
 618                         dac1: dac@1 {
 619                                 compatible = "st,stm32-dac";
 620                                 #io-channel-cells = <1>;
 621                                 reg = <1>;
 622                                 status = "disabled";
 623                         };
 624
 625                         dac2: dac@2 {
 626                                 compatible = "st,stm32-dac";
 627                                 #io-channel-cells = <1>;
 628                                 reg = <2>;
 629                                 status = "disabled";
 630                         };
 631                 };
 632
 633                 uart7: serial@40018000 {
 634                         compatible = "st,stm32h7-uart";
 635                         reg = <0x40018000 0x400>;
 636                         interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
 637                         clocks = <&rcc UART7_K>;
 638                         wakeup-source;
 639                         dmas = <&dmamux1 79 0x400 0x15>,
 640                                <&dmamux1 80 0x400 0x11>;
 641                         dma-names = "rx", "tx";
 642                         status = "disabled";
 643                 };
 644
 645                 uart8: serial@40019000 {
 646                         compatible = "st,stm32h7-uart";
 647                         reg = <0x40019000 0x400>;
 648                         interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
 649                         clocks = <&rcc UART8_K>;
 650                         wakeup-source;
 651                         dmas = <&dmamux1 81 0x400 0x15>,
 652                                <&dmamux1 82 0x400 0x11>;
 653                         dma-names = "rx", "tx";
 654                         status = "disabled";
 655                 };
 656
 657                 timers1: timer@44000000 {
 658                         #address-cells = <1>;
 659                         #size-cells = <0>;
 660                         compatible = "st,stm32-timers";
 661                         reg = <0x44000000 0x400>;
 662                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
 663                                      <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
 664                                      <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
 665                                      <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 666                         interrupt-names = "brk", "up", "trg-com", "cc";
 667                         clocks = <&rcc TIM1_K>;
 668                         clock-names = "int";
 669                         dmas = <&dmamux1 11 0x400 0x1>,
 670                                <&dmamux1 12 0x400 0x1>,
 671                                <&dmamux1 13 0x400 0x1>,
 672                                <&dmamux1 14 0x400 0x1>,
 673                                <&dmamux1 15 0x400 0x1>,
 674                                <&dmamux1 16 0x400 0x1>,
 675                                <&dmamux1 17 0x400 0x1>;
 676                         dma-names = "ch1", "ch2", "ch3", "ch4",
 677                                     "up", "trig", "com";
 678                         status = "disabled";
 679
 680                         pwm {
 681                                 compatible = "st,stm32-pwm";
 682                                 #pwm-cells = <3>;
 683                                 status = "disabled";
 684                         };
 685
 686                         timer@0 {
 687                                 compatible = "st,stm32h7-timer-trigger";
 688                                 reg = <0>;
 689                                 status = "disabled";
 690                         };
 691
 692                         counter {
 693                                 compatible = "st,stm32-timer-counter";
 694                                 status = "disabled";
 695                         };
 696                 };
 697
 698                 timers8: timer@44001000 {
 699                         #address-cells = <1>;
 700                         #size-cells = <0>;
 701                         compatible = "st,stm32-timers";
 702                         reg = <0x44001000 0x400>;
 703                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
 704                                      <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
 705                                      <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
 706                                      <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 707                         interrupt-names = "brk", "up", "trg-com", "cc";
 708                         clocks = <&rcc TIM8_K>;
 709                         clock-names = "int";
 710                         dmas = <&dmamux1 47 0x400 0x1>,
 711                                <&dmamux1 48 0x400 0x1>,
 712                                <&dmamux1 49 0x400 0x1>,
 713                                <&dmamux1 50 0x400 0x1>,
 714                                <&dmamux1 51 0x400 0x1>,
 715                                <&dmamux1 52 0x400 0x1>,
 716                                <&dmamux1 53 0x400 0x1>;
 717                         dma-names = "ch1", "ch2", "ch3", "ch4",
 718                                     "up", "trig", "com";
 719                         status = "disabled";
 720
 721                         pwm {
 722                                 compatible = "st,stm32-pwm";
 723                                 #pwm-cells = <3>;
 724                                 status = "disabled";
 725                         };
 726
 727                         timer@7 {
 728                                 compatible = "st,stm32h7-timer-trigger";
 729                                 reg = <7>;
 730                                 status = "disabled";
 731                         };
 732
 733                         counter {
 734                                 compatible = "st,stm32-timer-counter";
 735                                 status = "disabled";
 736                         };
 737                 };
 738
 739                 usart6: serial@44003000 {
 740                         compatible = "st,stm32h7-uart";
 741                         reg = <0x44003000 0x400>;
 742                         interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
 743                         clocks = <&rcc USART6_K>;
 744                         wakeup-source;
 745                         dmas = <&dmamux1 71 0x400 0x15>,
 746                                <&dmamux1 72 0x400 0x11>;
 747                         dma-names = "rx", "tx";
 748                         status = "disabled";
 749                 };
 750
 751                 spi1: spi@44004000 {
 752                         #address-cells = <1>;
 753                         #size-cells = <0>;
 754                         compatible = "st,stm32h7-spi";
 755                         reg = <0x44004000 0x400>;
 756                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 757                         clocks = <&rcc SPI1_K>;
 758                         resets = <&rcc SPI1_R>;
 759                         dmas = <&dmamux1 37 0x400 0x05>,
 760                                <&dmamux1 38 0x400 0x05>;
 761                         dma-names = "rx", "tx";
 762                         status = "disabled";
 763                 };
 764
 765                 i2s1: audio-controller@44004000 {
 766                         compatible = "st,stm32h7-i2s";
 767                         #sound-dai-cells = <0>;
 768                         reg = <0x44004000 0x400>;
 769                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 770                         dmas = <&dmamux1 37 0x400 0x01>,
 771                                <&dmamux1 38 0x400 0x01>;
 772                         dma-names = "rx", "tx";
 773                         status = "disabled";
 774                 };
 775
 776                 spi4: spi@44005000 {
 777                         #address-cells = <1>;
 778                         #size-cells = <0>;
 779                         compatible = "st,stm32h7-spi";
 780                         reg = <0x44005000 0x400>;
 781                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 782                         clocks = <&rcc SPI4_K>;
 783                         resets = <&rcc SPI4_R>;
 784                         dmas = <&dmamux1 83 0x400 0x05>,
 785                                <&dmamux1 84 0x400 0x05>;
 786                         dma-names = "rx", "tx";
 787                         status = "disabled";
 788                 };
 789
 790                 timers15: timer@44006000 {
 791                         #address-cells = <1>;
 792                         #size-cells = <0>;
 793                         compatible = "st,stm32-timers";
 794                         reg = <0x44006000 0x400>;
 795                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 796                         interrupt-names = "global";
 797                         clocks = <&rcc TIM15_K>;
 798                         clock-names = "int";
 799                         dmas = <&dmamux1 105 0x400 0x1>,
 800                                <&dmamux1 106 0x400 0x1>,
 801                                <&dmamux1 107 0x400 0x1>,
 802                                <&dmamux1 108 0x400 0x1>;
 803                         dma-names = "ch1", "up", "trig", "com";
 804                         status = "disabled";
 805
 806                         pwm {
 807                                 compatible = "st,stm32-pwm";
 808                                 #pwm-cells = <3>;
 809                                 status = "disabled";
 810                         };
 811
 812                         timer@14 {
 813                                 compatible = "st,stm32h7-timer-trigger";
 814                                 reg = <14>;
 815                                 status = "disabled";
 816                         };
 817                 };
 818
 819                 timers16: timer@44007000 {
 820                         #address-cells = <1>;
 821                         #size-cells = <0>;
 822                         compatible = "st,stm32-timers";
 823                         reg = <0x44007000 0x400>;
 824                         interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 825                         interrupt-names = "global";
 826                         clocks = <&rcc TIM16_K>;
 827                         clock-names = "int";
 828                         dmas = <&dmamux1 109 0x400 0x1>,
 829                                <&dmamux1 110 0x400 0x1>;
 830                         dma-names = "ch1", "up";
 831                         status = "disabled";
 832
 833                         pwm {
 834                                 compatible = "st,stm32-pwm";
 835                                 #pwm-cells = <3>;
 836                                 status = "disabled";
 837                         };
 838                         timer@15 {
 839                                 compatible = "st,stm32h7-timer-trigger";
 840                                 reg = <15>;
 841                                 status = "disabled";
 842                         };
 843                 };
 844
 845                 timers17: timer@44008000 {
 846                         #address-cells = <1>;
 847                         #size-cells = <0>;
 848                         compatible = "st,stm32-timers";
 849                         reg = <0x44008000 0x400>;
 850                         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 851                         interrupt-names = "global";
 852                         clocks = <&rcc TIM17_K>;
 853                         clock-names = "int";
 854                         dmas = <&dmamux1 111 0x400 0x1>,
 855                                <&dmamux1 112 0x400 0x1>;
 856                         dma-names = "ch1", "up";
 857                         status = "disabled";
 858
 859                         pwm {
 860                                 compatible = "st,stm32-pwm";
 861                                 #pwm-cells = <3>;
 862                                 status = "disabled";
 863                         };
 864
 865                         timer@16 {
 866                                 compatible = "st,stm32h7-timer-trigger";
 867                                 reg = <16>;
 868                                 status = "disabled";
 869                         };
 870                 };
 871
 872                 spi5: spi@44009000 {
 873                         #address-cells = <1>;
 874                         #size-cells = <0>;
 875                         compatible = "st,stm32h7-spi";
 876                         reg = <0x44009000 0x400>;
 877                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 878                         clocks = <&rcc SPI5_K>;
 879                         resets = <&rcc SPI5_R>;
 880                         dmas = <&dmamux1 85 0x400 0x05>,
 881                                <&dmamux1 86 0x400 0x05>;
 882                         dma-names = "rx", "tx";
 883                         status = "disabled";
 884                 };
 885
 886                 sai1: sai@4400a000 {
 887                         compatible = "st,stm32h7-sai";
 888                         #address-cells = <1>;
 889                         #size-cells = <1>;
 890                         ranges = <0 0x4400a000 0x400>;
 891                         reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
 892                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 893                         resets = <&rcc SAI1_R>;
 894                         status = "disabled";
 895
 896                         sai1a: audio-controller@4400a004 {
 897                                 #sound-dai-cells = <0>;
 898
 899                                 compatible = "st,stm32-sai-sub-a";
 900                                 reg = <0x4 0x20>;
 901                                 clocks = <&rcc SAI1_K>;
 902                                 clock-names = "sai_ck";
 903                                 dmas = <&dmamux1 87 0x400 0x01>;
 904                                 status = "disabled";
 905                         };
 906
 907                         sai1b: audio-controller@4400a024 {
 908                                 #sound-dai-cells = <0>;
 909                                 compatible = "st,stm32-sai-sub-b";
 910                                 reg = <0x24 0x20>;
 911                                 clocks = <&rcc SAI1_K>;
 912                                 clock-names = "sai_ck";
 913                                 dmas = <&dmamux1 88 0x400 0x01>;
 914                                 status = "disabled";
 915                         };
 916                 };
 917
 918                 sai2: sai@4400b000 {
 919                         compatible = "st,stm32h7-sai";
 920                         #address-cells = <1>;
 921                         #size-cells = <1>;
 922                         ranges = <0 0x4400b000 0x400>;
 923                         reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
 924                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 925                         resets = <&rcc SAI2_R>;
 926                         status = "disabled";
 927
 928                         sai2a: audio-controller@4400b004 {
 929                                 #sound-dai-cells = <0>;
 930                                 compatible = "st,stm32-sai-sub-a";
 931                                 reg = <0x4 0x20>;
 932                                 clocks = <&rcc SAI2_K>;
 933                                 clock-names = "sai_ck";
 934                                 dmas = <&dmamux1 89 0x400 0x01>;
 935                                 status = "disabled";
 936                         };
 937
 938                         sai2b: audio-controller@4400b024 {
 939                                 #sound-dai-cells = <0>;
 940                                 compatible = "st,stm32-sai-sub-b";
 941                                 reg = <0x24 0x20>;
 942                                 clocks = <&rcc SAI2_K>;
 943                                 clock-names = "sai_ck";
 944                                 dmas = <&dmamux1 90 0x400 0x01>;
 945                                 status = "disabled";
 946                         };
 947                 };
 948
 949                 sai3: sai@4400c000 {
 950                         compatible = "st,stm32h7-sai";
 951                         #address-cells = <1>;
 952                         #size-cells = <1>;
 953                         ranges = <0 0x4400c000 0x400>;
 954                         reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
 955                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 956                         resets = <&rcc SAI3_R>;
 957                         status = "disabled";
 958
 959                         sai3a: audio-controller@4400c004 {
 960                                 #sound-dai-cells = <0>;
 961                                 compatible = "st,stm32-sai-sub-a";
 962                                 reg = <0x04 0x20>;
 963                                 clocks = <&rcc SAI3_K>;
 964                                 clock-names = "sai_ck";
 965                                 dmas = <&dmamux1 113 0x400 0x01>;
 966                                 status = "disabled";
 967                         };
 968
 969                         sai3b: audio-controller@4400c024 {
 970                                 #sound-dai-cells = <0>;
 971                                 compatible = "st,stm32-sai-sub-b";
 972                                 reg = <0x24 0x20>;
 973                                 clocks = <&rcc SAI3_K>;
 974                                 clock-names = "sai_ck";
 975                                 dmas = <&dmamux1 114 0x400 0x01>;
 976                                 status = "disabled";
 977                         };
 978                 };
 979
 980                 dfsdm: dfsdm@4400d000 {
 981                         compatible = "st,stm32mp1-dfsdm";
 982                         reg = <0x4400d000 0x800>;
 983                         clocks = <&rcc DFSDM_K>;
 984                         clock-names = "dfsdm";
 985                         #address-cells = <1>;
 986                         #size-cells = <0>;
 987                         status = "disabled";
 988
 989                         dfsdm0: filter@0 {
 990                                 compatible = "st,stm32-dfsdm-adc";
 991                                 #io-channel-cells = <1>;
 992                                 reg = <0>;
 993                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 994                                 dmas = <&dmamux1 101 0x400 0x01>;
 995                                 dma-names = "rx";
 996                                 status = "disabled";
 997                         };
 998
 999                         dfsdm1: filter@1 {
1000                                 compatible = "st,stm32-dfsdm-adc";
1001                                 #io-channel-cells = <1>;
1002                                 reg = <1>;
1003                                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1004                                 dmas = <&dmamux1 102 0x400 0x01>;
1005                                 dma-names = "rx";
1006                                 status = "disabled";
1007                         };
1008
1009                         dfsdm2: filter@2 {
1010                                 compatible = "st,stm32-dfsdm-adc";
1011                                 #io-channel-cells = <1>;
1012                                 reg = <2>;
1013                                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1014                                 dmas = <&dmamux1 103 0x400 0x01>;
1015                                 dma-names = "rx";
1016                                 status = "disabled";
1017                         };
1018
1019                         dfsdm3: filter@3 {
1020                                 compatible = "st,stm32-dfsdm-adc";
1021                                 #io-channel-cells = <1>;
1022                                 reg = <3>;
1023                                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1024                                 dmas = <&dmamux1 104 0x400 0x01>;
1025                                 dma-names = "rx";
1026                                 status = "disabled";
1027                         };
1028
1029                         dfsdm4: filter@4 {
1030                                 compatible = "st,stm32-dfsdm-adc";
1031                                 #io-channel-cells = <1>;
1032                                 reg = <4>;
1033                                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
1034                                 dmas = <&dmamux1 91 0x400 0x01>;
1035                                 dma-names = "rx";
1036                                 status = "disabled";
1037                         };
1038
1039                         dfsdm5: filter@5 {
1040                                 compatible = "st,stm32-dfsdm-adc";
1041                                 #io-channel-cells = <1>;
1042                                 reg = <5>;
1043                                 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
1044                                 dmas = <&dmamux1 92 0x400 0x01>;
1045                                 dma-names = "rx";
1046                                 status = "disabled";
1047                         };
1048                 };
1049
1050                 dma1: dma-controller@48000000 {
1051                         compatible = "st,stm32-dma";
1052                         reg = <0x48000000 0x400>;
1053                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
1054                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1055                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
1056                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
1057                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
1058                                      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
1059                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
1060                                      <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1061                         clocks = <&rcc DMA1>;
1062                         resets = <&rcc DMA1_R>;
1063                         #dma-cells = <4>;
1064                         st,mem2mem;
1065                         dma-requests = <8>;
1066                 };
1067
1068                 dma2: dma-controller@48001000 {
1069                         compatible = "st,stm32-dma";
1070                         reg = <0x48001000 0x400>;
1071                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
1072                                      <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
1073                                      <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
1074                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
1075                                      <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
1076                                      <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
1077                                      <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1078                                      <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1079                         clocks = <&rcc DMA2>;
1080                         resets = <&rcc DMA2_R>;
1081                         #dma-cells = <4>;
1082                         st,mem2mem;
1083                         dma-requests = <8>;
1084                 };
1085
1086                 dmamux1: dma-router@48002000 {
1087                         compatible = "st,stm32h7-dmamux";
1088                         reg = <0x48002000 0x40>;
1089                         #dma-cells = <3>;
1090                         dma-requests = <128>;
1091                         dma-masters = <&dma1 &dma2>;
1092                         dma-channels = <16>;
1093                         clocks = <&rcc DMAMUX>;
1094                         resets = <&rcc DMAMUX_R>;
1095                 };
1096
1097                 adc: adc@48003000 {
1098                         compatible = "st,stm32mp1-adc-core";
1099                         reg = <0x48003000 0x400>;
1100                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
1101                                      <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1102                         clocks = <&rcc ADC12>, <&rcc ADC12_K>;
1103                         clock-names = "bus", "adc";
1104                         interrupt-controller;
1105                         st,syscfg = <&syscfg>;
1106                         #interrupt-cells = <1>;
1107                         #address-cells = <1>;
1108                         #size-cells = <0>;
1109                         status = "disabled";
1110
1111                         adc1: adc@0 {
1112                                 compatible = "st,stm32mp1-adc";
1113                                 #io-channel-cells = <1>;
1114                                 reg = <0x0>;
1115                                 interrupt-parent = <&adc>;
1116                                 interrupts = <0>;
1117                                 dmas = <&dmamux1 9 0x400 0x01>;
1118                                 dma-names = "rx";
1119                                 status = "disabled";
1120                         };
1121
1122                         adc2: adc@100 {
1123                                 compatible = "st,stm32mp1-adc";
1124                                 #io-channel-cells = <1>;
1125                                 reg = <0x100>;
1126                                 interrupt-parent = <&adc>;
1127                                 interrupts = <1>;
1128                                 dmas = <&dmamux1 10 0x400 0x01>;
1129                                 dma-names = "rx";
1130                                 status = "disabled";
1131                         };
1132                 };
1133
1134                 sdmmc3: mmc@48004000 {
1135                         compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
1136                         arm,primecell-periphid = <0x00253180>;
1137                         reg = <0x48004000 0x400>;
1138                         interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
1139                         clocks = <&rcc SDMMC3_K>;
1140                         clock-names = "apb_pclk";
1141                         resets = <&rcc SDMMC3_R>;
1142                         cap-sd-highspeed;
1143                         cap-mmc-highspeed;
1144                         max-frequency = <120000000>;
1145                         status = "disabled";
1146                 };
1147
1148                 usbotg_hs: usb-otg@49000000 {
1149                         compatible = "st,stm32mp15-hsotg", "snps,dwc2";
1150                         reg = <0x49000000 0x10000>;
1151                         clocks = <&rcc USBO_K>, <&usbphyc>;
1152                         clock-names = "otg", "utmi";
1153                         resets = <&rcc USBO_R>;
1154                         reset-names = "dwc2";
1155                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1156                         g-rx-fifo-size = <512>;
1157                         g-np-tx-fifo-size = <32>;
1158                         g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
1159                         dr_mode = "otg";
1160                         otg-rev = <0x200>;
1161                         usb33d-supply = <&usb33>;
1162                         status = "disabled";
1163                 };
1164
1165                 hwspinlock: hwspinlock@4c000000 {
1166                         compatible = "st,stm32-hwspinlock";
1167                         #hwlock-cells = <1>;
1168                         reg = <0x4c000000 0x400>;
1169                         clocks = <&rcc HSEM>;
1170                         clock-names = "hwspinlock";
1171                 };
1172
1173                 ipcc: mailbox@4c001000 {
1174                         compatible = "st,stm32mp1-ipcc";
1175                         #mbox-cells = <1>;
1176                         reg = <0x4c001000 0x400>;
1177                         st,proc-id = <0>;
1178                         interrupts-extended =
1179                                 <&exti 61 1>,
1180                                 <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1181                         interrupt-names = "rx", "tx";
1182                         clocks = <&rcc IPCC>;
1183                         wakeup-source;
1184                         status = "disabled";
1185                 };
1186
1187                 dcmi: dcmi@4c006000 {
1188                         compatible = "st,stm32-dcmi";
1189                         reg = <0x4c006000 0x400>;
1190                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1191                         resets = <&rcc CAMITF_R>;
1192                         clocks = <&rcc DCMI>;
1193                         clock-names = "mclk";
1194                         dmas = <&dmamux1 75 0x400 0x01>;
1195                         dma-names = "tx";
1196                         status = "disabled";
1197                 };
1198
1199                 rcc: rcc@50000000 {
1200                         compatible = "st,stm32mp1-rcc", "syscon";
1201                         reg = <0x50000000 0x1000>;
1202                         #clock-cells = <1>;
1203                         #reset-cells = <1>;
1204
1205                         clock-names = "hse", "hsi", "csi", "lse", "lsi";
1206                         clocks = <&clk_hse>, <&clk_hsi>, <&clk_csi>,
1207                                  <&clk_lse>, <&clk_lsi>;
1208                 };
1209
1210                 pwr_regulators: pwr@50001000 {
1211                         compatible = "st,stm32mp1,pwr-reg";
1212                         reg = <0x50001000 0x10>;
1213
1214                         reg11: reg11 {
1215                                 regulator-name = "reg11";
1216                                 regulator-min-microvolt = <1100000>;
1217                                 regulator-max-microvolt = <1100000>;
1218                         };
1219
1220                         reg18: reg18 {
1221                                 regulator-name = "reg18";
1222                                 regulator-min-microvolt = <1800000>;
1223                                 regulator-max-microvolt = <1800000>;
1224                         };
1225
1226                         usb33: usb33 {
1227                                 regulator-name = "usb33";
1228                                 regulator-min-microvolt = <3300000>;
1229                                 regulator-max-microvolt = <3300000>;
1230                         };
1231                 };
1232
1233                 pwr_mcu: pwr_mcu@50001014 {
1234                         compatible = "st,stm32mp151-pwr-mcu", "syscon";
1235                         reg = <0x50001014 0x4>;
1236                 };
1237
1238                 exti: interrupt-controller@5000d000 {
1239                         compatible = "st,stm32mp1-exti", "syscon";
1240                         interrupt-controller;
1241                         #interrupt-cells = <2>;
1242                         reg = <0x5000d000 0x400>;
1243                 };
1244
1245                 syscfg: syscon@50020000 {
1246                         compatible = "st,stm32mp157-syscfg", "syscon";
1247                         reg = <0x50020000 0x400>;
1248                         clocks = <&rcc SYSCFG>;
1249                 };
1250
1251                 lptimer2: timer@50021000 {
1252                         #address-cells = <1>;
1253                         #size-cells = <0>;
1254                         compatible = "st,stm32-lptimer";
1255                         reg = <0x50021000 0x400>;
1256                         interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>;
1257                         clocks = <&rcc LPTIM2_K>;
1258                         clock-names = "mux";
1259                         wakeup-source;
1260                         status = "disabled";
1261
1262                         pwm {
1263                                 compatible = "st,stm32-pwm-lp";
1264                                 #pwm-cells = <3>;
1265                                 status = "disabled";
1266                         };
1267
1268                         trigger@1 {
1269                                 compatible = "st,stm32-lptimer-trigger";
1270                                 reg = <1>;
1271                                 status = "disabled";
1272                         };
1273
1274                         counter {
1275                                 compatible = "st,stm32-lptimer-counter";
1276                                 status = "disabled";
1277                         };
1278                 };
1279
1280                 lptimer3: timer@50022000 {
1281                         #address-cells = <1>;
1282                         #size-cells = <0>;
1283                         compatible = "st,stm32-lptimer";
1284                         reg = <0x50022000 0x400>;
1285                         interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>;
1286                         clocks = <&rcc LPTIM3_K>;
1287                         clock-names = "mux";
1288                         wakeup-source;
1289                         status = "disabled";
1290
1291                         pwm {
1292                                 compatible = "st,stm32-pwm-lp";
1293                                 #pwm-cells = <3>;
1294                                 status = "disabled";
1295                         };
1296
1297                         trigger@2 {
1298                                 compatible = "st,stm32-lptimer-trigger";
1299                                 reg = <2>;
1300                                 status = "disabled";
1301                         };
1302                 };
1303
1304                 lptimer4: timer@50023000 {
1305                         compatible = "st,stm32-lptimer";
1306                         reg = <0x50023000 0x400>;
1307                         interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>;
1308                         clocks = <&rcc LPTIM4_K>;
1309                         clock-names = "mux";
1310                         wakeup-source;
1311                         status = "disabled";
1312
1313                         pwm {
1314                                 compatible = "st,stm32-pwm-lp";
1315                                 #pwm-cells = <3>;
1316                                 status = "disabled";
1317                         };
1318                 };
1319
1320                 lptimer5: timer@50024000 {
1321                         compatible = "st,stm32-lptimer";
1322                         reg = <0x50024000 0x400>;
1323                         interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>;
1324                         clocks = <&rcc LPTIM5_K>;
1325                         clock-names = "mux";
1326                         wakeup-source;
1327                         status = "disabled";
1328
1329                         pwm {
1330                                 compatible = "st,stm32-pwm-lp";
1331                                 #pwm-cells = <3>;
1332                                 status = "disabled";
1333                         };
1334                 };
1335
1336                 vrefbuf: vrefbuf@50025000 {
1337                         compatible = "st,stm32-vrefbuf";
1338                         reg = <0x50025000 0x8>;
1339                         regulator-min-microvolt = <1500000>;
1340                         regulator-max-microvolt = <2500000>;
1341                         clocks = <&rcc VREF>;
1342                         status = "disabled";
1343                 };
1344
1345                 sai4: sai@50027000 {
1346                         compatible = "st,stm32h7-sai";
1347                         #address-cells = <1>;
1348                         #size-cells = <1>;
1349                         ranges = <0 0x50027000 0x400>;
1350                         reg = <0x50027000 0x4>, <0x500273f0 0x10>;
1351                         interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
1352                         resets = <&rcc SAI4_R>;
1353                         status = "disabled";
1354
1355                         sai4a: audio-controller@50027004 {
1356                                 #sound-dai-cells = <0>;
1357                                 compatible = "st,stm32-sai-sub-a";
1358                                 reg = <0x04 0x20>;
1359                                 clocks = <&rcc SAI4_K>;
1360                                 clock-names = "sai_ck";
1361                                 dmas = <&dmamux1 99 0x400 0x01>;
1362                                 status = "disabled";
1363                         };
1364
1365                         sai4b: audio-controller@50027024 {
1366                                 #sound-dai-cells = <0>;
1367                                 compatible = "st,stm32-sai-sub-b";
1368                                 reg = <0x24 0x20>;
1369                                 clocks = <&rcc SAI4_K>;
1370                                 clock-names = "sai_ck";
1371                                 dmas = <&dmamux1 100 0x400 0x01>;
1372                                 status = "disabled";
1373                         };
1374                 };
1375
1376                 dts: thermal@50028000 {
1377                         compatible = "st,stm32-thermal";
1378                         reg = <0x50028000 0x100>;
1379                         interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1380                         clocks = <&rcc TMPSENS>;
1381                         clock-names = "pclk";
1382                         #thermal-sensor-cells = <0>;
1383                         status = "disabled";
1384                 };
1385
1386                 hash1: hash@54002000 {
1387                         compatible = "st,stm32f756-hash";
1388                         reg = <0x54002000 0x400>;
1389                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1390                         clocks = <&rcc HASH1>;
1391                         resets = <&rcc HASH1_R>;
1392                         dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>;
1393                         dma-names = "in";
1394                         dma-maxburst = <2>;
1395                         status = "disabled";
1396                 };
1397
1398                 rng1: rng@54003000 {
1399                         compatible = "st,stm32-rng";
1400                         reg = <0x54003000 0x400>;
1401                         clocks = <&rcc RNG1_K>;
1402                         resets = <&rcc RNG1_R>;
1403                         status = "disabled";
1404                 };
1405
1406                 mdma1: dma-controller@58000000 {
1407                         compatible = "st,stm32h7-mdma";
1408                         reg = <0x58000000 0x1000>;
1409                         interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1410                         clocks = <&rcc MDMA>;
1411                         resets = <&rcc MDMA_R>;
1412                         #dma-cells = <5>;
1413                         dma-channels = <32>;
1414                         dma-requests = <48>;
1415                 };
1416
1417                 fmc: memory-controller@58002000 {
1418                         #address-cells = <2>;
1419                         #size-cells = <1>;
1420                         compatible = "st,stm32mp1-fmc2-ebi";
1421                         reg = <0x58002000 0x1000>;
1422                         clocks = <&rcc FMC_K>;
1423                         resets = <&rcc FMC_R>;
1424                         status = "disabled";
1425
1426                         ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
1427                                  <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
1428                                  <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
1429                                  <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
1430                                  <4 0 0x80000000 0x10000000>; /* NAND */
1431
1432                         nand-controller@4,0 {
1433                                 #address-cells = <1>;
1434                                 #size-cells = <0>;
1435                                 compatible = "st,stm32mp1-fmc2-nfc";
1436                                 reg = <4 0x00000000 0x1000>,
1437                                       <4 0x08010000 0x1000>,
1438                                       <4 0x08020000 0x1000>,
1439                                       <4 0x01000000 0x1000>,
1440                                       <4 0x09010000 0x1000>,
1441                                       <4 0x09020000 0x1000>;
1442                                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1443                                 dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
1444                                        <&mdma1 20 0x2 0x12000a08 0x0 0x0>,
1445                                        <&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
1446                                 dma-names = "tx", "rx", "ecc";
1447                                 status = "disabled";
1448                         };
1449                 };
1450
1451                 qspi: spi@58003000 {
1452                         compatible = "st,stm32f469-qspi";
1453                         reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
1454                         reg-names = "qspi", "qspi_mm";
1455                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
1456                         dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>,
1457                                <&mdma1 22 0x2 0x10100008 0x0 0x0>;
1458                         dma-names = "tx", "rx";
1459                         clocks = <&rcc QSPI_K>;
1460                         resets = <&rcc QSPI_R>;
1461                         #address-cells = <1>;
1462                         #size-cells = <0>;
1463                         status = "disabled";
1464                 };
1465
1466                 sdmmc1: mmc@58005000 {
1467                         compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
1468                         arm,primecell-periphid = <0x00253180>;
1469                         reg = <0x58005000 0x1000>;
1470                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1471                         clocks = <&rcc SDMMC1_K>;
1472                         clock-names = "apb_pclk";
1473                         resets = <&rcc SDMMC1_R>;
1474                         cap-sd-highspeed;
1475                         cap-mmc-highspeed;
1476                         max-frequency = <120000000>;
1477                         status = "disabled";
1478                 };
1479
1480                 sdmmc2: mmc@58007000 {
1481                         compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
1482                         arm,primecell-periphid = <0x00253180>;
1483                         reg = <0x58007000 0x1000>;
1484                         interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
1485                         clocks = <&rcc SDMMC2_K>;
1486                         clock-names = "apb_pclk";
1487                         resets = <&rcc SDMMC2_R>;
1488                         cap-sd-highspeed;
1489                         cap-mmc-highspeed;
1490                         max-frequency = <120000000>;
1491                         status = "disabled";
1492                 };
1493
1494                 crc1: crc@58009000 {
1495                         compatible = "st,stm32f7-crc";
1496                         reg = <0x58009000 0x400>;
1497                         clocks = <&rcc CRC1>;
1498                         status = "disabled";
1499                 };
1500
1501                 ethernet0: ethernet@5800a000 {
1502                         compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
1503                         reg = <0x5800a000 0x2000>;
1504                         reg-names = "stmmaceth";
1505                         interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1506                         interrupt-names = "macirq";
1507                         clock-names = "stmmaceth",
1508                                       "mac-clk-tx",
1509                                       "mac-clk-rx",
1510                                       "eth-ck",
1511                                       "ptp_ref",
1512                                       "ethstp";
1513                         clocks = <&rcc ETHMAC>,
1514                                  <&rcc ETHTX>,
1515                                  <&rcc ETHRX>,
1516                                  <&rcc ETHCK_K>,
1517                                  <&rcc ETHPTP_K>,
1518                                  <&rcc ETHSTP>;
1519                         st,syscon = <&syscfg 0x4>;
1520                         snps,mixed-burst;
1521                         snps,pbl = <2>;
1522                         snps,en-tx-lpi-clockgating;
1523                         snps,axi-config = <&stmmac_axi_config_0>;
1524                         snps,tso;
1525                         status = "disabled";
1526
1527                         stmmac_axi_config_0: stmmac-axi-config {
1528                                 snps,wr_osr_lmt = <0x7>;
1529                                 snps,rd_osr_lmt = <0x7>;
1530                                 snps,blen = <0 0 0 0 16 8 4>;
1531                         };
1532                 };
1533
1534                 usbh_ohci: usb@5800c000 {
1535                         compatible = "generic-ohci";
1536                         reg = <0x5800c000 0x1000>;
1537                         clocks = <&usbphyc>, <&rcc USBH>;
1538                         resets = <&rcc USBH_R>;
1539                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1540                         status = "disabled";
1541                 };
1542
1543                 usbh_ehci: usb@5800d000 {
1544                         compatible = "generic-ehci";
1545                         reg = <0x5800d000 0x1000>;
1546                         clocks = <&usbphyc>, <&rcc USBH>;
1547                         resets = <&rcc USBH_R>;
1548                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1549                         companion = <&usbh_ohci>;
1550                         status = "disabled";
1551                 };
1552
1553                 ltdc: display-controller@5a001000 {
1554                         compatible = "st,stm32-ltdc";
1555                         reg = <0x5a001000 0x400>;
1556                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1557                                      <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1558                         clocks = <&rcc LTDC_PX>;
1559                         clock-names = "lcd";
1560                         resets = <&rcc LTDC_R>;
1561                         status = "disabled";
1562
1563                         port {
1564                                 #address-cells = <1>;
1565                                 #size-cells = <0>;
1566                         };
1567                 };
1568
1569                 iwdg2: watchdog@5a002000 {
1570                         compatible = "st,stm32mp1-iwdg";
1571                         reg = <0x5a002000 0x400>;
1572                         clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
1573                         clock-names = "pclk", "lsi";
1574                         status = "disabled";
1575                 };
1576
1577                 usbphyc: usbphyc@5a006000 {
1578                         #address-cells = <1>;
1579                         #size-cells = <0>;
1580                         #clock-cells = <0>;
1581                         compatible = "st,stm32mp1-usbphyc";
1582                         reg = <0x5a006000 0x1000>;
1583                         clocks = <&rcc USBPHY_K>;
1584                         resets = <&rcc USBPHY_R>;
1585                         vdda1v1-supply = <&reg11>;
1586                         vdda1v8-supply = <&reg18>;
1587                         status = "disabled";
1588
1589                         usbphyc_port0: usb-phy@0 {
1590                                 #phy-cells = <0>;
1591                                 reg = <0>;
1592                         };
1593
1594                         usbphyc_port1: usb-phy@1 {
1595                                 #phy-cells = <1>;
1596                                 reg = <1>;
1597                         };
1598                 };
1599
1600                 usart1: serial@5c000000 {
1601                         compatible = "st,stm32h7-uart";
1602                         reg = <0x5c000000 0x400>;
1603                         interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
1604                         clocks = <&rcc USART1_K>;
1605                         wakeup-source;
1606                         status = "disabled";
1607                 };
1608
1609                 spi6: spi@5c001000 {
1610                         #address-cells = <1>;
1611                         #size-cells = <0>;
1612                         compatible = "st,stm32h7-spi";
1613                         reg = <0x5c001000 0x400>;
1614                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1615                         clocks = <&rcc SPI6_K>;
1616                         resets = <&rcc SPI6_R>;
1617                         dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
1618                                <&mdma1 35 0x0 0x40002 0x0 0x0>;
1619                         dma-names = "rx", "tx";
1620                         status = "disabled";
1621                 };
1622
1623                 i2c4: i2c@5c002000 {
1624                         compatible = "st,stm32mp15-i2c";
1625                         reg = <0x5c002000 0x400>;
1626                         interrupt-names = "event", "error";
1627                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1628                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1629                         clocks = <&rcc I2C4_K>;
1630                         resets = <&rcc I2C4_R>;
1631                         #address-cells = <1>;
1632                         #size-cells = <0>;
1633                         st,syscfg-fmp = <&syscfg 0x4 0x8>;
1634                         wakeup-source;
1635                         i2c-analog-filter;
1636                         status = "disabled";
1637                 };
1638
1639                 rtc: rtc@5c004000 {
1640                         compatible = "st,stm32mp1-rtc";
1641                         reg = <0x5c004000 0x400>;
1642                         clocks = <&rcc RTCAPB>, <&rcc RTC>;
1643                         clock-names = "pclk", "rtc_ck";
1644                         interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
1645                         status = "disabled";
1646                 };
1647
1648                 bsec: efuse@5c005000 {
1649                         compatible = "st,stm32mp15-bsec";
1650                         reg = <0x5c005000 0x400>;
1651                         #address-cells = <1>;
1652                         #size-cells = <1>;
1653                         part_number_otp: part_number_otp@4 {
1654                                 reg = <0x4 0x1>;
1655                         };
1656                         ts_cal1: calib@5c {
1657                                 reg = <0x5c 0x2>;
1658                         };
1659                         ts_cal2: calib@5e {
1660                                 reg = <0x5e 0x2>;
1661                         };
1662                 };
1663
1664                 i2c6: i2c@5c009000 {
1665                         compatible = "st,stm32mp15-i2c";
1666                         reg = <0x5c009000 0x400>;
1667                         interrupt-names = "event", "error";
1668                         interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1669                                      <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1670                         clocks = <&rcc I2C6_K>;
1671                         resets = <&rcc I2C6_R>;
1672                         #address-cells = <1>;
1673                         #size-cells = <0>;
1674                         st,syscfg-fmp = <&syscfg 0x4 0x20>;
1675                         wakeup-source;
1676                         i2c-analog-filter;
1677                         status = "disabled";
1678                 };
1679
1680                 tamp: tamp@5c00a000 {
1681                         compatible = "st,stm32-tamp", "syscon", "simple-mfd";
1682                         reg = <0x5c00a000 0x400>;
1683                 };
1684
1685                 /*
1686                  * Break node order to solve dependency probe issue between
1687                  * pinctrl and exti.
1688                  */
1689                 pinctrl: pinctrl@50002000 {
1690                         #address-cells = <1>;
1691                         #size-cells = <1>;
1692                         compatible = "st,stm32mp157-pinctrl";
1693                         ranges = <0 0x50002000 0xa400>;
1694                         interrupt-parent = <&exti>;
1695                         st,syscfg = <&exti 0x60 0xff>;
1696
1697                         gpioa: gpio@50002000 {
1698                                 gpio-controller;
1699                                 #gpio-cells = <2>;
1700                                 interrupt-controller;
1701                                 #interrupt-cells = <2>;
1702                                 reg = <0x0 0x400>;
1703                                 clocks = <&rcc GPIOA>;
1704                                 st,bank-name = "GPIOA";
1705                                 status = "disabled";
1706                         };
1707
1708                         gpiob: gpio@50003000 {
1709                                 gpio-controller;
1710                                 #gpio-cells = <2>;
1711                                 interrupt-controller;
1712                                 #interrupt-cells = <2>;
1713                                 reg = <0x1000 0x400>;
1714                                 clocks = <&rcc GPIOB>;
1715                                 st,bank-name = "GPIOB";
1716                                 status = "disabled";
1717                         };
1718
1719                         gpioc: gpio@50004000 {
1720                                 gpio-controller;
1721                                 #gpio-cells = <2>;
1722                                 interrupt-controller;
1723                                 #interrupt-cells = <2>;
1724                                 reg = <0x2000 0x400>;
1725                                 clocks = <&rcc GPIOC>;
1726                                 st,bank-name = "GPIOC";
1727                                 status = "disabled";
1728                         };
1729
1730                         gpiod: gpio@50005000 {
1731                                 gpio-controller;
1732                                 #gpio-cells = <2>;
1733                                 interrupt-controller;
1734                                 #interrupt-cells = <2>;
1735                                 reg = <0x3000 0x400>;
1736                                 clocks = <&rcc GPIOD>;
1737                                 st,bank-name = "GPIOD";
1738                                 status = "disabled";
1739                         };
1740
1741                         gpioe: gpio@50006000 {
1742                                 gpio-controller;
1743                                 #gpio-cells = <2>;
1744                                 interrupt-controller;
1745                                 #interrupt-cells = <2>;
1746                                 reg = <0x4000 0x400>;
1747                                 clocks = <&rcc GPIOE>;
1748                                 st,bank-name = "GPIOE";
1749                                 status = "disabled";
1750                         };
1751
1752                         gpiof: gpio@50007000 {
1753                                 gpio-controller;
1754                                 #gpio-cells = <2>;
1755                                 interrupt-controller;
1756                                 #interrupt-cells = <2>;
1757                                 reg = <0x5000 0x400>;
1758                                 clocks = <&rcc GPIOF>;
1759                                 st,bank-name = "GPIOF";
1760                                 status = "disabled";
1761                         };
1762
1763                         gpiog: gpio@50008000 {
1764                                 gpio-controller;
1765                                 #gpio-cells = <2>;
1766                                 interrupt-controller;
1767                                 #interrupt-cells = <2>;
1768                                 reg = <0x6000 0x400>;
1769                                 clocks = <&rcc GPIOG>;
1770                                 st,bank-name = "GPIOG";
1771                                 status = "disabled";
1772                         };
1773
1774                         gpioh: gpio@50009000 {
1775                                 gpio-controller;
1776                                 #gpio-cells = <2>;
1777                                 interrupt-controller;
1778                                 #interrupt-cells = <2>;
1779                                 reg = <0x7000 0x400>;
1780                                 clocks = <&rcc GPIOH>;
1781                                 st,bank-name = "GPIOH";
1782                                 status = "disabled";
1783                         };
1784
1785                         gpioi: gpio@5000a000 {
1786                                 gpio-controller;
1787                                 #gpio-cells = <2>;
1788                                 interrupt-controller;
1789                                 #interrupt-cells = <2>;
1790                                 reg = <0x8000 0x400>;
1791                                 clocks = <&rcc GPIOI>;
1792                                 st,bank-name = "GPIOI";
1793                                 status = "disabled";
1794                         };
1795
1796                         gpioj: gpio@5000b000 {
1797                                 gpio-controller;
1798                                 #gpio-cells = <2>;
1799                                 interrupt-controller;
1800                                 #interrupt-cells = <2>;
1801                                 reg = <0x9000 0x400>;
1802                                 clocks = <&rcc GPIOJ>;
1803                                 st,bank-name = "GPIOJ";
1804                                 status = "disabled";
1805                         };
1806
1807                         gpiok: gpio@5000c000 {
1808                                 gpio-controller;
1809                                 #gpio-cells = <2>;
1810                                 interrupt-controller;
1811                                 #interrupt-cells = <2>;
1812                                 reg = <0xa000 0x400>;
1813                                 clocks = <&rcc GPIOK>;
1814                                 st,bank-name = "GPIOK";
1815                                 status = "disabled";
1816                         };
1817                 };
1818
1819                 pinctrl_z: pinctrl@54004000 {
1820                         #address-cells = <1>;
1821                         #size-cells = <1>;
1822                         compatible = "st,stm32mp157-z-pinctrl";
1823                         ranges = <0 0x54004000 0x400>;
1824                         interrupt-parent = <&exti>;
1825                         st,syscfg = <&exti 0x60 0xff>;
1826
1827                         gpioz: gpio@54004000 {
1828                                 gpio-controller;
1829                                 #gpio-cells = <2>;
1830                                 interrupt-controller;
1831                                 #interrupt-cells = <2>;
1832                                 reg = <0 0x400>;
1833                                 clocks = <&rcc GPIOZ>;
1834                                 st,bank-name = "GPIOZ";
1835                                 st,bank-ioport = <11>;
1836                                 status = "disabled";
1837                         };
1838                 };
1839         };
1840
1841         mlahb: ahb {
1842                 compatible = "st,mlahb", "simple-bus";
1843                 #address-cells = <1>;
1844                 #size-cells = <1>;
1845                 ranges;
1846                 dma-ranges = <0x00000000 0x38000000 0x10000>,
1847                              <0x10000000 0x10000000 0x60000>,
1848                              <0x30000000 0x30000000 0x60000>;
1849
1850                 m4_rproc: m4@10000000 {
1851                         compatible = "st,stm32mp1-m4";
1852                         reg = <0x10000000 0x40000>,
1853                               <0x30000000 0x40000>,
1854                               <0x38000000 0x10000>;
1855                         resets = <&rcc MCU_R>;
1856                         st,syscfg-holdboot = <&rcc 0x10C 0x1>;
1857                         st,syscfg-tz = <&rcc 0x000 0x1>;
1858                         st,syscfg-pdds = <&pwr_mcu 0x0 0x1>;
1859                         st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>;
1860                         st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>;
1861                         status = "disabled";
1862                 };
1863         };
1864 };