arch/arm/dts/stm32mp151.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /*
   3  * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
   4  * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
   5  */
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/stm32mp1-clks.h>
   8 #include <dt-bindings/reset/stm32mp1-resets.h>
   9
  10 / {
  11         #address-cells = <1>;
  12         #size-cells = <1>;
  13
  14         cpus {
  15                 #address-cells = <1>;
  16                 #size-cells = <0>;
  17
  18                 cpu0: cpu@0 {
  19                         compatible = "arm,cortex-a7";
  20                         clock-frequency = <650000000>;
  21                         device_type = "cpu";
  22                         reg = <0>;
  23                         operating-points-v2 = <&cpu0_opp_table>;
  24                         nvmem-cells = <&part_number_otp>;
  25                         nvmem-cell-names = "part_number";
  26                 };
  27         };
  28
  29         cpu0_opp_table: cpu0-opp-table {
  30                 compatible = "operating-points-v2";
  31                 opp-shared;
  32                 opp-650000000 {
  33                         opp-hz = /bits/ 64 <650000000>;
  34                         opp-microvolt = <1200000>;
  35                         opp-supported-hw = <0x1>;
  36                 };
  37                 opp-800000000 {
  38                         opp-hz = /bits/ 64 <800000000>;
  39                         opp-microvolt = <1350000>;
  40                         opp-supported-hw = <0x2>;
  41                 };
  42         };
  43
  44         psci {
  45                 compatible = "arm,psci-1.0";
  46                 method = "smc";
  47                 cpu_off = <0x84000002>;
  48                 cpu_on = <0x84000003>;
  49         };
  50
  51         intc: interrupt-controller@a0021000 {
  52                 compatible = "arm,cortex-a7-gic";
  53                 #interrupt-cells = <3>;
  54                 interrupt-controller;
  55                 reg = <0xa0021000 0x1000>,
  56                       <0xa0022000 0x2000>;
  57         };
  58
  59         timer {
  60                 compatible = "arm,armv7-timer";
  61                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  62                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  63                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  64                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  65                 interrupt-parent = <&intc>;
  66         };
  67
  68         clocks {
  69                 clk_hse: clk-hse {
  70                         #clock-cells = <0>;
  71                         compatible = "fixed-clock";
  72                         clock-frequency = <24000000>;
  73                 };
  74
  75                 clk_hsi: clk-hsi {
  76                         #clock-cells = <0>;
  77                         compatible = "fixed-clock";
  78                         clock-frequency = <64000000>;
  79                 };
  80
  81                 clk_lse: clk-lse {
  82                         #clock-cells = <0>;
  83                         compatible = "fixed-clock";
  84                         clock-frequency = <32768>;
  85                 };
  86
  87                 clk_lsi: clk-lsi {
  88                         #clock-cells = <0>;
  89                         compatible = "fixed-clock";
  90                         clock-frequency = <32000>;
  91                 };
  92
  93                 clk_csi: clk-csi {
  94                         #clock-cells = <0>;
  95                         compatible = "fixed-clock";
  96                         clock-frequency = <4000000>;
  97                 };
  98         };
  99
 100         thermal-zones {
 101                 cpu_thermal: cpu-thermal {
 102                         polling-delay-passive = <0>;
 103                         polling-delay = <0>;
 104                         thermal-sensors = <&dts>;
 105
 106                         trips {
 107                                 cpu_alert1: cpu-alert1 {
 108                                         temperature = <85000>;
 109                                         hysteresis = <0>;
 110                                         type = "passive";
 111                                 };
 112
 113                                 cpu-crit {
 114                                         temperature = <120000>;
 115                                         hysteresis = <0>;
 116                                         type = "critical";
 117                                 };
 118                         };
 119
 120                         cooling-maps {
 121                         };
 122                 };
 123         };
 124
 125         booster: regulator-booster {
 126                 compatible = "st,stm32mp1-booster";
 127                 st,syscfg = <&syscfg>;
 128                 status = "disabled";
 129         };
 130
 131         reboot {
 132                 compatible = "syscon-reboot";
 133                 regmap = <&rcc>;
 134                 offset = <0x404>;
 135                 mask = <0x1>;
 136         };
 137
 138         soc {
 139                 compatible = "simple-bus";
 140                 #address-cells = <1>;
 141                 #size-cells = <1>;
 142                 interrupt-parent = <&intc>;
 143                 ranges;
 144
 145                 timers2: timer@40000000 {
 146                         #address-cells = <1>;
 147                         #size-cells = <0>;
 148                         compatible = "st,stm32-timers";
 149                         reg = <0x40000000 0x400>;
 150                         clocks = <&rcc TIM2_K>;
 151                         clock-names = "int";
 152                         dmas = <&dmamux1 18 0x400 0x1>,
 153                                <&dmamux1 19 0x400 0x1>,
 154                                <&dmamux1 20 0x400 0x1>,
 155                                <&dmamux1 21 0x400 0x1>,
 156                                <&dmamux1 22 0x400 0x1>;
 157                         dma-names = "ch1", "ch2", "ch3", "ch4", "up";
 158                         status = "disabled";
 159
 160                         pwm {
 161                                 compatible = "st,stm32-pwm";
 162                                 #pwm-cells = <3>;
 163                                 status = "disabled";
 164                         };
 165
 166                         timer@1 {
 167                                 compatible = "st,stm32h7-timer-trigger";
 168                                 reg = <1>;
 169                                 status = "disabled";
 170                         };
 171
 172                         counter {
 173                                 compatible = "st,stm32-timer-counter";
 174                                 status = "disabled";
 175                         };
 176                 };
 177
 178                 timers3: timer@40001000 {
 179                         #address-cells = <1>;
 180                         #size-cells = <0>;
 181                         compatible = "st,stm32-timers";
 182                         reg = <0x40001000 0x400>;
 183                         clocks = <&rcc TIM3_K>;
 184                         clock-names = "int";
 185                         dmas = <&dmamux1 23 0x400 0x1>,
 186                                <&dmamux1 24 0x400 0x1>,
 187                                <&dmamux1 25 0x400 0x1>,
 188                                <&dmamux1 26 0x400 0x1>,
 189                                <&dmamux1 27 0x400 0x1>,
 190                                <&dmamux1 28 0x400 0x1>;
 191                         dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
 192                         status = "disabled";
 193
 194                         pwm {
 195                                 compatible = "st,stm32-pwm";
 196                                 #pwm-cells = <3>;
 197                                 status = "disabled";
 198                         };
 199
 200                         timer@2 {
 201                                 compatible = "st,stm32h7-timer-trigger";
 202                                 reg = <2>;
 203                                 status = "disabled";
 204                         };
 205
 206                         counter {
 207                                 compatible = "st,stm32-timer-counter";
 208                                 status = "disabled";
 209                         };
 210                 };
 211
 212                 timers4: timer@40002000 {
 213                         #address-cells = <1>;
 214                         #size-cells = <0>;
 215                         compatible = "st,stm32-timers";
 216                         reg = <0x40002000 0x400>;
 217                         clocks = <&rcc TIM4_K>;
 218                         clock-names = "int";
 219                         dmas = <&dmamux1 29 0x400 0x1>,
 220                                <&dmamux1 30 0x400 0x1>,
 221                                <&dmamux1 31 0x400 0x1>,
 222                                <&dmamux1 32 0x400 0x1>;
 223                         dma-names = "ch1", "ch2", "ch3", "ch4";
 224                         status = "disabled";
 225
 226                         pwm {
 227                                 compatible = "st,stm32-pwm";
 228                                 #pwm-cells = <3>;
 229                                 status = "disabled";
 230                         };
 231
 232                         timer@3 {
 233                                 compatible = "st,stm32h7-timer-trigger";
 234                                 reg = <3>;
 235                                 status = "disabled";
 236                         };
 237
 238                         counter {
 239                                 compatible = "st,stm32-timer-counter";
 240                                 status = "disabled";
 241                         };
 242                 };
 243
 244                 timers5: timer@40003000 {
 245                         #address-cells = <1>;
 246                         #size-cells = <0>;
 247                         compatible = "st,stm32-timers";
 248                         reg = <0x40003000 0x400>;
 249                         clocks = <&rcc TIM5_K>;
 250                         clock-names = "int";
 251                         dmas = <&dmamux1 55 0x400 0x1>,
 252                                <&dmamux1 56 0x400 0x1>,
 253                                <&dmamux1 57 0x400 0x1>,
 254                                <&dmamux1 58 0x400 0x1>,
 255                                <&dmamux1 59 0x400 0x1>,
 256                                <&dmamux1 60 0x400 0x1>;
 257                         dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
 258                         status = "disabled";
 259
 260                         pwm {
 261                                 compatible = "st,stm32-pwm";
 262                                 #pwm-cells = <3>;
 263                                 status = "disabled";
 264                         };
 265
 266                         timer@4 {
 267                                 compatible = "st,stm32h7-timer-trigger";
 268                                 reg = <4>;
 269                                 status = "disabled";
 270                         };
 271
 272                         counter {
 273                                 compatible = "st,stm32-timer-counter";
 274                                 status = "disabled";
 275                         };
 276                 };
 277
 278                 timers6: timer@40004000 {
 279                         #address-cells = <1>;
 280                         #size-cells = <0>;
 281                         compatible = "st,stm32-timers";
 282                         reg = <0x40004000 0x400>;
 283                         clocks = <&rcc TIM6_K>;
 284                         clock-names = "int";
 285                         dmas = <&dmamux1 69 0x400 0x1>;
 286                         dma-names = "up";
 287                         status = "disabled";
 288
 289                         timer@5 {
 290                                 compatible = "st,stm32h7-timer-trigger";
 291                                 reg = <5>;
 292                                 status = "disabled";
 293                         };
 294                 };
 295
 296                 timers7: timer@40005000 {
 297                         #address-cells = <1>;
 298                         #size-cells = <0>;
 299                         compatible = "st,stm32-timers";
 300                         reg = <0x40005000 0x400>;
 301                         clocks = <&rcc TIM7_K>;
 302                         clock-names = "int";
 303                         dmas = <&dmamux1 70 0x400 0x1>;
 304                         dma-names = "up";
 305                         status = "disabled";
 306
 307                         timer@6 {
 308                                 compatible = "st,stm32h7-timer-trigger";
 309                                 reg = <6>;
 310                                 status = "disabled";
 311                         };
 312                 };
 313
 314                 timers12: timer@40006000 {
 315                         #address-cells = <1>;
 316                         #size-cells = <0>;
 317                         compatible = "st,stm32-timers";
 318                         reg = <0x40006000 0x400>;
 319                         clocks = <&rcc TIM12_K>;
 320                         clock-names = "int";
 321                         status = "disabled";
 322
 323                         pwm {
 324                                 compatible = "st,stm32-pwm";
 325                                 #pwm-cells = <3>;
 326                                 status = "disabled";
 327                         };
 328
 329                         timer@11 {
 330                                 compatible = "st,stm32h7-timer-trigger";
 331                                 reg = <11>;
 332                                 status = "disabled";
 333                         };
 334                 };
 335
 336                 timers13: timer@40007000 {
 337                         #address-cells = <1>;
 338                         #size-cells = <0>;
 339                         compatible = "st,stm32-timers";
 340                         reg = <0x40007000 0x400>;
 341                         clocks = <&rcc TIM13_K>;
 342                         clock-names = "int";
 343                         status = "disabled";
 344
 345                         pwm {
 346                                 compatible = "st,stm32-pwm";
 347                                 #pwm-cells = <3>;
 348                                 status = "disabled";
 349                         };
 350
 351                         timer@12 {
 352                                 compatible = "st,stm32h7-timer-trigger";
 353                                 reg = <12>;
 354                                 status = "disabled";
 355                         };
 356                 };
 357
 358                 timers14: timer@40008000 {
 359                         #address-cells = <1>;
 360                         #size-cells = <0>;
 361                         compatible = "st,stm32-timers";
 362                         reg = <0x40008000 0x400>;
 363                         clocks = <&rcc TIM14_K>;
 364                         clock-names = "int";
 365                         status = "disabled";
 366
 367                         pwm {
 368                                 compatible = "st,stm32-pwm";
 369                                 #pwm-cells = <3>;
 370                                 status = "disabled";
 371                         };
 372
 373                         timer@13 {
 374                                 compatible = "st,stm32h7-timer-trigger";
 375                                 reg = <13>;
 376                                 status = "disabled";
 377                         };
 378                 };
 379
 380                 lptimer1: timer@40009000 {
 381                         #address-cells = <1>;
 382                         #size-cells = <0>;
 383                         compatible = "st,stm32-lptimer";
 384                         reg = <0x40009000 0x400>;
 385                         clocks = <&rcc LPTIM1_K>;
 386                         clock-names = "mux";
 387                         status = "disabled";
 388
 389                         pwm {
 390                                 compatible = "st,stm32-pwm-lp";
 391                                 #pwm-cells = <3>;
 392                                 status = "disabled";
 393                         };
 394
 395                         trigger@0 {
 396                                 compatible = "st,stm32-lptimer-trigger";
 397                                 reg = <0>;
 398                                 status = "disabled";
 399                         };
 400
 401                         counter {
 402                                 compatible = "st,stm32-lptimer-counter";
 403                                 status = "disabled";
 404                         };
 405                 };
 406
 407                 spi2: spi@4000b000 {
 408                         #address-cells = <1>;
 409                         #size-cells = <0>;
 410                         compatible = "st,stm32h7-spi";
 411                         reg = <0x4000b000 0x400>;
 412                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 413                         clocks = <&rcc SPI2_K>;
 414                         resets = <&rcc SPI2_R>;
 415                         dmas = <&dmamux1 39 0x400 0x05>,
 416                                <&dmamux1 40 0x400 0x05>;
 417                         dma-names = "rx", "tx";
 418                         status = "disabled";
 419                 };
 420
 421                 i2s2: audio-controller@4000b000 {
 422                         compatible = "st,stm32h7-i2s";
 423                         #sound-dai-cells = <0>;
 424                         reg = <0x4000b000 0x400>;
 425                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 426                         dmas = <&dmamux1 39 0x400 0x01>,
 427                                <&dmamux1 40 0x400 0x01>;
 428                         dma-names = "rx", "tx";
 429                         status = "disabled";
 430                 };
 431
 432                 spi3: spi@4000c000 {
 433                         #address-cells = <1>;
 434                         #size-cells = <0>;
 435                         compatible = "st,stm32h7-spi";
 436                         reg = <0x4000c000 0x400>;
 437                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 438                         clocks = <&rcc SPI3_K>;
 439                         resets = <&rcc SPI3_R>;
 440                         dmas = <&dmamux1 61 0x400 0x05>,
 441                                <&dmamux1 62 0x400 0x05>;
 442                         dma-names = "rx", "tx";
 443                         status = "disabled";
 444                 };
 445
 446                 i2s3: audio-controller@4000c000 {
 447                         compatible = "st,stm32h7-i2s";
 448                         #sound-dai-cells = <0>;
 449                         reg = <0x4000c000 0x400>;
 450                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 451                         dmas = <&dmamux1 61 0x400 0x01>,
 452                                <&dmamux1 62 0x400 0x01>;
 453                         dma-names = "rx", "tx";
 454                         status = "disabled";
 455                 };
 456
 457                 spdifrx: audio-controller@4000d000 {
 458                         compatible = "st,stm32h7-spdifrx";
 459                         #sound-dai-cells = <0>;
 460                         reg = <0x4000d000 0x400>;
 461                         clocks = <&rcc SPDIF_K>;
 462                         clock-names = "kclk";
 463                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 464                         dmas = <&dmamux1 93 0x400 0x01>,
 465                                <&dmamux1 94 0x400 0x01>;
 466                         dma-names = "rx", "rx-ctrl";
 467                         status = "disabled";
 468                 };
 469
 470                 usart2: serial@4000e000 {
 471                         compatible = "st,stm32h7-uart";
 472                         reg = <0x4000e000 0x400>;
 473                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 474                         clocks = <&rcc USART2_K>;
 475                         status = "disabled";
 476                 };
 477
 478                 usart3: serial@4000f000 {
 479                         compatible = "st,stm32h7-uart";
 480                         reg = <0x4000f000 0x400>;
 481                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 482                         clocks = <&rcc USART3_K>;
 483                         status = "disabled";
 484                 };
 485
 486                 uart4: serial@40010000 {
 487                         compatible = "st,stm32h7-uart";
 488                         reg = <0x40010000 0x400>;
 489                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 490                         clocks = <&rcc UART4_K>;
 491                         status = "disabled";
 492                 };
 493
 494                 uart5: serial@40011000 {
 495                         compatible = "st,stm32h7-uart";
 496                         reg = <0x40011000 0x400>;
 497                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 498                         clocks = <&rcc UART5_K>;
 499                         status = "disabled";
 500                 };
 501
 502                 i2c1: i2c@40012000 {
 503                         compatible = "st,stm32f7-i2c";
 504                         reg = <0x40012000 0x400>;
 505                         interrupt-names = "event", "error";
 506                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
 507                                      <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 508                         clocks = <&rcc I2C1_K>;
 509                         resets = <&rcc I2C1_R>;
 510                         #address-cells = <1>;
 511                         #size-cells = <0>;
 512                         wakeup-source;
 513                         status = "disabled";
 514                 };
 515
 516                 i2c2: i2c@40013000 {
 517                         compatible = "st,stm32f7-i2c";
 518                         reg = <0x40013000 0x400>;
 519                         interrupt-names = "event", "error";
 520                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 521                                      <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 522                         clocks = <&rcc I2C2_K>;
 523                         resets = <&rcc I2C2_R>;
 524                         #address-cells = <1>;
 525                         #size-cells = <0>;
 526                         wakeup-source;
 527                         status = "disabled";
 528                 };
 529
 530                 i2c3: i2c@40014000 {
 531                         compatible = "st,stm32f7-i2c";
 532                         reg = <0x40014000 0x400>;
 533                         interrupt-names = "event", "error";
 534                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 535                                      <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 536                         clocks = <&rcc I2C3_K>;
 537                         resets = <&rcc I2C3_R>;
 538                         #address-cells = <1>;
 539                         #size-cells = <0>;
 540                         wakeup-source;
 541                         status = "disabled";
 542                 };
 543
 544                 i2c5: i2c@40015000 {
 545                         compatible = "st,stm32f7-i2c";
 546                         reg = <0x40015000 0x400>;
 547                         interrupt-names = "event", "error";
 548                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 549                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 550                         clocks = <&rcc I2C5_K>;
 551                         resets = <&rcc I2C5_R>;
 552                         #address-cells = <1>;
 553                         #size-cells = <0>;
 554                         wakeup-source;
 555                         status = "disabled";
 556                 };
 557
 558                 cec: cec@40016000 {
 559                         compatible = "st,stm32-cec";
 560                         reg = <0x40016000 0x400>;
 561                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 562                         clocks = <&rcc CEC_K>, <&clk_lse>;
 563                         clock-names = "cec", "hdmi-cec";
 564                         status = "disabled";
 565                 };
 566
 567                 dac: dac@40017000 {
 568                         compatible = "st,stm32h7-dac-core";
 569                         reg = <0x40017000 0x400>;
 570                         clocks = <&rcc DAC12>;
 571                         clock-names = "pclk";
 572                         #address-cells = <1>;
 573                         #size-cells = <0>;
 574                         status = "disabled";
 575
 576                         dac1: dac@1 {
 577                                 compatible = "st,stm32-dac";
 578                                 #io-channels-cells = <1>;
 579                                 reg = <1>;
 580                                 status = "disabled";
 581                         };
 582
 583                         dac2: dac@2 {
 584                                 compatible = "st,stm32-dac";
 585                                 #io-channels-cells = <1>;
 586                                 reg = <2>;
 587                                 status = "disabled";
 588                         };
 589                 };
 590
 591                 uart7: serial@40018000 {
 592                         compatible = "st,stm32h7-uart";
 593                         reg = <0x40018000 0x400>;
 594                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 595                         clocks = <&rcc UART7_K>;
 596                         status = "disabled";
 597                 };
 598
 599                 uart8: serial@40019000 {
 600                         compatible = "st,stm32h7-uart";
 601                         reg = <0x40019000 0x400>;
 602                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 603                         clocks = <&rcc UART8_K>;
 604                         status = "disabled";
 605                 };
 606
 607                 timers1: timer@44000000 {
 608                         #address-cells = <1>;
 609                         #size-cells = <0>;
 610                         compatible = "st,stm32-timers";
 611                         reg = <0x44000000 0x400>;
 612                         clocks = <&rcc TIM1_K>;
 613                         clock-names = "int";
 614                         dmas = <&dmamux1 11 0x400 0x1>,
 615                                <&dmamux1 12 0x400 0x1>,
 616                                <&dmamux1 13 0x400 0x1>,
 617                                <&dmamux1 14 0x400 0x1>,
 618                                <&dmamux1 15 0x400 0x1>,
 619                                <&dmamux1 16 0x400 0x1>,
 620                                <&dmamux1 17 0x400 0x1>;
 621                         dma-names = "ch1", "ch2", "ch3", "ch4",
 622                                     "up", "trig", "com";
 623                         status = "disabled";
 624
 625                         pwm {
 626                                 compatible = "st,stm32-pwm";
 627                                 #pwm-cells = <3>;
 628                                 status = "disabled";
 629                         };
 630
 631                         timer@0 {
 632                                 compatible = "st,stm32h7-timer-trigger";
 633                                 reg = <0>;
 634                                 status = "disabled";
 635                         };
 636
 637                         counter {
 638                                 compatible = "st,stm32-timer-counter";
 639                                 status = "disabled";
 640                         };
 641                 };
 642
 643                 timers8: timer@44001000 {
 644                         #address-cells = <1>;
 645                         #size-cells = <0>;
 646                         compatible = "st,stm32-timers";
 647                         reg = <0x44001000 0x400>;
 648                         clocks = <&rcc TIM8_K>;
 649                         clock-names = "int";
 650                         dmas = <&dmamux1 47 0x400 0x1>,
 651                                <&dmamux1 48 0x400 0x1>,
 652                                <&dmamux1 49 0x400 0x1>,
 653                                <&dmamux1 50 0x400 0x1>,
 654                                <&dmamux1 51 0x400 0x1>,
 655                                <&dmamux1 52 0x400 0x1>,
 656                                <&dmamux1 53 0x400 0x1>;
 657                         dma-names = "ch1", "ch2", "ch3", "ch4",
 658                                     "up", "trig", "com";
 659                         status = "disabled";
 660
 661                         pwm {
 662                                 compatible = "st,stm32-pwm";
 663                                 #pwm-cells = <3>;
 664                                 status = "disabled";
 665                         };
 666
 667                         timer@7 {
 668                                 compatible = "st,stm32h7-timer-trigger";
 669                                 reg = <7>;
 670                                 status = "disabled";
 671                         };
 672
 673                         counter {
 674                                 compatible = "st,stm32-timer-counter";
 675                                 status = "disabled";
 676                         };
 677                 };
 678
 679                 usart6: serial@44003000 {
 680                         compatible = "st,stm32h7-uart";
 681                         reg = <0x44003000 0x400>;
 682                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 683                         clocks = <&rcc USART6_K>;
 684                         status = "disabled";
 685                 };
 686
 687                 spi1: spi@44004000 {
 688                         #address-cells = <1>;
 689                         #size-cells = <0>;
 690                         compatible = "st,stm32h7-spi";
 691                         reg = <0x44004000 0x400>;
 692                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 693                         clocks = <&rcc SPI1_K>;
 694                         resets = <&rcc SPI1_R>;
 695                         dmas = <&dmamux1 37 0x400 0x05>,
 696                                <&dmamux1 38 0x400 0x05>;
 697                         dma-names = "rx", "tx";
 698                         status = "disabled";
 699                 };
 700
 701                 i2s1: audio-controller@44004000 {
 702                         compatible = "st,stm32h7-i2s";
 703                         #sound-dai-cells = <0>;
 704                         reg = <0x44004000 0x400>;
 705                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 706                         dmas = <&dmamux1 37 0x400 0x01>,
 707                                <&dmamux1 38 0x400 0x01>;
 708                         dma-names = "rx", "tx";
 709                         status = "disabled";
 710                 };
 711
 712                 spi4: spi@44005000 {
 713                         #address-cells = <1>;
 714                         #size-cells = <0>;
 715                         compatible = "st,stm32h7-spi";
 716                         reg = <0x44005000 0x400>;
 717                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 718                         clocks = <&rcc SPI4_K>;
 719                         resets = <&rcc SPI4_R>;
 720                         dmas = <&dmamux1 83 0x400 0x05>,
 721                                <&dmamux1 84 0x400 0x05>;
 722                         dma-names = "rx", "tx";
 723                         status = "disabled";
 724                 };
 725
 726                 timers15: timer@44006000 {
 727                         #address-cells = <1>;
 728                         #size-cells = <0>;
 729                         compatible = "st,stm32-timers";
 730                         reg = <0x44006000 0x400>;
 731                         clocks = <&rcc TIM15_K>;
 732                         clock-names = "int";
 733                         dmas = <&dmamux1 105 0x400 0x1>,
 734                                <&dmamux1 106 0x400 0x1>,
 735                                <&dmamux1 107 0x400 0x1>,
 736                                <&dmamux1 108 0x400 0x1>;
 737                         dma-names = "ch1", "up", "trig", "com";
 738                         status = "disabled";
 739
 740                         pwm {
 741                                 compatible = "st,stm32-pwm";
 742                                 #pwm-cells = <3>;
 743                                 status = "disabled";
 744                         };
 745
 746                         timer@14 {
 747                                 compatible = "st,stm32h7-timer-trigger";
 748                                 reg = <14>;
 749                                 status = "disabled";
 750                         };
 751                 };
 752
 753                 timers16: timer@44007000 {
 754                         #address-cells = <1>;
 755                         #size-cells = <0>;
 756                         compatible = "st,stm32-timers";
 757                         reg = <0x44007000 0x400>;
 758                         clocks = <&rcc TIM16_K>;
 759                         clock-names = "int";
 760                         dmas = <&dmamux1 109 0x400 0x1>,
 761                                <&dmamux1 110 0x400 0x1>;
 762                         dma-names = "ch1", "up";
 763                         status = "disabled";
 764
 765                         pwm {
 766                                 compatible = "st,stm32-pwm";
 767                                 #pwm-cells = <3>;
 768                                 status = "disabled";
 769                         };
 770                         timer@15 {
 771                                 compatible = "st,stm32h7-timer-trigger";
 772                                 reg = <15>;
 773                                 status = "disabled";
 774                         };
 775                 };
 776
 777                 timers17: timer@44008000 {
 778                         #address-cells = <1>;
 779                         #size-cells = <0>;
 780                         compatible = "st,stm32-timers";
 781                         reg = <0x44008000 0x400>;
 782                         clocks = <&rcc TIM17_K>;
 783                         clock-names = "int";
 784                         dmas = <&dmamux1 111 0x400 0x1>,
 785                                <&dmamux1 112 0x400 0x1>;
 786                         dma-names = "ch1", "up";
 787                         status = "disabled";
 788
 789                         pwm {
 790                                 compatible = "st,stm32-pwm";
 791                                 #pwm-cells = <3>;
 792                                 status = "disabled";
 793                         };
 794
 795                         timer@16 {
 796                                 compatible = "st,stm32h7-timer-trigger";
 797                                 reg = <16>;
 798                                 status = "disabled";
 799                         };
 800                 };
 801
 802                 spi5: spi@44009000 {
 803                         #address-cells = <1>;
 804                         #size-cells = <0>;
 805                         compatible = "st,stm32h7-spi";
 806                         reg = <0x44009000 0x400>;
 807                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 808                         clocks = <&rcc SPI5_K>;
 809                         resets = <&rcc SPI5_R>;
 810                         dmas = <&dmamux1 85 0x400 0x05>,
 811                                <&dmamux1 86 0x400 0x05>;
 812                         dma-names = "rx", "tx";
 813                         status = "disabled";
 814                 };
 815
 816                 sai1: sai@4400a000 {
 817                         compatible = "st,stm32h7-sai";
 818                         #address-cells = <1>;
 819                         #size-cells = <1>;
 820                         ranges = <0 0x4400a000 0x400>;
 821                         reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
 822                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 823                         resets = <&rcc SAI1_R>;
 824                         status = "disabled";
 825
 826                         sai1a: audio-controller@4400a004 {
 827                                 #sound-dai-cells = <0>;
 828
 829                                 compatible = "st,stm32-sai-sub-a";
 830                                 reg = <0x4 0x1c>;
 831                                 clocks = <&rcc SAI1_K>;
 832                                 clock-names = "sai_ck";
 833                                 dmas = <&dmamux1 87 0x400 0x01>;
 834                                 status = "disabled";
 835                         };
 836
 837                         sai1b: audio-controller@4400a024 {
 838                                 #sound-dai-cells = <0>;
 839                                 compatible = "st,stm32-sai-sub-b";
 840                                 reg = <0x24 0x1c>;
 841                                 clocks = <&rcc SAI1_K>;
 842                                 clock-names = "sai_ck";
 843                                 dmas = <&dmamux1 88 0x400 0x01>;
 844                                 status = "disabled";
 845                         };
 846                 };
 847
 848                 sai2: sai@4400b000 {
 849                         compatible = "st,stm32h7-sai";
 850                         #address-cells = <1>;
 851                         #size-cells = <1>;
 852                         ranges = <0 0x4400b000 0x400>;
 853                         reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
 854                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 855                         resets = <&rcc SAI2_R>;
 856                         status = "disabled";
 857
 858                         sai2a: audio-controller@4400b004 {
 859                                 #sound-dai-cells = <0>;
 860                                 compatible = "st,stm32-sai-sub-a";
 861                                 reg = <0x4 0x1c>;
 862                                 clocks = <&rcc SAI2_K>;
 863                                 clock-names = "sai_ck";
 864                                 dmas = <&dmamux1 89 0x400 0x01>;
 865                                 status = "disabled";
 866                         };
 867
 868                         sai2b: audio-controller@4400b024 {
 869                                 #sound-dai-cells = <0>;
 870                                 compatible = "st,stm32-sai-sub-b";
 871                                 reg = <0x24 0x1c>;
 872                                 clocks = <&rcc SAI2_K>;
 873                                 clock-names = "sai_ck";
 874                                 dmas = <&dmamux1 90 0x400 0x01>;
 875                                 status = "disabled";
 876                         };
 877                 };
 878
 879                 sai3: sai@4400c000 {
 880                         compatible = "st,stm32h7-sai";
 881                         #address-cells = <1>;
 882                         #size-cells = <1>;
 883                         ranges = <0 0x4400c000 0x400>;
 884                         reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
 885                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 886                         resets = <&rcc SAI3_R>;
 887                         status = "disabled";
 888
 889                         sai3a: audio-controller@4400c004 {
 890                                 #sound-dai-cells = <0>;
 891                                 compatible = "st,stm32-sai-sub-a";
 892                                 reg = <0x04 0x1c>;
 893                                 clocks = <&rcc SAI3_K>;
 894                                 clock-names = "sai_ck";
 895                                 dmas = <&dmamux1 113 0x400 0x01>;
 896                                 status = "disabled";
 897                         };
 898
 899                         sai3b: audio-controller@4400c024 {
 900                                 #sound-dai-cells = <0>;
 901                                 compatible = "st,stm32-sai-sub-b";
 902                                 reg = <0x24 0x1c>;
 903                                 clocks = <&rcc SAI3_K>;
 904                                 clock-names = "sai_ck";
 905                                 dmas = <&dmamux1 114 0x400 0x01>;
 906                                 status = "disabled";
 907                         };
 908                 };
 909
 910                 dfsdm: dfsdm@4400d000 {
 911                         compatible = "st,stm32mp1-dfsdm";
 912                         reg = <0x4400d000 0x800>;
 913                         clocks = <&rcc DFSDM_K>;
 914                         clock-names = "dfsdm";
 915                         #address-cells = <1>;
 916                         #size-cells = <0>;
 917                         status = "disabled";
 918
 919                         dfsdm0: filter@0 {
 920                                 compatible = "st,stm32-dfsdm-adc";
 921                                 #io-channel-cells = <1>;
 922                                 reg = <0>;
 923                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 924                                 dmas = <&dmamux1 101 0x400 0x01>;
 925                                 dma-names = "rx";
 926                                 status = "disabled";
 927                         };
 928
 929                         dfsdm1: filter@1 {
 930                                 compatible = "st,stm32-dfsdm-adc";
 931                                 #io-channel-cells = <1>;
 932                                 reg = <1>;
 933                                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 934                                 dmas = <&dmamux1 102 0x400 0x01>;
 935                                 dma-names = "rx";
 936                                 status = "disabled";
 937                         };
 938
 939                         dfsdm2: filter@2 {
 940                                 compatible = "st,stm32-dfsdm-adc";
 941                                 #io-channel-cells = <1>;
 942                                 reg = <2>;
 943                                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 944                                 dmas = <&dmamux1 103 0x400 0x01>;
 945                                 dma-names = "rx";
 946                                 status = "disabled";
 947                         };
 948
 949                         dfsdm3: filter@3 {
 950                                 compatible = "st,stm32-dfsdm-adc";
 951                                 #io-channel-cells = <1>;
 952                                 reg = <3>;
 953                                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 954                                 dmas = <&dmamux1 104 0x400 0x01>;
 955                                 dma-names = "rx";
 956                                 status = "disabled";
 957                         };
 958
 959                         dfsdm4: filter@4 {
 960                                 compatible = "st,stm32-dfsdm-adc";
 961                                 #io-channel-cells = <1>;
 962                                 reg = <4>;
 963                                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 964                                 dmas = <&dmamux1 91 0x400 0x01>;
 965                                 dma-names = "rx";
 966                                 status = "disabled";
 967                         };
 968
 969                         dfsdm5: filter@5 {
 970                                 compatible = "st,stm32-dfsdm-adc";
 971                                 #io-channel-cells = <1>;
 972                                 reg = <5>;
 973                                 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 974                                 dmas = <&dmamux1 92 0x400 0x01>;
 975                                 dma-names = "rx";
 976                                 status = "disabled";
 977                         };
 978                 };
 979
 980                 dma1: dma-controller@48000000 {
 981                         compatible = "st,stm32-dma";
 982                         reg = <0x48000000 0x400>;
 983                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 984                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 985                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 986                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 987                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 988                                      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 989                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 990                                      <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 991                         clocks = <&rcc DMA1>;
 992                         resets = <&rcc DMA1_R>;
 993                         #dma-cells = <4>;
 994                         st,mem2mem;
 995                         dma-requests = <8>;
 996                 };
 997
 998                 dma2: dma-controller@48001000 {
 999                         compatible = "st,stm32-dma";
1000                         reg = <0x48001000 0x400>;
1001                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
1002                                      <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
1003                                      <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
1004                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
1005                                      <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
1006                                      <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
1007                                      <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1008                                      <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1009                         clocks = <&rcc DMA2>;
1010                         resets = <&rcc DMA2_R>;
1011                         #dma-cells = <4>;
1012                         st,mem2mem;
1013                         dma-requests = <8>;
1014                 };
1015
1016                 dmamux1: dma-router@48002000 {
1017                         compatible = "st,stm32h7-dmamux";
1018                         reg = <0x48002000 0x1c>;
1019                         #dma-cells = <3>;
1020                         dma-requests = <128>;
1021                         dma-masters = <&dma1 &dma2>;
1022                         dma-channels = <16>;
1023                         clocks = <&rcc DMAMUX>;
1024                         resets = <&rcc DMAMUX_R>;
1025                 };
1026
1027                 adc: adc@48003000 {
1028                         compatible = "st,stm32mp1-adc-core";
1029                         reg = <0x48003000 0x400>;
1030                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
1031                                      <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1032                         clocks = <&rcc ADC12>, <&rcc ADC12_K>;
1033                         clock-names = "bus", "adc";
1034                         interrupt-controller;
1035                         st,syscfg = <&syscfg>;
1036                         #interrupt-cells = <1>;
1037                         #address-cells = <1>;
1038                         #size-cells = <0>;
1039                         status = "disabled";
1040
1041                         adc1: adc@0 {
1042                                 compatible = "st,stm32mp1-adc";
1043                                 #io-channel-cells = <1>;
1044                                 reg = <0x0>;
1045                                 interrupt-parent = <&adc>;
1046                                 interrupts = <0>;
1047                                 dmas = <&dmamux1 9 0x400 0x01>;
1048                                 dma-names = "rx";
1049                                 status = "disabled";
1050                         };
1051
1052                         adc2: adc@100 {
1053                                 compatible = "st,stm32mp1-adc";
1054                                 #io-channel-cells = <1>;
1055                                 reg = <0x100>;
1056                                 interrupt-parent = <&adc>;
1057                                 interrupts = <1>;
1058                                 dmas = <&dmamux1 10 0x400 0x01>;
1059                                 dma-names = "rx";
1060                                 status = "disabled";
1061                         };
1062                 };
1063
1064                 sdmmc3: sdmmc@48004000 {
1065                         compatible = "arm,pl18x", "arm,primecell";
1066                         arm,primecell-periphid = <0x10153180>;
1067                         reg = <0x48004000 0x400>;
1068                         interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
1069                         interrupt-names = "cmd_irq";
1070                         clocks = <&rcc SDMMC3_K>;
1071                         clock-names = "apb_pclk";
1072                         resets = <&rcc SDMMC3_R>;
1073                         cap-sd-highspeed;
1074                         cap-mmc-highspeed;
1075                         max-frequency = <120000000>;
1076                         status = "disabled";
1077                 };
1078
1079                 usbotg_hs: usb-otg@49000000 {
1080                         compatible = "st,stm32mp15-hsotg", "snps,dwc2";
1081                         reg = <0x49000000 0x10000>;
1082                         clocks = <&rcc USBO_K>;
1083                         clock-names = "otg";
1084                         resets = <&rcc USBO_R>;
1085                         reset-names = "dwc2";
1086                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1087                         g-rx-fifo-size = <256>;
1088                         g-np-tx-fifo-size = <32>;
1089                         g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
1090                         dr_mode = "otg";
1091                         usb33d-supply = <&usb33>;
1092                         status = "disabled";
1093                 };
1094
1095                 hwspinlock: hwspinlock@4c000000 {
1096                         compatible = "st,stm32-hwspinlock";
1097                         #hwlock-cells = <1>;
1098                         reg = <0x4c000000 0x400>;
1099                         clocks = <&rcc HSEM>;
1100                         clock-names = "hwspinlock";
1101                 };
1102
1103                 ipcc: mailbox@4c001000 {
1104                         compatible = "st,stm32mp1-ipcc";
1105                         #mbox-cells = <1>;
1106                         reg = <0x4c001000 0x400>;
1107                         st,proc-id = <0>;
1108                         interrupts-extended =
1109                                 <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1110                                 <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1111                                 <&exti 61 1>;
1112                         interrupt-names = "rx", "tx", "wakeup";
1113                         clocks = <&rcc IPCC>;
1114                         wakeup-source;
1115                         status = "disabled";
1116                 };
1117
1118                 dcmi: dcmi@4c006000 {
1119                         compatible = "st,stm32-dcmi";
1120                         reg = <0x4c006000 0x400>;
1121                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1122                         resets = <&rcc CAMITF_R>;
1123                         clocks = <&rcc DCMI>;
1124                         clock-names = "mclk";
1125                         dmas = <&dmamux1 75 0x400 0x0d>;
1126                         dma-names = "tx";
1127                         status = "disabled";
1128                 };
1129
1130                 rcc: rcc@50000000 {
1131                         compatible = "st,stm32mp1-rcc", "syscon";
1132                         reg = <0x50000000 0x1000>;
1133                         #clock-cells = <1>;
1134                         #reset-cells = <1>;
1135                 };
1136
1137                 pwr_regulators: pwr@50001000 {
1138                         compatible = "st,stm32mp1,pwr-reg";
1139                         reg = <0x50001000 0x10>;
1140
1141                         reg11: reg11 {
1142                                 regulator-name = "reg11";
1143                                 regulator-min-microvolt = <1100000>;
1144                                 regulator-max-microvolt = <1100000>;
1145                         };
1146
1147                         reg18: reg18 {
1148                                 regulator-name = "reg18";
1149                                 regulator-min-microvolt = <1800000>;
1150                                 regulator-max-microvolt = <1800000>;
1151                         };
1152
1153                         usb33: usb33 {
1154                                 regulator-name = "usb33";
1155                                 regulator-min-microvolt = <3300000>;
1156                                 regulator-max-microvolt = <3300000>;
1157                         };
1158                 };
1159
1160                 exti: interrupt-controller@5000d000 {
1161                         compatible = "st,stm32mp1-exti", "syscon";
1162                         interrupt-controller;
1163                         #interrupt-cells = <2>;
1164                         reg = <0x5000d000 0x400>;
1165                 };
1166
1167                 syscfg: syscon@50020000 {
1168                         compatible = "st,stm32mp157-syscfg", "syscon";
1169                         reg = <0x50020000 0x400>;
1170                         clocks = <&rcc SYSCFG>;
1171                 };
1172
1173                 lptimer2: timer@50021000 {
1174                         #address-cells = <1>;
1175                         #size-cells = <0>;
1176                         compatible = "st,stm32-lptimer";
1177                         reg = <0x50021000 0x400>;
1178                         clocks = <&rcc LPTIM2_K>;
1179                         clock-names = "mux";
1180                         status = "disabled";
1181
1182                         pwm {
1183                                 compatible = "st,stm32-pwm-lp";
1184                                 #pwm-cells = <3>;
1185                                 status = "disabled";
1186                         };
1187
1188                         trigger@1 {
1189                                 compatible = "st,stm32-lptimer-trigger";
1190                                 reg = <1>;
1191                                 status = "disabled";
1192                         };
1193
1194                         counter {
1195                                 compatible = "st,stm32-lptimer-counter";
1196                                 status = "disabled";
1197                         };
1198                 };
1199
1200                 lptimer3: timer@50022000 {
1201                         #address-cells = <1>;
1202                         #size-cells = <0>;
1203                         compatible = "st,stm32-lptimer";
1204                         reg = <0x50022000 0x400>;
1205                         clocks = <&rcc LPTIM3_K>;
1206                         clock-names = "mux";
1207                         status = "disabled";
1208
1209                         pwm {
1210                                 compatible = "st,stm32-pwm-lp";
1211                                 #pwm-cells = <3>;
1212                                 status = "disabled";
1213                         };
1214
1215                         trigger@2 {
1216                                 compatible = "st,stm32-lptimer-trigger";
1217                                 reg = <2>;
1218                                 status = "disabled";
1219                         };
1220                 };
1221
1222                 lptimer4: timer@50023000 {
1223                         compatible = "st,stm32-lptimer";
1224                         reg = <0x50023000 0x400>;
1225                         clocks = <&rcc LPTIM4_K>;
1226                         clock-names = "mux";
1227                         status = "disabled";
1228
1229                         pwm {
1230                                 compatible = "st,stm32-pwm-lp";
1231                                 #pwm-cells = <3>;
1232                                 status = "disabled";
1233                         };
1234                 };
1235
1236                 lptimer5: timer@50024000 {
1237                         compatible = "st,stm32-lptimer";
1238                         reg = <0x50024000 0x400>;
1239                         clocks = <&rcc LPTIM5_K>;
1240                         clock-names = "mux";
1241                         status = "disabled";
1242
1243                         pwm {
1244                                 compatible = "st,stm32-pwm-lp";
1245                                 #pwm-cells = <3>;
1246                                 status = "disabled";
1247                         };
1248                 };
1249
1250                 vrefbuf: vrefbuf@50025000 {
1251                         compatible = "st,stm32-vrefbuf";
1252                         reg = <0x50025000 0x8>;
1253                         regulator-min-microvolt = <1500000>;
1254                         regulator-max-microvolt = <2500000>;
1255                         clocks = <&rcc VREF>;
1256                         status = "disabled";
1257                 };
1258
1259                 sai4: sai@50027000 {
1260                         compatible = "st,stm32h7-sai";
1261                         #address-cells = <1>;
1262                         #size-cells = <1>;
1263                         ranges = <0 0x50027000 0x400>;
1264                         reg = <0x50027000 0x4>, <0x500273f0 0x10>;
1265                         interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
1266                         resets = <&rcc SAI4_R>;
1267                         status = "disabled";
1268
1269                         sai4a: audio-controller@50027004 {
1270                                 #sound-dai-cells = <0>;
1271                                 compatible = "st,stm32-sai-sub-a";
1272                                 reg = <0x04 0x1c>;
1273                                 clocks = <&rcc SAI4_K>;
1274                                 clock-names = "sai_ck";
1275                                 dmas = <&dmamux1 99 0x400 0x01>;
1276                                 status = "disabled";
1277                         };
1278
1279                         sai4b: audio-controller@50027024 {
1280                                 #sound-dai-cells = <0>;
1281                                 compatible = "st,stm32-sai-sub-b";
1282                                 reg = <0x24 0x1c>;
1283                                 clocks = <&rcc SAI4_K>;
1284                                 clock-names = "sai_ck";
1285                                 dmas = <&dmamux1 100 0x400 0x01>;
1286                                 status = "disabled";
1287                         };
1288                 };
1289
1290                 dts: thermal@50028000 {
1291                         compatible = "st,stm32-thermal";
1292                         reg = <0x50028000 0x100>;
1293                         interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1294                         clocks = <&rcc TMPSENS>;
1295                         clock-names = "pclk";
1296                         #thermal-sensor-cells = <0>;
1297                         status = "disabled";
1298                 };
1299
1300                 hash1: hash@54002000 {
1301                         compatible = "st,stm32f756-hash";
1302                         reg = <0x54002000 0x400>;
1303                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1304                         clocks = <&rcc HASH1>;
1305                         resets = <&rcc HASH1_R>;
1306                         dmas = <&mdma1 31 0x10 0x1000A02 0x0 0x0>;
1307                         dma-names = "in";
1308                         dma-maxburst = <2>;
1309                         status = "disabled";
1310                 };
1311
1312                 rng1: rng@54003000 {
1313                         compatible = "st,stm32-rng";
1314                         reg = <0x54003000 0x400>;
1315                         clocks = <&rcc RNG1_K>;
1316                         resets = <&rcc RNG1_R>;
1317                         status = "disabled";
1318                 };
1319
1320                 mdma1: dma-controller@58000000 {
1321                         compatible = "st,stm32h7-mdma";
1322                         reg = <0x58000000 0x1000>;
1323                         interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1324                         clocks = <&rcc MDMA>;
1325                         resets = <&rcc MDMA_R>;
1326                         #dma-cells = <5>;
1327                         dma-channels = <32>;
1328                         dma-requests = <48>;
1329                 };
1330
1331                 fmc: nand-controller@58002000 {
1332                         compatible = "st,stm32mp15-fmc2";
1333                         reg = <0x58002000 0x1000>,
1334                               <0x80000000 0x1000>,
1335                               <0x88010000 0x1000>,
1336                               <0x88020000 0x1000>,
1337                               <0x81000000 0x1000>,
1338                               <0x89010000 0x1000>,
1339                               <0x89020000 0x1000>;
1340                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1341                         dmas = <&mdma1 20 0x10 0x12000a02 0x0 0x0>,
1342                                <&mdma1 20 0x10 0x12000a08 0x0 0x0>,
1343                                <&mdma1 21 0x10 0x12000a0a 0x0 0x0>;
1344                         dma-names = "tx", "rx", "ecc";
1345                         clocks = <&rcc FMC_K>;
1346                         resets = <&rcc FMC_R>;
1347                         status = "disabled";
1348                 };
1349
1350                 qspi: spi@58003000 {
1351                         compatible = "st,stm32f469-qspi";
1352                         reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
1353                         reg-names = "qspi", "qspi_mm";
1354                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
1355                         dmas = <&mdma1 22 0x10 0x100002 0x0 0x0>,
1356                                <&mdma1 22 0x10 0x100008 0x0 0x0>;
1357                         dma-names = "tx", "rx";
1358                         clocks = <&rcc QSPI_K>;
1359                         resets = <&rcc QSPI_R>;
1360                         status = "disabled";
1361                 };
1362
1363                 sdmmc1: sdmmc@58005000 {
1364                         compatible = "arm,pl18x", "arm,primecell";
1365                         arm,primecell-periphid = <0x10153180>;
1366                         reg = <0x58005000 0x1000>;
1367                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1368                         interrupt-names = "cmd_irq";
1369                         clocks = <&rcc SDMMC1_K>;
1370                         clock-names = "apb_pclk";
1371                         resets = <&rcc SDMMC1_R>;
1372                         cap-sd-highspeed;
1373                         cap-mmc-highspeed;
1374                         max-frequency = <120000000>;
1375                         status = "disabled";
1376                 };
1377
1378                 sdmmc2: sdmmc@58007000 {
1379                         compatible = "arm,pl18x", "arm,primecell";
1380                         arm,primecell-periphid = <0x10153180>;
1381                         reg = <0x58007000 0x1000>;
1382                         interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
1383                         interrupt-names = "cmd_irq";
1384                         clocks = <&rcc SDMMC2_K>;
1385                         clock-names = "apb_pclk";
1386                         resets = <&rcc SDMMC2_R>;
1387                         cap-sd-highspeed;
1388                         cap-mmc-highspeed;
1389                         max-frequency = <120000000>;
1390                         status = "disabled";
1391                 };
1392
1393                 crc1: crc@58009000 {
1394                         compatible = "st,stm32f7-crc";
1395                         reg = <0x58009000 0x400>;
1396                         clocks = <&rcc CRC1>;
1397                         status = "disabled";
1398                 };
1399
1400                 stmmac_axi_config_0: stmmac-axi-config {
1401                         snps,wr_osr_lmt = <0x7>;
1402                         snps,rd_osr_lmt = <0x7>;
1403                         snps,blen = <0 0 0 0 16 8 4>;
1404                 };
1405
1406                 ethernet0: ethernet@5800a000 {
1407                         compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
1408                         reg = <0x5800a000 0x2000>;
1409                         reg-names = "stmmaceth";
1410                         interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1411                         interrupt-names = "macirq";
1412                         clock-names = "stmmaceth",
1413                                       "mac-clk-tx",
1414                                       "mac-clk-rx",
1415                                       "eth-ck",
1416                                       "ethstp",
1417                                       "syscfg-clk";
1418                         clocks = <&rcc ETHMAC>,
1419                                  <&rcc ETHTX>,
1420                                  <&rcc ETHRX>,
1421                                  <&rcc ETHCK_K>,
1422                                  <&rcc ETHSTP>,
1423                                  <&rcc SYSCFG>;
1424                         st,syscon = <&syscfg 0x4>;
1425                         snps,mixed-burst;
1426                         snps,pbl = <2>;
1427                         snps,en-tx-lpi-clockgating;
1428                         snps,axi-config = <&stmmac_axi_config_0>;
1429                         snps,tso;
1430                         status = "disabled";
1431                 };
1432
1433                 usbh_ohci: usbh-ohci@5800c000 {
1434                         compatible = "generic-ohci";
1435                         reg = <0x5800c000 0x1000>;
1436                         clocks = <&rcc USBH>;
1437                         resets = <&rcc USBH_R>;
1438                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1439                         status = "disabled";
1440                 };
1441
1442                 usbh_ehci: usbh-ehci@5800d000 {
1443                         compatible = "generic-ehci";
1444                         reg = <0x5800d000 0x1000>;
1445                         clocks = <&rcc USBH>;
1446                         resets = <&rcc USBH_R>;
1447                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1448                         companion = <&usbh_ohci>;
1449                         status = "disabled";
1450                 };
1451
1452                 ltdc: display-controller@5a001000 {
1453                         compatible = "st,stm32-ltdc";
1454                         reg = <0x5a001000 0x400>;
1455                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1456                                      <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1457                         clocks = <&rcc LTDC_PX>;
1458                         clock-names = "lcd";
1459                         resets = <&rcc LTDC_R>;
1460                         status = "disabled";
1461                 };
1462
1463                 iwdg2: watchdog@5a002000 {
1464                         compatible = "st,stm32mp1-iwdg";
1465                         reg = <0x5a002000 0x400>;
1466                         clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
1467                         clock-names = "pclk", "lsi";
1468                         status = "disabled";
1469                 };
1470
1471                 usbphyc: usbphyc@5a006000 {
1472                         #address-cells = <1>;
1473                         #size-cells = <0>;
1474                         compatible = "st,stm32mp1-usbphyc";
1475                         reg = <0x5a006000 0x1000>;
1476                         clocks = <&rcc USBPHY_K>;
1477                         resets = <&rcc USBPHY_R>;
1478                         vdda1v1-supply = <&reg11>;
1479                         vdda1v8-supply = <&reg18>;
1480                         status = "disabled";
1481
1482                         usbphyc_port0: usb-phy@0 {
1483                                 #phy-cells = <0>;
1484                                 reg = <0>;
1485                         };
1486
1487                         usbphyc_port1: usb-phy@1 {
1488                                 #phy-cells = <1>;
1489                                 reg = <1>;
1490                         };
1491                 };
1492
1493                 usart1: serial@5c000000 {
1494                         compatible = "st,stm32h7-uart";
1495                         reg = <0x5c000000 0x400>;
1496                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1497                         clocks = <&rcc USART1_K>;
1498                         status = "disabled";
1499                 };
1500
1501                 spi6: spi@5c001000 {
1502                         #address-cells = <1>;
1503                         #size-cells = <0>;
1504                         compatible = "st,stm32h7-spi";
1505                         reg = <0x5c001000 0x400>;
1506                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1507                         clocks = <&rcc SPI6_K>;
1508                         resets = <&rcc SPI6_R>;
1509                         dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
1510                                <&mdma1 35 0x0 0x40002 0x0 0x0>;
1511                         dma-names = "rx", "tx";
1512                         status = "disabled";
1513                 };
1514
1515                 i2c4: i2c@5c002000 {
1516                         compatible = "st,stm32f7-i2c";
1517                         reg = <0x5c002000 0x400>;
1518                         interrupt-names = "event", "error";
1519                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1520                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1521                         clocks = <&rcc I2C4_K>;
1522                         resets = <&rcc I2C4_R>;
1523                         #address-cells = <1>;
1524                         #size-cells = <0>;
1525                         wakeup-source;
1526                         status = "disabled";
1527                 };
1528
1529                 rtc: rtc@5c004000 {
1530                         compatible = "st,stm32mp1-rtc";
1531                         reg = <0x5c004000 0x400>;
1532                         clocks = <&rcc RTCAPB>, <&rcc RTC>;
1533                         clock-names = "pclk", "rtc_ck";
1534                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1535                         status = "disabled";
1536                 };
1537
1538                 bsec: efuse@5c005000 {
1539                         compatible = "st,stm32mp15-bsec";
1540                         reg = <0x5c005000 0x400>;
1541                         #address-cells = <1>;
1542                         #size-cells = <1>;
1543                         part_number_otp: part_number_otp@4 {
1544                                 reg = <0x4 0x1>;
1545                         };
1546                         ts_cal1: calib@5c {
1547                                 reg = <0x5c 0x2>;
1548                         };
1549                         ts_cal2: calib@5e {
1550                                 reg = <0x5e 0x2>;
1551                         };
1552                 };
1553
1554                 i2c6: i2c@5c009000 {
1555                         compatible = "st,stm32f7-i2c";
1556                         reg = <0x5c009000 0x400>;
1557                         interrupt-names = "event", "error";
1558                         interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1559                                      <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1560                         clocks = <&rcc I2C6_K>;
1561                         resets = <&rcc I2C6_R>;
1562                         #address-cells = <1>;
1563                         #size-cells = <0>;
1564                         wakeup-source;
1565                         status = "disabled";
1566                 };
1567
1568                 /*
1569                  * Break node order to solve dependency probe issue between
1570                  * pinctrl and exti.
1571                  */
1572                 pinctrl: pin-controller@50002000 {
1573                         #address-cells = <1>;
1574                         #size-cells = <1>;
1575                         compatible = "st,stm32mp157-pinctrl";
1576                         ranges = <0 0x50002000 0xa400>;
1577                         interrupt-parent = <&exti>;
1578                         st,syscfg = <&exti 0x60 0xff>;
1579                         hwlocks = <&hwspinlock 0>;
1580                         pins-are-numbered;
1581
1582                         gpioa: gpio@50002000 {
1583                                 gpio-controller;
1584                                 #gpio-cells = <2>;
1585                                 interrupt-controller;
1586                                 #interrupt-cells = <2>;
1587                                 reg = <0x0 0x400>;
1588                                 clocks = <&rcc GPIOA>;
1589                                 st,bank-name = "GPIOA";
1590                                 status = "disabled";
1591                         };
1592
1593                         gpiob: gpio@50003000 {
1594                                 gpio-controller;
1595                                 #gpio-cells = <2>;
1596                                 interrupt-controller;
1597                                 #interrupt-cells = <2>;
1598                                 reg = <0x1000 0x400>;
1599                                 clocks = <&rcc GPIOB>;
1600                                 st,bank-name = "GPIOB";
1601                                 status = "disabled";
1602                         };
1603
1604                         gpioc: gpio@50004000 {
1605                                 gpio-controller;
1606                                 #gpio-cells = <2>;
1607                                 interrupt-controller;
1608                                 #interrupt-cells = <2>;
1609                                 reg = <0x2000 0x400>;
1610                                 clocks = <&rcc GPIOC>;
1611                                 st,bank-name = "GPIOC";
1612                                 status = "disabled";
1613                         };
1614
1615                         gpiod: gpio@50005000 {
1616                                 gpio-controller;
1617                                 #gpio-cells = <2>;
1618                                 interrupt-controller;
1619                                 #interrupt-cells = <2>;
1620                                 reg = <0x3000 0x400>;
1621                                 clocks = <&rcc GPIOD>;
1622                                 st,bank-name = "GPIOD";
1623                                 status = "disabled";
1624                         };
1625
1626                         gpioe: gpio@50006000 {
1627                                 gpio-controller;
1628                                 #gpio-cells = <2>;
1629                                 interrupt-controller;
1630                                 #interrupt-cells = <2>;
1631                                 reg = <0x4000 0x400>;
1632                                 clocks = <&rcc GPIOE>;
1633                                 st,bank-name = "GPIOE";
1634                                 status = "disabled";
1635                         };
1636
1637                         gpiof: gpio@50007000 {
1638                                 gpio-controller;
1639                                 #gpio-cells = <2>;
1640                                 interrupt-controller;
1641                                 #interrupt-cells = <2>;
1642                                 reg = <0x5000 0x400>;
1643                                 clocks = <&rcc GPIOF>;
1644                                 st,bank-name = "GPIOF";
1645                                 status = "disabled";
1646                         };
1647
1648                         gpiog: gpio@50008000 {
1649                                 gpio-controller;
1650                                 #gpio-cells = <2>;
1651                                 interrupt-controller;
1652                                 #interrupt-cells = <2>;
1653                                 reg = <0x6000 0x400>;
1654                                 clocks = <&rcc GPIOG>;
1655                                 st,bank-name = "GPIOG";
1656                                 status = "disabled";
1657                         };
1658
1659                         gpioh: gpio@50009000 {
1660                                 gpio-controller;
1661                                 #gpio-cells = <2>;
1662                                 interrupt-controller;
1663                                 #interrupt-cells = <2>;
1664                                 reg = <0x7000 0x400>;
1665                                 clocks = <&rcc GPIOH>;
1666                                 st,bank-name = "GPIOH";
1667                                 status = "disabled";
1668                         };
1669
1670                         gpioi: gpio@5000a000 {
1671                                 gpio-controller;
1672                                 #gpio-cells = <2>;
1673                                 interrupt-controller;
1674                                 #interrupt-cells = <2>;
1675                                 reg = <0x8000 0x400>;
1676                                 clocks = <&rcc GPIOI>;
1677                                 st,bank-name = "GPIOI";
1678                                 status = "disabled";
1679                         };
1680
1681                         gpioj: gpio@5000b000 {
1682                                 gpio-controller;
1683                                 #gpio-cells = <2>;
1684                                 interrupt-controller;
1685                                 #interrupt-cells = <2>;
1686                                 reg = <0x9000 0x400>;
1687                                 clocks = <&rcc GPIOJ>;
1688                                 st,bank-name = "GPIOJ";
1689                                 status = "disabled";
1690                         };
1691
1692                         gpiok: gpio@5000c000 {
1693                                 gpio-controller;
1694                                 #gpio-cells = <2>;
1695                                 interrupt-controller;
1696                                 #interrupt-cells = <2>;
1697                                 reg = <0xa000 0x400>;
1698                                 clocks = <&rcc GPIOK>;
1699                                 st,bank-name = "GPIOK";
1700                                 status = "disabled";
1701                         };
1702                 };
1703
1704                 pinctrl_z: pin-controller-z@54004000 {
1705                         #address-cells = <1>;
1706                         #size-cells = <1>;
1707                         compatible = "st,stm32mp157-z-pinctrl";
1708                         ranges = <0 0x54004000 0x400>;
1709                         pins-are-numbered;
1710                         interrupt-parent = <&exti>;
1711                         st,syscfg = <&exti 0x60 0xff>;
1712                         hwlocks = <&hwspinlock 0>;
1713
1714                         gpioz: gpio@54004000 {
1715                                 gpio-controller;
1716                                 #gpio-cells = <2>;
1717                                 interrupt-controller;
1718                                 #interrupt-cells = <2>;
1719                                 reg = <0 0x400>;
1720                                 clocks = <&rcc GPIOZ>;
1721                                 st,bank-name = "GPIOZ";
1722                                 st,bank-ioport = <11>;
1723                                 status = "disabled";
1724                         };
1725                 };
1726         };
1727
1728         mlahb: ahb {
1729                 compatible = "st,mlahb", "simple-bus";
1730                 #address-cells = <1>;
1731                 #size-cells = <1>;
1732                 ranges;
1733                 dma-ranges = <0x00000000 0x38000000 0x10000>,
1734                              <0x10000000 0x10000000 0x60000>,
1735                              <0x30000000 0x30000000 0x60000>;
1736
1737                 m4_rproc: m4@10000000 {
1738                         compatible = "st,stm32mp1-m4";
1739                         reg = <0x10000000 0x40000>,
1740                               <0x30000000 0x40000>,
1741                               <0x38000000 0x10000>;
1742                         resets = <&rcc MCU_R>;
1743                         st,syscfg-holdboot = <&rcc 0x10C 0x1>;
1744                         st,syscfg-tz = <&rcc 0x000 0x1>;
1745                         status = "disabled";
1746                 };
1747         };
1748 };