1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/stm32mp1-clks.h>
8 #include <dt-bindings/reset/stm32mp1-resets.h>
19 compatible = "arm,cortex-a7";
20 clock-frequency = <650000000>;
23 operating-points-v2 = <&cpu0_opp_table>;
24 nvmem-cells = <&part_number_otp>;
25 nvmem-cell-names = "part_number";
29 cpu0_opp_table: cpu0-opp-table {
30 compatible = "operating-points-v2";
33 opp-hz = /bits/ 64 <650000000>;
34 opp-microvolt = <1200000>;
35 opp-supported-hw = <0x1>;
38 opp-hz = /bits/ 64 <800000000>;
39 opp-microvolt = <1350000>;
40 opp-supported-hw = <0x2>;
45 compatible = "arm,psci-1.0";
47 cpu_off = <0x84000002>;
48 cpu_on = <0x84000003>;
51 intc: interrupt-controller@a0021000 {
52 compatible = "arm,cortex-a7-gic";
53 #interrupt-cells = <3>;
55 reg = <0xa0021000 0x1000>,
60 compatible = "arm,armv7-timer";
61 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
62 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
63 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
64 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
65 interrupt-parent = <&intc>;
71 compatible = "fixed-clock";
72 clock-frequency = <24000000>;
77 compatible = "fixed-clock";
78 clock-frequency = <64000000>;
83 compatible = "fixed-clock";
84 clock-frequency = <32768>;
89 compatible = "fixed-clock";
90 clock-frequency = <32000>;
95 compatible = "fixed-clock";
96 clock-frequency = <4000000>;
101 cpu_thermal: cpu-thermal {
102 polling-delay-passive = <0>;
104 thermal-sensors = <&dts>;
107 cpu_alert1: cpu-alert1 {
108 temperature = <85000>;
114 temperature = <120000>;
125 booster: regulator-booster {
126 compatible = "st,stm32mp1-booster";
127 st,syscfg = <&syscfg>;
132 compatible = "syscon-reboot";
139 compatible = "simple-bus";
140 #address-cells = <1>;
142 interrupt-parent = <&intc>;
145 timers2: timer@40000000 {
146 #address-cells = <1>;
148 compatible = "st,stm32-timers";
149 reg = <0x40000000 0x400>;
150 clocks = <&rcc TIM2_K>;
152 dmas = <&dmamux1 18 0x400 0x1>,
153 <&dmamux1 19 0x400 0x1>,
154 <&dmamux1 20 0x400 0x1>,
155 <&dmamux1 21 0x400 0x1>,
156 <&dmamux1 22 0x400 0x1>;
157 dma-names = "ch1", "ch2", "ch3", "ch4", "up";
161 compatible = "st,stm32-pwm";
167 compatible = "st,stm32h7-timer-trigger";
173 compatible = "st,stm32-timer-counter";
178 timers3: timer@40001000 {
179 #address-cells = <1>;
181 compatible = "st,stm32-timers";
182 reg = <0x40001000 0x400>;
183 clocks = <&rcc TIM3_K>;
185 dmas = <&dmamux1 23 0x400 0x1>,
186 <&dmamux1 24 0x400 0x1>,
187 <&dmamux1 25 0x400 0x1>,
188 <&dmamux1 26 0x400 0x1>,
189 <&dmamux1 27 0x400 0x1>,
190 <&dmamux1 28 0x400 0x1>;
191 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
195 compatible = "st,stm32-pwm";
201 compatible = "st,stm32h7-timer-trigger";
207 compatible = "st,stm32-timer-counter";
212 timers4: timer@40002000 {
213 #address-cells = <1>;
215 compatible = "st,stm32-timers";
216 reg = <0x40002000 0x400>;
217 clocks = <&rcc TIM4_K>;
219 dmas = <&dmamux1 29 0x400 0x1>,
220 <&dmamux1 30 0x400 0x1>,
221 <&dmamux1 31 0x400 0x1>,
222 <&dmamux1 32 0x400 0x1>;
223 dma-names = "ch1", "ch2", "ch3", "ch4";
227 compatible = "st,stm32-pwm";
233 compatible = "st,stm32h7-timer-trigger";
239 compatible = "st,stm32-timer-counter";
244 timers5: timer@40003000 {
245 #address-cells = <1>;
247 compatible = "st,stm32-timers";
248 reg = <0x40003000 0x400>;
249 clocks = <&rcc TIM5_K>;
251 dmas = <&dmamux1 55 0x400 0x1>,
252 <&dmamux1 56 0x400 0x1>,
253 <&dmamux1 57 0x400 0x1>,
254 <&dmamux1 58 0x400 0x1>,
255 <&dmamux1 59 0x400 0x1>,
256 <&dmamux1 60 0x400 0x1>;
257 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
261 compatible = "st,stm32-pwm";
267 compatible = "st,stm32h7-timer-trigger";
273 compatible = "st,stm32-timer-counter";
278 timers6: timer@40004000 {
279 #address-cells = <1>;
281 compatible = "st,stm32-timers";
282 reg = <0x40004000 0x400>;
283 clocks = <&rcc TIM6_K>;
285 dmas = <&dmamux1 69 0x400 0x1>;
290 compatible = "st,stm32h7-timer-trigger";
296 timers7: timer@40005000 {
297 #address-cells = <1>;
299 compatible = "st,stm32-timers";
300 reg = <0x40005000 0x400>;
301 clocks = <&rcc TIM7_K>;
303 dmas = <&dmamux1 70 0x400 0x1>;
308 compatible = "st,stm32h7-timer-trigger";
314 timers12: timer@40006000 {
315 #address-cells = <1>;
317 compatible = "st,stm32-timers";
318 reg = <0x40006000 0x400>;
319 clocks = <&rcc TIM12_K>;
324 compatible = "st,stm32-pwm";
330 compatible = "st,stm32h7-timer-trigger";
336 timers13: timer@40007000 {
337 #address-cells = <1>;
339 compatible = "st,stm32-timers";
340 reg = <0x40007000 0x400>;
341 clocks = <&rcc TIM13_K>;
346 compatible = "st,stm32-pwm";
352 compatible = "st,stm32h7-timer-trigger";
358 timers14: timer@40008000 {
359 #address-cells = <1>;
361 compatible = "st,stm32-timers";
362 reg = <0x40008000 0x400>;
363 clocks = <&rcc TIM14_K>;
368 compatible = "st,stm32-pwm";
374 compatible = "st,stm32h7-timer-trigger";
380 lptimer1: timer@40009000 {
381 #address-cells = <1>;
383 compatible = "st,stm32-lptimer";
384 reg = <0x40009000 0x400>;
385 clocks = <&rcc LPTIM1_K>;
390 compatible = "st,stm32-pwm-lp";
396 compatible = "st,stm32-lptimer-trigger";
402 compatible = "st,stm32-lptimer-counter";
408 #address-cells = <1>;
410 compatible = "st,stm32h7-spi";
411 reg = <0x4000b000 0x400>;
412 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
413 clocks = <&rcc SPI2_K>;
414 resets = <&rcc SPI2_R>;
415 dmas = <&dmamux1 39 0x400 0x05>,
416 <&dmamux1 40 0x400 0x05>;
417 dma-names = "rx", "tx";
421 i2s2: audio-controller@4000b000 {
422 compatible = "st,stm32h7-i2s";
423 #sound-dai-cells = <0>;
424 reg = <0x4000b000 0x400>;
425 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
426 dmas = <&dmamux1 39 0x400 0x01>,
427 <&dmamux1 40 0x400 0x01>;
428 dma-names = "rx", "tx";
433 #address-cells = <1>;
435 compatible = "st,stm32h7-spi";
436 reg = <0x4000c000 0x400>;
437 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
438 clocks = <&rcc SPI3_K>;
439 resets = <&rcc SPI3_R>;
440 dmas = <&dmamux1 61 0x400 0x05>,
441 <&dmamux1 62 0x400 0x05>;
442 dma-names = "rx", "tx";
446 i2s3: audio-controller@4000c000 {
447 compatible = "st,stm32h7-i2s";
448 #sound-dai-cells = <0>;
449 reg = <0x4000c000 0x400>;
450 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
451 dmas = <&dmamux1 61 0x400 0x01>,
452 <&dmamux1 62 0x400 0x01>;
453 dma-names = "rx", "tx";
457 spdifrx: audio-controller@4000d000 {
458 compatible = "st,stm32h7-spdifrx";
459 #sound-dai-cells = <0>;
460 reg = <0x4000d000 0x400>;
461 clocks = <&rcc SPDIF_K>;
462 clock-names = "kclk";
463 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
464 dmas = <&dmamux1 93 0x400 0x01>,
465 <&dmamux1 94 0x400 0x01>;
466 dma-names = "rx", "rx-ctrl";
470 usart2: serial@4000e000 {
471 compatible = "st,stm32h7-uart";
472 reg = <0x4000e000 0x400>;
473 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
474 clocks = <&rcc USART2_K>;
478 usart3: serial@4000f000 {
479 compatible = "st,stm32h7-uart";
480 reg = <0x4000f000 0x400>;
481 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
482 clocks = <&rcc USART3_K>;
486 uart4: serial@40010000 {
487 compatible = "st,stm32h7-uart";
488 reg = <0x40010000 0x400>;
489 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
490 clocks = <&rcc UART4_K>;
494 uart5: serial@40011000 {
495 compatible = "st,stm32h7-uart";
496 reg = <0x40011000 0x400>;
497 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
498 clocks = <&rcc UART5_K>;
503 compatible = "st,stm32f7-i2c";
504 reg = <0x40012000 0x400>;
505 interrupt-names = "event", "error";
506 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
507 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
508 clocks = <&rcc I2C1_K>;
509 resets = <&rcc I2C1_R>;
510 #address-cells = <1>;
517 compatible = "st,stm32f7-i2c";
518 reg = <0x40013000 0x400>;
519 interrupt-names = "event", "error";
520 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
521 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
522 clocks = <&rcc I2C2_K>;
523 resets = <&rcc I2C2_R>;
524 #address-cells = <1>;
531 compatible = "st,stm32f7-i2c";
532 reg = <0x40014000 0x400>;
533 interrupt-names = "event", "error";
534 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
535 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
536 clocks = <&rcc I2C3_K>;
537 resets = <&rcc I2C3_R>;
538 #address-cells = <1>;
545 compatible = "st,stm32f7-i2c";
546 reg = <0x40015000 0x400>;
547 interrupt-names = "event", "error";
548 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
549 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
550 clocks = <&rcc I2C5_K>;
551 resets = <&rcc I2C5_R>;
552 #address-cells = <1>;
559 compatible = "st,stm32-cec";
560 reg = <0x40016000 0x400>;
561 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
562 clocks = <&rcc CEC_K>, <&clk_lse>;
563 clock-names = "cec", "hdmi-cec";
568 compatible = "st,stm32h7-dac-core";
569 reg = <0x40017000 0x400>;
570 clocks = <&rcc DAC12>;
571 clock-names = "pclk";
572 #address-cells = <1>;
577 compatible = "st,stm32-dac";
578 #io-channels-cells = <1>;
584 compatible = "st,stm32-dac";
585 #io-channels-cells = <1>;
591 uart7: serial@40018000 {
592 compatible = "st,stm32h7-uart";
593 reg = <0x40018000 0x400>;
594 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
595 clocks = <&rcc UART7_K>;
599 uart8: serial@40019000 {
600 compatible = "st,stm32h7-uart";
601 reg = <0x40019000 0x400>;
602 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
603 clocks = <&rcc UART8_K>;
607 timers1: timer@44000000 {
608 #address-cells = <1>;
610 compatible = "st,stm32-timers";
611 reg = <0x44000000 0x400>;
612 clocks = <&rcc TIM1_K>;
614 dmas = <&dmamux1 11 0x400 0x1>,
615 <&dmamux1 12 0x400 0x1>,
616 <&dmamux1 13 0x400 0x1>,
617 <&dmamux1 14 0x400 0x1>,
618 <&dmamux1 15 0x400 0x1>,
619 <&dmamux1 16 0x400 0x1>,
620 <&dmamux1 17 0x400 0x1>;
621 dma-names = "ch1", "ch2", "ch3", "ch4",
626 compatible = "st,stm32-pwm";
632 compatible = "st,stm32h7-timer-trigger";
638 compatible = "st,stm32-timer-counter";
643 timers8: timer@44001000 {
644 #address-cells = <1>;
646 compatible = "st,stm32-timers";
647 reg = <0x44001000 0x400>;
648 clocks = <&rcc TIM8_K>;
650 dmas = <&dmamux1 47 0x400 0x1>,
651 <&dmamux1 48 0x400 0x1>,
652 <&dmamux1 49 0x400 0x1>,
653 <&dmamux1 50 0x400 0x1>,
654 <&dmamux1 51 0x400 0x1>,
655 <&dmamux1 52 0x400 0x1>,
656 <&dmamux1 53 0x400 0x1>;
657 dma-names = "ch1", "ch2", "ch3", "ch4",
662 compatible = "st,stm32-pwm";
668 compatible = "st,stm32h7-timer-trigger";
674 compatible = "st,stm32-timer-counter";
679 usart6: serial@44003000 {
680 compatible = "st,stm32h7-uart";
681 reg = <0x44003000 0x400>;
682 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
683 clocks = <&rcc USART6_K>;
688 #address-cells = <1>;
690 compatible = "st,stm32h7-spi";
691 reg = <0x44004000 0x400>;
692 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
693 clocks = <&rcc SPI1_K>;
694 resets = <&rcc SPI1_R>;
695 dmas = <&dmamux1 37 0x400 0x05>,
696 <&dmamux1 38 0x400 0x05>;
697 dma-names = "rx", "tx";
701 i2s1: audio-controller@44004000 {
702 compatible = "st,stm32h7-i2s";
703 #sound-dai-cells = <0>;
704 reg = <0x44004000 0x400>;
705 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
706 dmas = <&dmamux1 37 0x400 0x01>,
707 <&dmamux1 38 0x400 0x01>;
708 dma-names = "rx", "tx";
713 #address-cells = <1>;
715 compatible = "st,stm32h7-spi";
716 reg = <0x44005000 0x400>;
717 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
718 clocks = <&rcc SPI4_K>;
719 resets = <&rcc SPI4_R>;
720 dmas = <&dmamux1 83 0x400 0x05>,
721 <&dmamux1 84 0x400 0x05>;
722 dma-names = "rx", "tx";
726 timers15: timer@44006000 {
727 #address-cells = <1>;
729 compatible = "st,stm32-timers";
730 reg = <0x44006000 0x400>;
731 clocks = <&rcc TIM15_K>;
733 dmas = <&dmamux1 105 0x400 0x1>,
734 <&dmamux1 106 0x400 0x1>,
735 <&dmamux1 107 0x400 0x1>,
736 <&dmamux1 108 0x400 0x1>;
737 dma-names = "ch1", "up", "trig", "com";
741 compatible = "st,stm32-pwm";
747 compatible = "st,stm32h7-timer-trigger";
753 timers16: timer@44007000 {
754 #address-cells = <1>;
756 compatible = "st,stm32-timers";
757 reg = <0x44007000 0x400>;
758 clocks = <&rcc TIM16_K>;
760 dmas = <&dmamux1 109 0x400 0x1>,
761 <&dmamux1 110 0x400 0x1>;
762 dma-names = "ch1", "up";
766 compatible = "st,stm32-pwm";
771 compatible = "st,stm32h7-timer-trigger";
777 timers17: timer@44008000 {
778 #address-cells = <1>;
780 compatible = "st,stm32-timers";
781 reg = <0x44008000 0x400>;
782 clocks = <&rcc TIM17_K>;
784 dmas = <&dmamux1 111 0x400 0x1>,
785 <&dmamux1 112 0x400 0x1>;
786 dma-names = "ch1", "up";
790 compatible = "st,stm32-pwm";
796 compatible = "st,stm32h7-timer-trigger";
803 #address-cells = <1>;
805 compatible = "st,stm32h7-spi";
806 reg = <0x44009000 0x400>;
807 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
808 clocks = <&rcc SPI5_K>;
809 resets = <&rcc SPI5_R>;
810 dmas = <&dmamux1 85 0x400 0x05>,
811 <&dmamux1 86 0x400 0x05>;
812 dma-names = "rx", "tx";
817 compatible = "st,stm32h7-sai";
818 #address-cells = <1>;
820 ranges = <0 0x4400a000 0x400>;
821 reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
822 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
823 resets = <&rcc SAI1_R>;
826 sai1a: audio-controller@4400a004 {
827 #sound-dai-cells = <0>;
829 compatible = "st,stm32-sai-sub-a";
831 clocks = <&rcc SAI1_K>;
832 clock-names = "sai_ck";
833 dmas = <&dmamux1 87 0x400 0x01>;
837 sai1b: audio-controller@4400a024 {
838 #sound-dai-cells = <0>;
839 compatible = "st,stm32-sai-sub-b";
841 clocks = <&rcc SAI1_K>;
842 clock-names = "sai_ck";
843 dmas = <&dmamux1 88 0x400 0x01>;
849 compatible = "st,stm32h7-sai";
850 #address-cells = <1>;
852 ranges = <0 0x4400b000 0x400>;
853 reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
854 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
855 resets = <&rcc SAI2_R>;
858 sai2a: audio-controller@4400b004 {
859 #sound-dai-cells = <0>;
860 compatible = "st,stm32-sai-sub-a";
862 clocks = <&rcc SAI2_K>;
863 clock-names = "sai_ck";
864 dmas = <&dmamux1 89 0x400 0x01>;
868 sai2b: audio-controller@4400b024 {
869 #sound-dai-cells = <0>;
870 compatible = "st,stm32-sai-sub-b";
872 clocks = <&rcc SAI2_K>;
873 clock-names = "sai_ck";
874 dmas = <&dmamux1 90 0x400 0x01>;
880 compatible = "st,stm32h7-sai";
881 #address-cells = <1>;
883 ranges = <0 0x4400c000 0x400>;
884 reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
885 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
886 resets = <&rcc SAI3_R>;
889 sai3a: audio-controller@4400c004 {
890 #sound-dai-cells = <0>;
891 compatible = "st,stm32-sai-sub-a";
893 clocks = <&rcc SAI3_K>;
894 clock-names = "sai_ck";
895 dmas = <&dmamux1 113 0x400 0x01>;
899 sai3b: audio-controller@4400c024 {
900 #sound-dai-cells = <0>;
901 compatible = "st,stm32-sai-sub-b";
903 clocks = <&rcc SAI3_K>;
904 clock-names = "sai_ck";
905 dmas = <&dmamux1 114 0x400 0x01>;
910 dfsdm: dfsdm@4400d000 {
911 compatible = "st,stm32mp1-dfsdm";
912 reg = <0x4400d000 0x800>;
913 clocks = <&rcc DFSDM_K>;
914 clock-names = "dfsdm";
915 #address-cells = <1>;
920 compatible = "st,stm32-dfsdm-adc";
921 #io-channel-cells = <1>;
923 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
924 dmas = <&dmamux1 101 0x400 0x01>;
930 compatible = "st,stm32-dfsdm-adc";
931 #io-channel-cells = <1>;
933 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
934 dmas = <&dmamux1 102 0x400 0x01>;
940 compatible = "st,stm32-dfsdm-adc";
941 #io-channel-cells = <1>;
943 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
944 dmas = <&dmamux1 103 0x400 0x01>;
950 compatible = "st,stm32-dfsdm-adc";
951 #io-channel-cells = <1>;
953 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
954 dmas = <&dmamux1 104 0x400 0x01>;
960 compatible = "st,stm32-dfsdm-adc";
961 #io-channel-cells = <1>;
963 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
964 dmas = <&dmamux1 91 0x400 0x01>;
970 compatible = "st,stm32-dfsdm-adc";
971 #io-channel-cells = <1>;
973 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
974 dmas = <&dmamux1 92 0x400 0x01>;
980 dma1: dma-controller@48000000 {
981 compatible = "st,stm32-dma";
982 reg = <0x48000000 0x400>;
983 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
984 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
985 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
986 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
987 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
988 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
989 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
990 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
991 clocks = <&rcc DMA1>;
992 resets = <&rcc DMA1_R>;
998 dma2: dma-controller@48001000 {
999 compatible = "st,stm32-dma";
1000 reg = <0x48001000 0x400>;
1001 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
1002 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
1003 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
1004 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
1005 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
1006 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
1007 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1008 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1009 clocks = <&rcc DMA2>;
1010 resets = <&rcc DMA2_R>;
1016 dmamux1: dma-router@48002000 {
1017 compatible = "st,stm32h7-dmamux";
1018 reg = <0x48002000 0x1c>;
1020 dma-requests = <128>;
1021 dma-masters = <&dma1 &dma2>;
1022 dma-channels = <16>;
1023 clocks = <&rcc DMAMUX>;
1024 resets = <&rcc DMAMUX_R>;
1028 compatible = "st,stm32mp1-adc-core";
1029 reg = <0x48003000 0x400>;
1030 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
1031 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1032 clocks = <&rcc ADC12>, <&rcc ADC12_K>;
1033 clock-names = "bus", "adc";
1034 interrupt-controller;
1035 st,syscfg = <&syscfg>;
1036 #interrupt-cells = <1>;
1037 #address-cells = <1>;
1039 status = "disabled";
1042 compatible = "st,stm32mp1-adc";
1043 #io-channel-cells = <1>;
1045 interrupt-parent = <&adc>;
1047 dmas = <&dmamux1 9 0x400 0x01>;
1049 status = "disabled";
1053 compatible = "st,stm32mp1-adc";
1054 #io-channel-cells = <1>;
1056 interrupt-parent = <&adc>;
1058 dmas = <&dmamux1 10 0x400 0x01>;
1060 status = "disabled";
1064 sdmmc3: sdmmc@48004000 {
1065 compatible = "arm,pl18x", "arm,primecell";
1066 arm,primecell-periphid = <0x10153180>;
1067 reg = <0x48004000 0x400>;
1068 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
1069 interrupt-names = "cmd_irq";
1070 clocks = <&rcc SDMMC3_K>;
1071 clock-names = "apb_pclk";
1072 resets = <&rcc SDMMC3_R>;
1075 max-frequency = <120000000>;
1076 status = "disabled";
1079 usbotg_hs: usb-otg@49000000 {
1080 compatible = "st,stm32mp15-hsotg", "snps,dwc2";
1081 reg = <0x49000000 0x10000>;
1082 clocks = <&rcc USBO_K>;
1083 clock-names = "otg";
1084 resets = <&rcc USBO_R>;
1085 reset-names = "dwc2";
1086 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1087 g-rx-fifo-size = <256>;
1088 g-np-tx-fifo-size = <32>;
1089 g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
1091 usb33d-supply = <&usb33>;
1092 status = "disabled";
1095 hwspinlock: hwspinlock@4c000000 {
1096 compatible = "st,stm32-hwspinlock";
1097 #hwlock-cells = <1>;
1098 reg = <0x4c000000 0x400>;
1099 clocks = <&rcc HSEM>;
1100 clock-names = "hwspinlock";
1103 ipcc: mailbox@4c001000 {
1104 compatible = "st,stm32mp1-ipcc";
1106 reg = <0x4c001000 0x400>;
1108 interrupts-extended =
1109 <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1110 <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1112 interrupt-names = "rx", "tx", "wakeup";
1113 clocks = <&rcc IPCC>;
1115 status = "disabled";
1118 dcmi: dcmi@4c006000 {
1119 compatible = "st,stm32-dcmi";
1120 reg = <0x4c006000 0x400>;
1121 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1122 resets = <&rcc CAMITF_R>;
1123 clocks = <&rcc DCMI>;
1124 clock-names = "mclk";
1125 dmas = <&dmamux1 75 0x400 0x0d>;
1127 status = "disabled";
1131 compatible = "st,stm32mp1-rcc", "syscon";
1132 reg = <0x50000000 0x1000>;
1137 pwr_regulators: pwr@50001000 {
1138 compatible = "st,stm32mp1,pwr-reg";
1139 reg = <0x50001000 0x10>;
1142 regulator-name = "reg11";
1143 regulator-min-microvolt = <1100000>;
1144 regulator-max-microvolt = <1100000>;
1148 regulator-name = "reg18";
1149 regulator-min-microvolt = <1800000>;
1150 regulator-max-microvolt = <1800000>;
1154 regulator-name = "usb33";
1155 regulator-min-microvolt = <3300000>;
1156 regulator-max-microvolt = <3300000>;
1160 exti: interrupt-controller@5000d000 {
1161 compatible = "st,stm32mp1-exti", "syscon";
1162 interrupt-controller;
1163 #interrupt-cells = <2>;
1164 reg = <0x5000d000 0x400>;
1167 syscfg: syscon@50020000 {
1168 compatible = "st,stm32mp157-syscfg", "syscon";
1169 reg = <0x50020000 0x400>;
1170 clocks = <&rcc SYSCFG>;
1173 lptimer2: timer@50021000 {
1174 #address-cells = <1>;
1176 compatible = "st,stm32-lptimer";
1177 reg = <0x50021000 0x400>;
1178 clocks = <&rcc LPTIM2_K>;
1179 clock-names = "mux";
1180 status = "disabled";
1183 compatible = "st,stm32-pwm-lp";
1185 status = "disabled";
1189 compatible = "st,stm32-lptimer-trigger";
1191 status = "disabled";
1195 compatible = "st,stm32-lptimer-counter";
1196 status = "disabled";
1200 lptimer3: timer@50022000 {
1201 #address-cells = <1>;
1203 compatible = "st,stm32-lptimer";
1204 reg = <0x50022000 0x400>;
1205 clocks = <&rcc LPTIM3_K>;
1206 clock-names = "mux";
1207 status = "disabled";
1210 compatible = "st,stm32-pwm-lp";
1212 status = "disabled";
1216 compatible = "st,stm32-lptimer-trigger";
1218 status = "disabled";
1222 lptimer4: timer@50023000 {
1223 compatible = "st,stm32-lptimer";
1224 reg = <0x50023000 0x400>;
1225 clocks = <&rcc LPTIM4_K>;
1226 clock-names = "mux";
1227 status = "disabled";
1230 compatible = "st,stm32-pwm-lp";
1232 status = "disabled";
1236 lptimer5: timer@50024000 {
1237 compatible = "st,stm32-lptimer";
1238 reg = <0x50024000 0x400>;
1239 clocks = <&rcc LPTIM5_K>;
1240 clock-names = "mux";
1241 status = "disabled";
1244 compatible = "st,stm32-pwm-lp";
1246 status = "disabled";
1250 vrefbuf: vrefbuf@50025000 {
1251 compatible = "st,stm32-vrefbuf";
1252 reg = <0x50025000 0x8>;
1253 regulator-min-microvolt = <1500000>;
1254 regulator-max-microvolt = <2500000>;
1255 clocks = <&rcc VREF>;
1256 status = "disabled";
1259 sai4: sai@50027000 {
1260 compatible = "st,stm32h7-sai";
1261 #address-cells = <1>;
1263 ranges = <0 0x50027000 0x400>;
1264 reg = <0x50027000 0x4>, <0x500273f0 0x10>;
1265 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
1266 resets = <&rcc SAI4_R>;
1267 status = "disabled";
1269 sai4a: audio-controller@50027004 {
1270 #sound-dai-cells = <0>;
1271 compatible = "st,stm32-sai-sub-a";
1273 clocks = <&rcc SAI4_K>;
1274 clock-names = "sai_ck";
1275 dmas = <&dmamux1 99 0x400 0x01>;
1276 status = "disabled";
1279 sai4b: audio-controller@50027024 {
1280 #sound-dai-cells = <0>;
1281 compatible = "st,stm32-sai-sub-b";
1283 clocks = <&rcc SAI4_K>;
1284 clock-names = "sai_ck";
1285 dmas = <&dmamux1 100 0x400 0x01>;
1286 status = "disabled";
1290 dts: thermal@50028000 {
1291 compatible = "st,stm32-thermal";
1292 reg = <0x50028000 0x100>;
1293 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1294 clocks = <&rcc TMPSENS>;
1295 clock-names = "pclk";
1296 #thermal-sensor-cells = <0>;
1297 status = "disabled";
1300 hash1: hash@54002000 {
1301 compatible = "st,stm32f756-hash";
1302 reg = <0x54002000 0x400>;
1303 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1304 clocks = <&rcc HASH1>;
1305 resets = <&rcc HASH1_R>;
1306 dmas = <&mdma1 31 0x10 0x1000A02 0x0 0x0>;
1309 status = "disabled";
1312 rng1: rng@54003000 {
1313 compatible = "st,stm32-rng";
1314 reg = <0x54003000 0x400>;
1315 clocks = <&rcc RNG1_K>;
1316 resets = <&rcc RNG1_R>;
1317 status = "disabled";
1320 mdma1: dma-controller@58000000 {
1321 compatible = "st,stm32h7-mdma";
1322 reg = <0x58000000 0x1000>;
1323 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1324 clocks = <&rcc MDMA>;
1325 resets = <&rcc MDMA_R>;
1327 dma-channels = <32>;
1328 dma-requests = <48>;
1331 fmc: nand-controller@58002000 {
1332 compatible = "st,stm32mp15-fmc2";
1333 reg = <0x58002000 0x1000>,
1334 <0x80000000 0x1000>,
1335 <0x88010000 0x1000>,
1336 <0x88020000 0x1000>,
1337 <0x81000000 0x1000>,
1338 <0x89010000 0x1000>,
1339 <0x89020000 0x1000>;
1340 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1341 dmas = <&mdma1 20 0x10 0x12000a02 0x0 0x0>,
1342 <&mdma1 20 0x10 0x12000a08 0x0 0x0>,
1343 <&mdma1 21 0x10 0x12000a0a 0x0 0x0>;
1344 dma-names = "tx", "rx", "ecc";
1345 clocks = <&rcc FMC_K>;
1346 resets = <&rcc FMC_R>;
1347 status = "disabled";
1350 qspi: spi@58003000 {
1351 compatible = "st,stm32f469-qspi";
1352 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
1353 reg-names = "qspi", "qspi_mm";
1354 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
1355 dmas = <&mdma1 22 0x10 0x100002 0x0 0x0>,
1356 <&mdma1 22 0x10 0x100008 0x0 0x0>;
1357 dma-names = "tx", "rx";
1358 clocks = <&rcc QSPI_K>;
1359 resets = <&rcc QSPI_R>;
1360 status = "disabled";
1363 sdmmc1: sdmmc@58005000 {
1364 compatible = "arm,pl18x", "arm,primecell";
1365 arm,primecell-periphid = <0x10153180>;
1366 reg = <0x58005000 0x1000>;
1367 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1368 interrupt-names = "cmd_irq";
1369 clocks = <&rcc SDMMC1_K>;
1370 clock-names = "apb_pclk";
1371 resets = <&rcc SDMMC1_R>;
1374 max-frequency = <120000000>;
1375 status = "disabled";
1378 sdmmc2: sdmmc@58007000 {
1379 compatible = "arm,pl18x", "arm,primecell";
1380 arm,primecell-periphid = <0x10153180>;
1381 reg = <0x58007000 0x1000>;
1382 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
1383 interrupt-names = "cmd_irq";
1384 clocks = <&rcc SDMMC2_K>;
1385 clock-names = "apb_pclk";
1386 resets = <&rcc SDMMC2_R>;
1389 max-frequency = <120000000>;
1390 status = "disabled";
1393 crc1: crc@58009000 {
1394 compatible = "st,stm32f7-crc";
1395 reg = <0x58009000 0x400>;
1396 clocks = <&rcc CRC1>;
1397 status = "disabled";
1400 stmmac_axi_config_0: stmmac-axi-config {
1401 snps,wr_osr_lmt = <0x7>;
1402 snps,rd_osr_lmt = <0x7>;
1403 snps,blen = <0 0 0 0 16 8 4>;
1406 ethernet0: ethernet@5800a000 {
1407 compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
1408 reg = <0x5800a000 0x2000>;
1409 reg-names = "stmmaceth";
1410 interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1411 interrupt-names = "macirq";
1412 clock-names = "stmmaceth",
1418 clocks = <&rcc ETHMAC>,
1424 st,syscon = <&syscfg 0x4>;
1427 snps,en-tx-lpi-clockgating;
1428 snps,axi-config = <&stmmac_axi_config_0>;
1430 status = "disabled";
1433 usbh_ohci: usbh-ohci@5800c000 {
1434 compatible = "generic-ohci";
1435 reg = <0x5800c000 0x1000>;
1436 clocks = <&rcc USBH>;
1437 resets = <&rcc USBH_R>;
1438 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1439 status = "disabled";
1442 usbh_ehci: usbh-ehci@5800d000 {
1443 compatible = "generic-ehci";
1444 reg = <0x5800d000 0x1000>;
1445 clocks = <&rcc USBH>;
1446 resets = <&rcc USBH_R>;
1447 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1448 companion = <&usbh_ohci>;
1449 status = "disabled";
1452 ltdc: display-controller@5a001000 {
1453 compatible = "st,stm32-ltdc";
1454 reg = <0x5a001000 0x400>;
1455 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1456 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1457 clocks = <&rcc LTDC_PX>;
1458 clock-names = "lcd";
1459 resets = <&rcc LTDC_R>;
1460 status = "disabled";
1463 iwdg2: watchdog@5a002000 {
1464 compatible = "st,stm32mp1-iwdg";
1465 reg = <0x5a002000 0x400>;
1466 clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
1467 clock-names = "pclk", "lsi";
1468 status = "disabled";
1471 usbphyc: usbphyc@5a006000 {
1472 #address-cells = <1>;
1474 compatible = "st,stm32mp1-usbphyc";
1475 reg = <0x5a006000 0x1000>;
1476 clocks = <&rcc USBPHY_K>;
1477 resets = <&rcc USBPHY_R>;
1478 vdda1v1-supply = <®11>;
1479 vdda1v8-supply = <®18>;
1480 status = "disabled";
1482 usbphyc_port0: usb-phy@0 {
1487 usbphyc_port1: usb-phy@1 {
1493 usart1: serial@5c000000 {
1494 compatible = "st,stm32h7-uart";
1495 reg = <0x5c000000 0x400>;
1496 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1497 clocks = <&rcc USART1_K>;
1498 status = "disabled";
1501 spi6: spi@5c001000 {
1502 #address-cells = <1>;
1504 compatible = "st,stm32h7-spi";
1505 reg = <0x5c001000 0x400>;
1506 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1507 clocks = <&rcc SPI6_K>;
1508 resets = <&rcc SPI6_R>;
1509 dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
1510 <&mdma1 35 0x0 0x40002 0x0 0x0>;
1511 dma-names = "rx", "tx";
1512 status = "disabled";
1515 i2c4: i2c@5c002000 {
1516 compatible = "st,stm32f7-i2c";
1517 reg = <0x5c002000 0x400>;
1518 interrupt-names = "event", "error";
1519 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1520 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1521 clocks = <&rcc I2C4_K>;
1522 resets = <&rcc I2C4_R>;
1523 #address-cells = <1>;
1526 status = "disabled";
1530 compatible = "st,stm32mp1-rtc";
1531 reg = <0x5c004000 0x400>;
1532 clocks = <&rcc RTCAPB>, <&rcc RTC>;
1533 clock-names = "pclk", "rtc_ck";
1534 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1535 status = "disabled";
1538 bsec: efuse@5c005000 {
1539 compatible = "st,stm32mp15-bsec";
1540 reg = <0x5c005000 0x400>;
1541 #address-cells = <1>;
1543 part_number_otp: part_number_otp@4 {
1554 i2c6: i2c@5c009000 {
1555 compatible = "st,stm32f7-i2c";
1556 reg = <0x5c009000 0x400>;
1557 interrupt-names = "event", "error";
1558 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1559 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1560 clocks = <&rcc I2C6_K>;
1561 resets = <&rcc I2C6_R>;
1562 #address-cells = <1>;
1565 status = "disabled";
1569 * Break node order to solve dependency probe issue between
1572 pinctrl: pin-controller@50002000 {
1573 #address-cells = <1>;
1575 compatible = "st,stm32mp157-pinctrl";
1576 ranges = <0 0x50002000 0xa400>;
1577 interrupt-parent = <&exti>;
1578 st,syscfg = <&exti 0x60 0xff>;
1579 hwlocks = <&hwspinlock 0>;
1582 gpioa: gpio@50002000 {
1585 interrupt-controller;
1586 #interrupt-cells = <2>;
1588 clocks = <&rcc GPIOA>;
1589 st,bank-name = "GPIOA";
1590 status = "disabled";
1593 gpiob: gpio@50003000 {
1596 interrupt-controller;
1597 #interrupt-cells = <2>;
1598 reg = <0x1000 0x400>;
1599 clocks = <&rcc GPIOB>;
1600 st,bank-name = "GPIOB";
1601 status = "disabled";
1604 gpioc: gpio@50004000 {
1607 interrupt-controller;
1608 #interrupt-cells = <2>;
1609 reg = <0x2000 0x400>;
1610 clocks = <&rcc GPIOC>;
1611 st,bank-name = "GPIOC";
1612 status = "disabled";
1615 gpiod: gpio@50005000 {
1618 interrupt-controller;
1619 #interrupt-cells = <2>;
1620 reg = <0x3000 0x400>;
1621 clocks = <&rcc GPIOD>;
1622 st,bank-name = "GPIOD";
1623 status = "disabled";
1626 gpioe: gpio@50006000 {
1629 interrupt-controller;
1630 #interrupt-cells = <2>;
1631 reg = <0x4000 0x400>;
1632 clocks = <&rcc GPIOE>;
1633 st,bank-name = "GPIOE";
1634 status = "disabled";
1637 gpiof: gpio@50007000 {
1640 interrupt-controller;
1641 #interrupt-cells = <2>;
1642 reg = <0x5000 0x400>;
1643 clocks = <&rcc GPIOF>;
1644 st,bank-name = "GPIOF";
1645 status = "disabled";
1648 gpiog: gpio@50008000 {
1651 interrupt-controller;
1652 #interrupt-cells = <2>;
1653 reg = <0x6000 0x400>;
1654 clocks = <&rcc GPIOG>;
1655 st,bank-name = "GPIOG";
1656 status = "disabled";
1659 gpioh: gpio@50009000 {
1662 interrupt-controller;
1663 #interrupt-cells = <2>;
1664 reg = <0x7000 0x400>;
1665 clocks = <&rcc GPIOH>;
1666 st,bank-name = "GPIOH";
1667 status = "disabled";
1670 gpioi: gpio@5000a000 {
1673 interrupt-controller;
1674 #interrupt-cells = <2>;
1675 reg = <0x8000 0x400>;
1676 clocks = <&rcc GPIOI>;
1677 st,bank-name = "GPIOI";
1678 status = "disabled";
1681 gpioj: gpio@5000b000 {
1684 interrupt-controller;
1685 #interrupt-cells = <2>;
1686 reg = <0x9000 0x400>;
1687 clocks = <&rcc GPIOJ>;
1688 st,bank-name = "GPIOJ";
1689 status = "disabled";
1692 gpiok: gpio@5000c000 {
1695 interrupt-controller;
1696 #interrupt-cells = <2>;
1697 reg = <0xa000 0x400>;
1698 clocks = <&rcc GPIOK>;
1699 st,bank-name = "GPIOK";
1700 status = "disabled";
1704 pinctrl_z: pin-controller-z@54004000 {
1705 #address-cells = <1>;
1707 compatible = "st,stm32mp157-z-pinctrl";
1708 ranges = <0 0x54004000 0x400>;
1710 interrupt-parent = <&exti>;
1711 st,syscfg = <&exti 0x60 0xff>;
1712 hwlocks = <&hwspinlock 0>;
1714 gpioz: gpio@54004000 {
1717 interrupt-controller;
1718 #interrupt-cells = <2>;
1720 clocks = <&rcc GPIOZ>;
1721 st,bank-name = "GPIOZ";
1722 st,bank-ioport = <11>;
1723 status = "disabled";
1729 compatible = "st,mlahb", "simple-bus";
1730 #address-cells = <1>;
1733 dma-ranges = <0x00000000 0x38000000 0x10000>,
1734 <0x10000000 0x10000000 0x60000>,
1735 <0x30000000 0x30000000 0x60000>;
1737 m4_rproc: m4@10000000 {
1738 compatible = "st,stm32mp1-m4";
1739 reg = <0x10000000 0x40000>,
1740 <0x30000000 0x40000>,
1741 <0x38000000 0x10000>;
1742 resets = <&rcc MCU_R>;
1743 st,syscfg-holdboot = <&rcc 0x10C 0x1>;
1744 st,syscfg-tz = <&rcc 0x000 0x1>;
1745 status = "disabled";