arch/arm/dts/stm32mp151.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /*
   3  * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
   4  * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
   5  */
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/stm32mp1-clks.h>
   8 #include <dt-bindings/reset/stm32mp1-resets.h>
   9
  10 / {
  11         #address-cells = <1>;
  12         #size-cells = <1>;
  13
  14         cpus {
  15                 #address-cells = <1>;
  16                 #size-cells = <0>;
  17
  18                 cpu0: cpu@0 {
  19                         compatible = "arm,cortex-a7";
  20                         clock-frequency = <650000000>;
  21                         device_type = "cpu";
  22                         reg = <0>;
  23                         operating-points-v2 = <&cpu0_opp_table>;
  24                         nvmem-cells = <&part_number_otp>;
  25                         nvmem-cell-names = "part_number";
  26                 };
  27         };
  28
  29         cpu0_opp_table: cpu0-opp-table {
  30                 compatible = "operating-points-v2";
  31                 opp-shared;
  32                 opp-650000000 {
  33                         opp-hz = /bits/ 64 <650000000>;
  34                         opp-microvolt = <1200000>;
  35                         opp-supported-hw = <0x1>;
  36                 };
  37                 opp-800000000 {
  38                         opp-hz = /bits/ 64 <800000000>;
  39                         opp-microvolt = <1350000>;
  40                         opp-supported-hw = <0x2>;
  41                 };
  42         };
  43
  44         arm-pmu {
  45                 compatible = "arm,cortex-a7-pmu";
  46                 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
  47                 interrupt-affinity = <&cpu0>;
  48                 interrupt-parent = <&intc>;
  49         };
  50
  51         psci {
  52                 compatible = "arm,psci-1.0";
  53                 method = "smc";
  54         };
  55
  56         intc: interrupt-controller@a0021000 {
  57                 compatible = "arm,cortex-a7-gic";
  58                 #interrupt-cells = <3>;
  59                 interrupt-controller;
  60                 reg = <0xa0021000 0x1000>,
  61                       <0xa0022000 0x2000>;
  62         };
  63
  64         timer {
  65                 compatible = "arm,armv7-timer";
  66                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  67                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  68                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  69                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  70                 interrupt-parent = <&intc>;
  71         };
  72
  73         clocks {
  74                 clk_hse: clk-hse {
  75                         #clock-cells = <0>;
  76                         compatible = "fixed-clock";
  77                         clock-frequency = <24000000>;
  78                 };
  79
  80                 clk_hsi: clk-hsi {
  81                         #clock-cells = <0>;
  82                         compatible = "fixed-clock";
  83                         clock-frequency = <64000000>;
  84                 };
  85
  86                 clk_lse: clk-lse {
  87                         #clock-cells = <0>;
  88                         compatible = "fixed-clock";
  89                         clock-frequency = <32768>;
  90                 };
  91
  92                 clk_lsi: clk-lsi {
  93                         #clock-cells = <0>;
  94                         compatible = "fixed-clock";
  95                         clock-frequency = <32000>;
  96                 };
  97
  98                 clk_csi: clk-csi {
  99                         #clock-cells = <0>;
 100                         compatible = "fixed-clock";
 101                         clock-frequency = <4000000>;
 102                 };
 103         };
 104
 105         thermal-zones {
 106                 cpu_thermal: cpu-thermal {
 107                         polling-delay-passive = <0>;
 108                         polling-delay = <0>;
 109                         thermal-sensors = <&dts>;
 110
 111                         trips {
 112                                 cpu_alert1: cpu-alert1 {
 113                                         temperature = <85000>;
 114                                         hysteresis = <0>;
 115                                         type = "passive";
 116                                 };
 117
 118                                 cpu-crit {
 119                                         temperature = <120000>;
 120                                         hysteresis = <0>;
 121                                         type = "critical";
 122                                 };
 123                         };
 124
 125                         cooling-maps {
 126                         };
 127                 };
 128         };
 129
 130         booster: regulator-booster {
 131                 compatible = "st,stm32mp1-booster";
 132                 st,syscfg = <&syscfg>;
 133                 status = "disabled";
 134         };
 135
 136         soc {
 137                 compatible = "simple-bus";
 138                 #address-cells = <1>;
 139                 #size-cells = <1>;
 140                 interrupt-parent = <&intc>;
 141                 ranges;
 142
 143                 timers2: timer@40000000 {
 144                         #address-cells = <1>;
 145                         #size-cells = <0>;
 146                         compatible = "st,stm32-timers";
 147                         reg = <0x40000000 0x400>;
 148                         clocks = <&rcc TIM2_K>;
 149                         clock-names = "int";
 150                         dmas = <&dmamux1 18 0x400 0x1>,
 151                                <&dmamux1 19 0x400 0x1>,
 152                                <&dmamux1 20 0x400 0x1>,
 153                                <&dmamux1 21 0x400 0x1>,
 154                                <&dmamux1 22 0x400 0x1>;
 155                         dma-names = "ch1", "ch2", "ch3", "ch4", "up";
 156                         status = "disabled";
 157
 158                         pwm {
 159                                 compatible = "st,stm32-pwm";
 160                                 #pwm-cells = <3>;
 161                                 status = "disabled";
 162                         };
 163
 164                         timer@1 {
 165                                 compatible = "st,stm32h7-timer-trigger";
 166                                 reg = <1>;
 167                                 status = "disabled";
 168                         };
 169
 170                         counter {
 171                                 compatible = "st,stm32-timer-counter";
 172                                 status = "disabled";
 173                         };
 174                 };
 175
 176                 timers3: timer@40001000 {
 177                         #address-cells = <1>;
 178                         #size-cells = <0>;
 179                         compatible = "st,stm32-timers";
 180                         reg = <0x40001000 0x400>;
 181                         clocks = <&rcc TIM3_K>;
 182                         clock-names = "int";
 183                         dmas = <&dmamux1 23 0x400 0x1>,
 184                                <&dmamux1 24 0x400 0x1>,
 185                                <&dmamux1 25 0x400 0x1>,
 186                                <&dmamux1 26 0x400 0x1>,
 187                                <&dmamux1 27 0x400 0x1>,
 188                                <&dmamux1 28 0x400 0x1>;
 189                         dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
 190                         status = "disabled";
 191
 192                         pwm {
 193                                 compatible = "st,stm32-pwm";
 194                                 #pwm-cells = <3>;
 195                                 status = "disabled";
 196                         };
 197
 198                         timer@2 {
 199                                 compatible = "st,stm32h7-timer-trigger";
 200                                 reg = <2>;
 201                                 status = "disabled";
 202                         };
 203
 204                         counter {
 205                                 compatible = "st,stm32-timer-counter";
 206                                 status = "disabled";
 207                         };
 208                 };
 209
 210                 timers4: timer@40002000 {
 211                         #address-cells = <1>;
 212                         #size-cells = <0>;
 213                         compatible = "st,stm32-timers";
 214                         reg = <0x40002000 0x400>;
 215                         clocks = <&rcc TIM4_K>;
 216                         clock-names = "int";
 217                         dmas = <&dmamux1 29 0x400 0x1>,
 218                                <&dmamux1 30 0x400 0x1>,
 219                                <&dmamux1 31 0x400 0x1>,
 220                                <&dmamux1 32 0x400 0x1>;
 221                         dma-names = "ch1", "ch2", "ch3", "ch4";
 222                         status = "disabled";
 223
 224                         pwm {
 225                                 compatible = "st,stm32-pwm";
 226                                 #pwm-cells = <3>;
 227                                 status = "disabled";
 228                         };
 229
 230                         timer@3 {
 231                                 compatible = "st,stm32h7-timer-trigger";
 232                                 reg = <3>;
 233                                 status = "disabled";
 234                         };
 235
 236                         counter {
 237                                 compatible = "st,stm32-timer-counter";
 238                                 status = "disabled";
 239                         };
 240                 };
 241
 242                 timers5: timer@40003000 {
 243                         #address-cells = <1>;
 244                         #size-cells = <0>;
 245                         compatible = "st,stm32-timers";
 246                         reg = <0x40003000 0x400>;
 247                         clocks = <&rcc TIM5_K>;
 248                         clock-names = "int";
 249                         dmas = <&dmamux1 55 0x400 0x1>,
 250                                <&dmamux1 56 0x400 0x1>,
 251                                <&dmamux1 57 0x400 0x1>,
 252                                <&dmamux1 58 0x400 0x1>,
 253                                <&dmamux1 59 0x400 0x1>,
 254                                <&dmamux1 60 0x400 0x1>;
 255                         dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
 256                         status = "disabled";
 257
 258                         pwm {
 259                                 compatible = "st,stm32-pwm";
 260                                 #pwm-cells = <3>;
 261                                 status = "disabled";
 262                         };
 263
 264                         timer@4 {
 265                                 compatible = "st,stm32h7-timer-trigger";
 266                                 reg = <4>;
 267                                 status = "disabled";
 268                         };
 269
 270                         counter {
 271                                 compatible = "st,stm32-timer-counter";
 272                                 status = "disabled";
 273                         };
 274                 };
 275
 276                 timers6: timer@40004000 {
 277                         #address-cells = <1>;
 278                         #size-cells = <0>;
 279                         compatible = "st,stm32-timers";
 280                         reg = <0x40004000 0x400>;
 281                         clocks = <&rcc TIM6_K>;
 282                         clock-names = "int";
 283                         dmas = <&dmamux1 69 0x400 0x1>;
 284                         dma-names = "up";
 285                         status = "disabled";
 286
 287                         timer@5 {
 288                                 compatible = "st,stm32h7-timer-trigger";
 289                                 reg = <5>;
 290                                 status = "disabled";
 291                         };
 292                 };
 293
 294                 timers7: timer@40005000 {
 295                         #address-cells = <1>;
 296                         #size-cells = <0>;
 297                         compatible = "st,stm32-timers";
 298                         reg = <0x40005000 0x400>;
 299                         clocks = <&rcc TIM7_K>;
 300                         clock-names = "int";
 301                         dmas = <&dmamux1 70 0x400 0x1>;
 302                         dma-names = "up";
 303                         status = "disabled";
 304
 305                         timer@6 {
 306                                 compatible = "st,stm32h7-timer-trigger";
 307                                 reg = <6>;
 308                                 status = "disabled";
 309                         };
 310                 };
 311
 312                 timers12: timer@40006000 {
 313                         #address-cells = <1>;
 314                         #size-cells = <0>;
 315                         compatible = "st,stm32-timers";
 316                         reg = <0x40006000 0x400>;
 317                         clocks = <&rcc TIM12_K>;
 318                         clock-names = "int";
 319                         status = "disabled";
 320
 321                         pwm {
 322                                 compatible = "st,stm32-pwm";
 323                                 #pwm-cells = <3>;
 324                                 status = "disabled";
 325                         };
 326
 327                         timer@11 {
 328                                 compatible = "st,stm32h7-timer-trigger";
 329                                 reg = <11>;
 330                                 status = "disabled";
 331                         };
 332                 };
 333
 334                 timers13: timer@40007000 {
 335                         #address-cells = <1>;
 336                         #size-cells = <0>;
 337                         compatible = "st,stm32-timers";
 338                         reg = <0x40007000 0x400>;
 339                         clocks = <&rcc TIM13_K>;
 340                         clock-names = "int";
 341                         status = "disabled";
 342
 343                         pwm {
 344                                 compatible = "st,stm32-pwm";
 345                                 #pwm-cells = <3>;
 346                                 status = "disabled";
 347                         };
 348
 349                         timer@12 {
 350                                 compatible = "st,stm32h7-timer-trigger";
 351                                 reg = <12>;
 352                                 status = "disabled";
 353                         };
 354                 };
 355
 356                 timers14: timer@40008000 {
 357                         #address-cells = <1>;
 358                         #size-cells = <0>;
 359                         compatible = "st,stm32-timers";
 360                         reg = <0x40008000 0x400>;
 361                         clocks = <&rcc TIM14_K>;
 362                         clock-names = "int";
 363                         status = "disabled";
 364
 365                         pwm {
 366                                 compatible = "st,stm32-pwm";
 367                                 #pwm-cells = <3>;
 368                                 status = "disabled";
 369                         };
 370
 371                         timer@13 {
 372                                 compatible = "st,stm32h7-timer-trigger";
 373                                 reg = <13>;
 374                                 status = "disabled";
 375                         };
 376                 };
 377
 378                 lptimer1: timer@40009000 {
 379                         #address-cells = <1>;
 380                         #size-cells = <0>;
 381                         compatible = "st,stm32-lptimer";
 382                         reg = <0x40009000 0x400>;
 383                         interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>;
 384                         clocks = <&rcc LPTIM1_K>;
 385                         clock-names = "mux";
 386                         wakeup-source;
 387                         status = "disabled";
 388
 389                         pwm {
 390                                 compatible = "st,stm32-pwm-lp";
 391                                 #pwm-cells = <3>;
 392                                 status = "disabled";
 393                         };
 394
 395                         trigger@0 {
 396                                 compatible = "st,stm32-lptimer-trigger";
 397                                 reg = <0>;
 398                                 status = "disabled";
 399                         };
 400
 401                         counter {
 402                                 compatible = "st,stm32-lptimer-counter";
 403                                 status = "disabled";
 404                         };
 405                 };
 406
 407                 spi2: spi@4000b000 {
 408                         #address-cells = <1>;
 409                         #size-cells = <0>;
 410                         compatible = "st,stm32h7-spi";
 411                         reg = <0x4000b000 0x400>;
 412                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 413                         clocks = <&rcc SPI2_K>;
 414                         resets = <&rcc SPI2_R>;
 415                         dmas = <&dmamux1 39 0x400 0x05>,
 416                                <&dmamux1 40 0x400 0x05>;
 417                         dma-names = "rx", "tx";
 418                         status = "disabled";
 419                 };
 420
 421                 i2s2: audio-controller@4000b000 {
 422                         compatible = "st,stm32h7-i2s";
 423                         #sound-dai-cells = <0>;
 424                         reg = <0x4000b000 0x400>;
 425                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 426                         dmas = <&dmamux1 39 0x400 0x01>,
 427                                <&dmamux1 40 0x400 0x01>;
 428                         dma-names = "rx", "tx";
 429                         status = "disabled";
 430                 };
 431
 432                 spi3: spi@4000c000 {
 433                         #address-cells = <1>;
 434                         #size-cells = <0>;
 435                         compatible = "st,stm32h7-spi";
 436                         reg = <0x4000c000 0x400>;
 437                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 438                         clocks = <&rcc SPI3_K>;
 439                         resets = <&rcc SPI3_R>;
 440                         dmas = <&dmamux1 61 0x400 0x05>,
 441                                <&dmamux1 62 0x400 0x05>;
 442                         dma-names = "rx", "tx";
 443                         status = "disabled";
 444                 };
 445
 446                 i2s3: audio-controller@4000c000 {
 447                         compatible = "st,stm32h7-i2s";
 448                         #sound-dai-cells = <0>;
 449                         reg = <0x4000c000 0x400>;
 450                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 451                         dmas = <&dmamux1 61 0x400 0x01>,
 452                                <&dmamux1 62 0x400 0x01>;
 453                         dma-names = "rx", "tx";
 454                         status = "disabled";
 455                 };
 456
 457                 spdifrx: audio-controller@4000d000 {
 458                         compatible = "st,stm32h7-spdifrx";
 459                         #sound-dai-cells = <0>;
 460                         reg = <0x4000d000 0x400>;
 461                         clocks = <&rcc SPDIF_K>;
 462                         clock-names = "kclk";
 463                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 464                         dmas = <&dmamux1 93 0x400 0x01>,
 465                                <&dmamux1 94 0x400 0x01>;
 466                         dma-names = "rx", "rx-ctrl";
 467                         status = "disabled";
 468                 };
 469
 470                 usart2: serial@4000e000 {
 471                         compatible = "st,stm32h7-uart";
 472                         reg = <0x4000e000 0x400>;
 473                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 474                         clocks = <&rcc USART2_K>;
 475                         status = "disabled";
 476                 };
 477
 478                 usart3: serial@4000f000 {
 479                         compatible = "st,stm32h7-uart";
 480                         reg = <0x4000f000 0x400>;
 481                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 482                         clocks = <&rcc USART3_K>;
 483                         status = "disabled";
 484                 };
 485
 486                 uart4: serial@40010000 {
 487                         compatible = "st,stm32h7-uart";
 488                         reg = <0x40010000 0x400>;
 489                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 490                         clocks = <&rcc UART4_K>;
 491                         status = "disabled";
 492                 };
 493
 494                 uart5: serial@40011000 {
 495                         compatible = "st,stm32h7-uart";
 496                         reg = <0x40011000 0x400>;
 497                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 498                         clocks = <&rcc UART5_K>;
 499                         status = "disabled";
 500                 };
 501
 502                 i2c1: i2c@40012000 {
 503                         compatible = "st,stm32mp15-i2c";
 504                         reg = <0x40012000 0x400>;
 505                         interrupt-names = "event", "error";
 506                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
 507                                      <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 508                         clocks = <&rcc I2C1_K>;
 509                         resets = <&rcc I2C1_R>;
 510                         #address-cells = <1>;
 511                         #size-cells = <0>;
 512                         st,syscfg-fmp = <&syscfg 0x4 0x1>;
 513                         wakeup-source;
 514                         status = "disabled";
 515                 };
 516
 517                 i2c2: i2c@40013000 {
 518                         compatible = "st,stm32mp15-i2c";
 519                         reg = <0x40013000 0x400>;
 520                         interrupt-names = "event", "error";
 521                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 522                                      <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 523                         clocks = <&rcc I2C2_K>;
 524                         resets = <&rcc I2C2_R>;
 525                         #address-cells = <1>;
 526                         #size-cells = <0>;
 527                         st,syscfg-fmp = <&syscfg 0x4 0x2>;
 528                         wakeup-source;
 529                         status = "disabled";
 530                 };
 531
 532                 i2c3: i2c@40014000 {
 533                         compatible = "st,stm32mp15-i2c";
 534                         reg = <0x40014000 0x400>;
 535                         interrupt-names = "event", "error";
 536                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 537                                      <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 538                         clocks = <&rcc I2C3_K>;
 539                         resets = <&rcc I2C3_R>;
 540                         #address-cells = <1>;
 541                         #size-cells = <0>;
 542                         st,syscfg-fmp = <&syscfg 0x4 0x4>;
 543                         wakeup-source;
 544                         status = "disabled";
 545                 };
 546
 547                 i2c5: i2c@40015000 {
 548                         compatible = "st,stm32mp15-i2c";
 549                         reg = <0x40015000 0x400>;
 550                         interrupt-names = "event", "error";
 551                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 552                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 553                         clocks = <&rcc I2C5_K>;
 554                         resets = <&rcc I2C5_R>;
 555                         #address-cells = <1>;
 556                         #size-cells = <0>;
 557                         st,syscfg-fmp = <&syscfg 0x4 0x10>;
 558                         wakeup-source;
 559                         status = "disabled";
 560                 };
 561
 562                 cec: cec@40016000 {
 563                         compatible = "st,stm32-cec";
 564                         reg = <0x40016000 0x400>;
 565                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 566                         clocks = <&rcc CEC_K>, <&clk_lse>;
 567                         clock-names = "cec", "hdmi-cec";
 568                         status = "disabled";
 569                 };
 570
 571                 dac: dac@40017000 {
 572                         compatible = "st,stm32h7-dac-core";
 573                         reg = <0x40017000 0x400>;
 574                         clocks = <&rcc DAC12>;
 575                         clock-names = "pclk";
 576                         #address-cells = <1>;
 577                         #size-cells = <0>;
 578                         status = "disabled";
 579
 580                         dac1: dac@1 {
 581                                 compatible = "st,stm32-dac";
 582                                 #io-channel-cells = <1>;
 583                                 reg = <1>;
 584                                 status = "disabled";
 585                         };
 586
 587                         dac2: dac@2 {
 588                                 compatible = "st,stm32-dac";
 589                                 #io-channel-cells = <1>;
 590                                 reg = <2>;
 591                                 status = "disabled";
 592                         };
 593                 };
 594
 595                 uart7: serial@40018000 {
 596                         compatible = "st,stm32h7-uart";
 597                         reg = <0x40018000 0x400>;
 598                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 599                         clocks = <&rcc UART7_K>;
 600                         status = "disabled";
 601                 };
 602
 603                 uart8: serial@40019000 {
 604                         compatible = "st,stm32h7-uart";
 605                         reg = <0x40019000 0x400>;
 606                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 607                         clocks = <&rcc UART8_K>;
 608                         status = "disabled";
 609                 };
 610
 611                 timers1: timer@44000000 {
 612                         #address-cells = <1>;
 613                         #size-cells = <0>;
 614                         compatible = "st,stm32-timers";
 615                         reg = <0x44000000 0x400>;
 616                         clocks = <&rcc TIM1_K>;
 617                         clock-names = "int";
 618                         dmas = <&dmamux1 11 0x400 0x1>,
 619                                <&dmamux1 12 0x400 0x1>,
 620                                <&dmamux1 13 0x400 0x1>,
 621                                <&dmamux1 14 0x400 0x1>,
 622                                <&dmamux1 15 0x400 0x1>,
 623                                <&dmamux1 16 0x400 0x1>,
 624                                <&dmamux1 17 0x400 0x1>;
 625                         dma-names = "ch1", "ch2", "ch3", "ch4",
 626                                     "up", "trig", "com";
 627                         status = "disabled";
 628
 629                         pwm {
 630                                 compatible = "st,stm32-pwm";
 631                                 #pwm-cells = <3>;
 632                                 status = "disabled";
 633                         };
 634
 635                         timer@0 {
 636                                 compatible = "st,stm32h7-timer-trigger";
 637                                 reg = <0>;
 638                                 status = "disabled";
 639                         };
 640
 641                         counter {
 642                                 compatible = "st,stm32-timer-counter";
 643                                 status = "disabled";
 644                         };
 645                 };
 646
 647                 timers8: timer@44001000 {
 648                         #address-cells = <1>;
 649                         #size-cells = <0>;
 650                         compatible = "st,stm32-timers";
 651                         reg = <0x44001000 0x400>;
 652                         clocks = <&rcc TIM8_K>;
 653                         clock-names = "int";
 654                         dmas = <&dmamux1 47 0x400 0x1>,
 655                                <&dmamux1 48 0x400 0x1>,
 656                                <&dmamux1 49 0x400 0x1>,
 657                                <&dmamux1 50 0x400 0x1>,
 658                                <&dmamux1 51 0x400 0x1>,
 659                                <&dmamux1 52 0x400 0x1>,
 660                                <&dmamux1 53 0x400 0x1>;
 661                         dma-names = "ch1", "ch2", "ch3", "ch4",
 662                                     "up", "trig", "com";
 663                         status = "disabled";
 664
 665                         pwm {
 666                                 compatible = "st,stm32-pwm";
 667                                 #pwm-cells = <3>;
 668                                 status = "disabled";
 669                         };
 670
 671                         timer@7 {
 672                                 compatible = "st,stm32h7-timer-trigger";
 673                                 reg = <7>;
 674                                 status = "disabled";
 675                         };
 676
 677                         counter {
 678                                 compatible = "st,stm32-timer-counter";
 679                                 status = "disabled";
 680                         };
 681                 };
 682
 683                 usart6: serial@44003000 {
 684                         compatible = "st,stm32h7-uart";
 685                         reg = <0x44003000 0x400>;
 686                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 687                         clocks = <&rcc USART6_K>;
 688                         status = "disabled";
 689                 };
 690
 691                 spi1: spi@44004000 {
 692                         #address-cells = <1>;
 693                         #size-cells = <0>;
 694                         compatible = "st,stm32h7-spi";
 695                         reg = <0x44004000 0x400>;
 696                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 697                         clocks = <&rcc SPI1_K>;
 698                         resets = <&rcc SPI1_R>;
 699                         dmas = <&dmamux1 37 0x400 0x05>,
 700                                <&dmamux1 38 0x400 0x05>;
 701                         dma-names = "rx", "tx";
 702                         status = "disabled";
 703                 };
 704
 705                 i2s1: audio-controller@44004000 {
 706                         compatible = "st,stm32h7-i2s";
 707                         #sound-dai-cells = <0>;
 708                         reg = <0x44004000 0x400>;
 709                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 710                         dmas = <&dmamux1 37 0x400 0x01>,
 711                                <&dmamux1 38 0x400 0x01>;
 712                         dma-names = "rx", "tx";
 713                         status = "disabled";
 714                 };
 715
 716                 spi4: spi@44005000 {
 717                         #address-cells = <1>;
 718                         #size-cells = <0>;
 719                         compatible = "st,stm32h7-spi";
 720                         reg = <0x44005000 0x400>;
 721                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 722                         clocks = <&rcc SPI4_K>;
 723                         resets = <&rcc SPI4_R>;
 724                         dmas = <&dmamux1 83 0x400 0x05>,
 725                                <&dmamux1 84 0x400 0x05>;
 726                         dma-names = "rx", "tx";
 727                         status = "disabled";
 728                 };
 729
 730                 timers15: timer@44006000 {
 731                         #address-cells = <1>;
 732                         #size-cells = <0>;
 733                         compatible = "st,stm32-timers";
 734                         reg = <0x44006000 0x400>;
 735                         clocks = <&rcc TIM15_K>;
 736                         clock-names = "int";
 737                         dmas = <&dmamux1 105 0x400 0x1>,
 738                                <&dmamux1 106 0x400 0x1>,
 739                                <&dmamux1 107 0x400 0x1>,
 740                                <&dmamux1 108 0x400 0x1>;
 741                         dma-names = "ch1", "up", "trig", "com";
 742                         status = "disabled";
 743
 744                         pwm {
 745                                 compatible = "st,stm32-pwm";
 746                                 #pwm-cells = <3>;
 747                                 status = "disabled";
 748                         };
 749
 750                         timer@14 {
 751                                 compatible = "st,stm32h7-timer-trigger";
 752                                 reg = <14>;
 753                                 status = "disabled";
 754                         };
 755                 };
 756
 757                 timers16: timer@44007000 {
 758                         #address-cells = <1>;
 759                         #size-cells = <0>;
 760                         compatible = "st,stm32-timers";
 761                         reg = <0x44007000 0x400>;
 762                         clocks = <&rcc TIM16_K>;
 763                         clock-names = "int";
 764                         dmas = <&dmamux1 109 0x400 0x1>,
 765                                <&dmamux1 110 0x400 0x1>;
 766                         dma-names = "ch1", "up";
 767                         status = "disabled";
 768
 769                         pwm {
 770                                 compatible = "st,stm32-pwm";
 771                                 #pwm-cells = <3>;
 772                                 status = "disabled";
 773                         };
 774                         timer@15 {
 775                                 compatible = "st,stm32h7-timer-trigger";
 776                                 reg = <15>;
 777                                 status = "disabled";
 778                         };
 779                 };
 780
 781                 timers17: timer@44008000 {
 782                         #address-cells = <1>;
 783                         #size-cells = <0>;
 784                         compatible = "st,stm32-timers";
 785                         reg = <0x44008000 0x400>;
 786                         clocks = <&rcc TIM17_K>;
 787                         clock-names = "int";
 788                         dmas = <&dmamux1 111 0x400 0x1>,
 789                                <&dmamux1 112 0x400 0x1>;
 790                         dma-names = "ch1", "up";
 791                         status = "disabled";
 792
 793                         pwm {
 794                                 compatible = "st,stm32-pwm";
 795                                 #pwm-cells = <3>;
 796                                 status = "disabled";
 797                         };
 798
 799                         timer@16 {
 800                                 compatible = "st,stm32h7-timer-trigger";
 801                                 reg = <16>;
 802                                 status = "disabled";
 803                         };
 804                 };
 805
 806                 spi5: spi@44009000 {
 807                         #address-cells = <1>;
 808                         #size-cells = <0>;
 809                         compatible = "st,stm32h7-spi";
 810                         reg = <0x44009000 0x400>;
 811                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 812                         clocks = <&rcc SPI5_K>;
 813                         resets = <&rcc SPI5_R>;
 814                         dmas = <&dmamux1 85 0x400 0x05>,
 815                                <&dmamux1 86 0x400 0x05>;
 816                         dma-names = "rx", "tx";
 817                         status = "disabled";
 818                 };
 819
 820                 sai1: sai@4400a000 {
 821                         compatible = "st,stm32h7-sai";
 822                         #address-cells = <1>;
 823                         #size-cells = <1>;
 824                         ranges = <0 0x4400a000 0x400>;
 825                         reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
 826                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 827                         resets = <&rcc SAI1_R>;
 828                         status = "disabled";
 829
 830                         sai1a: audio-controller@4400a004 {
 831                                 #sound-dai-cells = <0>;
 832
 833                                 compatible = "st,stm32-sai-sub-a";
 834                                 reg = <0x4 0x1c>;
 835                                 clocks = <&rcc SAI1_K>;
 836                                 clock-names = "sai_ck";
 837                                 dmas = <&dmamux1 87 0x400 0x01>;
 838                                 status = "disabled";
 839                         };
 840
 841                         sai1b: audio-controller@4400a024 {
 842                                 #sound-dai-cells = <0>;
 843                                 compatible = "st,stm32-sai-sub-b";
 844                                 reg = <0x24 0x1c>;
 845                                 clocks = <&rcc SAI1_K>;
 846                                 clock-names = "sai_ck";
 847                                 dmas = <&dmamux1 88 0x400 0x01>;
 848                                 status = "disabled";
 849                         };
 850                 };
 851
 852                 sai2: sai@4400b000 {
 853                         compatible = "st,stm32h7-sai";
 854                         #address-cells = <1>;
 855                         #size-cells = <1>;
 856                         ranges = <0 0x4400b000 0x400>;
 857                         reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
 858                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 859                         resets = <&rcc SAI2_R>;
 860                         status = "disabled";
 861
 862                         sai2a: audio-controller@4400b004 {
 863                                 #sound-dai-cells = <0>;
 864                                 compatible = "st,stm32-sai-sub-a";
 865                                 reg = <0x4 0x1c>;
 866                                 clocks = <&rcc SAI2_K>;
 867                                 clock-names = "sai_ck";
 868                                 dmas = <&dmamux1 89 0x400 0x01>;
 869                                 status = "disabled";
 870                         };
 871
 872                         sai2b: audio-controller@4400b024 {
 873                                 #sound-dai-cells = <0>;
 874                                 compatible = "st,stm32-sai-sub-b";
 875                                 reg = <0x24 0x1c>;
 876                                 clocks = <&rcc SAI2_K>;
 877                                 clock-names = "sai_ck";
 878                                 dmas = <&dmamux1 90 0x400 0x01>;
 879                                 status = "disabled";
 880                         };
 881                 };
 882
 883                 sai3: sai@4400c000 {
 884                         compatible = "st,stm32h7-sai";
 885                         #address-cells = <1>;
 886                         #size-cells = <1>;
 887                         ranges = <0 0x4400c000 0x400>;
 888                         reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
 889                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 890                         resets = <&rcc SAI3_R>;
 891                         status = "disabled";
 892
 893                         sai3a: audio-controller@4400c004 {
 894                                 #sound-dai-cells = <0>;
 895                                 compatible = "st,stm32-sai-sub-a";
 896                                 reg = <0x04 0x1c>;
 897                                 clocks = <&rcc SAI3_K>;
 898                                 clock-names = "sai_ck";
 899                                 dmas = <&dmamux1 113 0x400 0x01>;
 900                                 status = "disabled";
 901                         };
 902
 903                         sai3b: audio-controller@4400c024 {
 904                                 #sound-dai-cells = <0>;
 905                                 compatible = "st,stm32-sai-sub-b";
 906                                 reg = <0x24 0x1c>;
 907                                 clocks = <&rcc SAI3_K>;
 908                                 clock-names = "sai_ck";
 909                                 dmas = <&dmamux1 114 0x400 0x01>;
 910                                 status = "disabled";
 911                         };
 912                 };
 913
 914                 dfsdm: dfsdm@4400d000 {
 915                         compatible = "st,stm32mp1-dfsdm";
 916                         reg = <0x4400d000 0x800>;
 917                         clocks = <&rcc DFSDM_K>;
 918                         clock-names = "dfsdm";
 919                         #address-cells = <1>;
 920                         #size-cells = <0>;
 921                         status = "disabled";
 922
 923                         dfsdm0: filter@0 {
 924                                 compatible = "st,stm32-dfsdm-adc";
 925                                 #io-channel-cells = <1>;
 926                                 reg = <0>;
 927                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 928                                 dmas = <&dmamux1 101 0x400 0x01>;
 929                                 dma-names = "rx";
 930                                 status = "disabled";
 931                         };
 932
 933                         dfsdm1: filter@1 {
 934                                 compatible = "st,stm32-dfsdm-adc";
 935                                 #io-channel-cells = <1>;
 936                                 reg = <1>;
 937                                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 938                                 dmas = <&dmamux1 102 0x400 0x01>;
 939                                 dma-names = "rx";
 940                                 status = "disabled";
 941                         };
 942
 943                         dfsdm2: filter@2 {
 944                                 compatible = "st,stm32-dfsdm-adc";
 945                                 #io-channel-cells = <1>;
 946                                 reg = <2>;
 947                                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 948                                 dmas = <&dmamux1 103 0x400 0x01>;
 949                                 dma-names = "rx";
 950                                 status = "disabled";
 951                         };
 952
 953                         dfsdm3: filter@3 {
 954                                 compatible = "st,stm32-dfsdm-adc";
 955                                 #io-channel-cells = <1>;
 956                                 reg = <3>;
 957                                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 958                                 dmas = <&dmamux1 104 0x400 0x01>;
 959                                 dma-names = "rx";
 960                                 status = "disabled";
 961                         };
 962
 963                         dfsdm4: filter@4 {
 964                                 compatible = "st,stm32-dfsdm-adc";
 965                                 #io-channel-cells = <1>;
 966                                 reg = <4>;
 967                                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 968                                 dmas = <&dmamux1 91 0x400 0x01>;
 969                                 dma-names = "rx";
 970                                 status = "disabled";
 971                         };
 972
 973                         dfsdm5: filter@5 {
 974                                 compatible = "st,stm32-dfsdm-adc";
 975                                 #io-channel-cells = <1>;
 976                                 reg = <5>;
 977                                 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 978                                 dmas = <&dmamux1 92 0x400 0x01>;
 979                                 dma-names = "rx";
 980                                 status = "disabled";
 981                         };
 982                 };
 983
 984                 dma1: dma-controller@48000000 {
 985                         compatible = "st,stm32-dma";
 986                         reg = <0x48000000 0x400>;
 987                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 988                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 989                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 990                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 991                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 992                                      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 993                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 994                                      <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 995                         clocks = <&rcc DMA1>;
 996                         resets = <&rcc DMA1_R>;
 997                         #dma-cells = <4>;
 998                         st,mem2mem;
 999                         dma-requests = <8>;
1000                 };
1001
1002                 dma2: dma-controller@48001000 {
1003                         compatible = "st,stm32-dma";
1004                         reg = <0x48001000 0x400>;
1005                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
1006                                      <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
1007                                      <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
1008                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
1009                                      <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
1010                                      <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
1011                                      <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1012                                      <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1013                         clocks = <&rcc DMA2>;
1014                         resets = <&rcc DMA2_R>;
1015                         #dma-cells = <4>;
1016                         st,mem2mem;
1017                         dma-requests = <8>;
1018                 };
1019
1020                 dmamux1: dma-router@48002000 {
1021                         compatible = "st,stm32h7-dmamux";
1022                         reg = <0x48002000 0x40>;
1023                         #dma-cells = <3>;
1024                         dma-requests = <128>;
1025                         dma-masters = <&dma1 &dma2>;
1026                         dma-channels = <16>;
1027                         clocks = <&rcc DMAMUX>;
1028                         resets = <&rcc DMAMUX_R>;
1029                 };
1030
1031                 adc: adc@48003000 {
1032                         compatible = "st,stm32mp1-adc-core";
1033                         reg = <0x48003000 0x400>;
1034                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
1035                                      <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1036                         clocks = <&rcc ADC12>, <&rcc ADC12_K>;
1037                         clock-names = "bus", "adc";
1038                         interrupt-controller;
1039                         st,syscfg = <&syscfg>;
1040                         #interrupt-cells = <1>;
1041                         #address-cells = <1>;
1042                         #size-cells = <0>;
1043                         status = "disabled";
1044
1045                         adc1: adc@0 {
1046                                 compatible = "st,stm32mp1-adc";
1047                                 #io-channel-cells = <1>;
1048                                 reg = <0x0>;
1049                                 interrupt-parent = <&adc>;
1050                                 interrupts = <0>;
1051                                 dmas = <&dmamux1 9 0x400 0x01>;
1052                                 dma-names = "rx";
1053                                 status = "disabled";
1054                         };
1055
1056                         adc2: adc@100 {
1057                                 compatible = "st,stm32mp1-adc";
1058                                 #io-channel-cells = <1>;
1059                                 reg = <0x100>;
1060                                 interrupt-parent = <&adc>;
1061                                 interrupts = <1>;
1062                                 dmas = <&dmamux1 10 0x400 0x01>;
1063                                 dma-names = "rx";
1064                                 status = "disabled";
1065                         };
1066                 };
1067
1068                 sdmmc3: sdmmc@48004000 {
1069                         compatible = "arm,pl18x", "arm,primecell";
1070                         arm,primecell-periphid = <0x00253180>;
1071                         reg = <0x48004000 0x400>;
1072                         interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
1073                         interrupt-names = "cmd_irq";
1074                         clocks = <&rcc SDMMC3_K>;
1075                         clock-names = "apb_pclk";
1076                         resets = <&rcc SDMMC3_R>;
1077                         cap-sd-highspeed;
1078                         cap-mmc-highspeed;
1079                         max-frequency = <120000000>;
1080                         status = "disabled";
1081                 };
1082
1083                 usbotg_hs: usb-otg@49000000 {
1084                         compatible = "st,stm32mp15-hsotg", "snps,dwc2";
1085                         reg = <0x49000000 0x10000>;
1086                         clocks = <&rcc USBO_K>;
1087                         clock-names = "otg";
1088                         resets = <&rcc USBO_R>;
1089                         reset-names = "dwc2";
1090                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1091                         g-rx-fifo-size = <512>;
1092                         g-np-tx-fifo-size = <32>;
1093                         g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
1094                         dr_mode = "otg";
1095                         usb33d-supply = <&usb33>;
1096                         status = "disabled";
1097                 };
1098
1099                 hwspinlock: hwspinlock@4c000000 {
1100                         compatible = "st,stm32-hwspinlock";
1101                         #hwlock-cells = <1>;
1102                         reg = <0x4c000000 0x400>;
1103                         clocks = <&rcc HSEM>;
1104                         clock-names = "hwspinlock";
1105                 };
1106
1107                 ipcc: mailbox@4c001000 {
1108                         compatible = "st,stm32mp1-ipcc";
1109                         #mbox-cells = <1>;
1110                         reg = <0x4c001000 0x400>;
1111                         st,proc-id = <0>;
1112                         interrupts-extended =
1113                                 <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1114                                 <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1115                                 <&exti 61 1>;
1116                         interrupt-names = "rx", "tx", "wakeup";
1117                         clocks = <&rcc IPCC>;
1118                         wakeup-source;
1119                         status = "disabled";
1120                 };
1121
1122                 dcmi: dcmi@4c006000 {
1123                         compatible = "st,stm32-dcmi";
1124                         reg = <0x4c006000 0x400>;
1125                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1126                         resets = <&rcc CAMITF_R>;
1127                         clocks = <&rcc DCMI>;
1128                         clock-names = "mclk";
1129                         dmas = <&dmamux1 75 0x400 0x01>;
1130                         dma-names = "tx";
1131                         status = "disabled";
1132                 };
1133
1134                 rcc: rcc@50000000 {
1135                         compatible = "st,stm32mp1-rcc", "syscon";
1136                         reg = <0x50000000 0x1000>;
1137                         #clock-cells = <1>;
1138                         #reset-cells = <1>;
1139
1140                         clock-names = "hse", "hsi", "csi", "lse", "lsi";
1141                         clocks = <&clk_hse>, <&clk_hsi>, <&clk_csi>,
1142                                  <&clk_lse>, <&clk_lsi>;
1143                 };
1144
1145                 pwr_regulators: pwr@50001000 {
1146                         compatible = "st,stm32mp1,pwr-reg";
1147                         reg = <0x50001000 0x10>;
1148
1149                         reg11: reg11 {
1150                                 regulator-name = "reg11";
1151                                 regulator-min-microvolt = <1100000>;
1152                                 regulator-max-microvolt = <1100000>;
1153                         };
1154
1155                         reg18: reg18 {
1156                                 regulator-name = "reg18";
1157                                 regulator-min-microvolt = <1800000>;
1158                                 regulator-max-microvolt = <1800000>;
1159                         };
1160
1161                         usb33: usb33 {
1162                                 regulator-name = "usb33";
1163                                 regulator-min-microvolt = <3300000>;
1164                                 regulator-max-microvolt = <3300000>;
1165                         };
1166                 };
1167
1168                 pwr_mcu: pwr_mcu@50001014 {
1169                         compatible = "st,stm32mp151-pwr-mcu", "syscon";
1170                         reg = <0x50001014 0x4>;
1171                 };
1172
1173                 exti: interrupt-controller@5000d000 {
1174                         compatible = "st,stm32mp1-exti", "syscon";
1175                         interrupt-controller;
1176                         #interrupt-cells = <2>;
1177                         reg = <0x5000d000 0x400>;
1178                 };
1179
1180                 syscfg: syscon@50020000 {
1181                         compatible = "st,stm32mp157-syscfg", "syscon";
1182                         reg = <0x50020000 0x400>;
1183                         clocks = <&rcc SYSCFG>;
1184                 };
1185
1186                 lptimer2: timer@50021000 {
1187                         #address-cells = <1>;
1188                         #size-cells = <0>;
1189                         compatible = "st,stm32-lptimer";
1190                         reg = <0x50021000 0x400>;
1191                         interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>;
1192                         clocks = <&rcc LPTIM2_K>;
1193                         clock-names = "mux";
1194                         wakeup-source;
1195                         status = "disabled";
1196
1197                         pwm {
1198                                 compatible = "st,stm32-pwm-lp";
1199                                 #pwm-cells = <3>;
1200                                 status = "disabled";
1201                         };
1202
1203                         trigger@1 {
1204                                 compatible = "st,stm32-lptimer-trigger";
1205                                 reg = <1>;
1206                                 status = "disabled";
1207                         };
1208
1209                         counter {
1210                                 compatible = "st,stm32-lptimer-counter";
1211                                 status = "disabled";
1212                         };
1213                 };
1214
1215                 lptimer3: timer@50022000 {
1216                         #address-cells = <1>;
1217                         #size-cells = <0>;
1218                         compatible = "st,stm32-lptimer";
1219                         reg = <0x50022000 0x400>;
1220                         interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>;
1221                         clocks = <&rcc LPTIM3_K>;
1222                         clock-names = "mux";
1223                         wakeup-source;
1224                         status = "disabled";
1225
1226                         pwm {
1227                                 compatible = "st,stm32-pwm-lp";
1228                                 #pwm-cells = <3>;
1229                                 status = "disabled";
1230                         };
1231
1232                         trigger@2 {
1233                                 compatible = "st,stm32-lptimer-trigger";
1234                                 reg = <2>;
1235                                 status = "disabled";
1236                         };
1237                 };
1238
1239                 lptimer4: timer@50023000 {
1240                         compatible = "st,stm32-lptimer";
1241                         reg = <0x50023000 0x400>;
1242                         interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>;
1243                         clocks = <&rcc LPTIM4_K>;
1244                         clock-names = "mux";
1245                         wakeup-source;
1246                         status = "disabled";
1247
1248                         pwm {
1249                                 compatible = "st,stm32-pwm-lp";
1250                                 #pwm-cells = <3>;
1251                                 status = "disabled";
1252                         };
1253                 };
1254
1255                 lptimer5: timer@50024000 {
1256                         compatible = "st,stm32-lptimer";
1257                         reg = <0x50024000 0x400>;
1258                         interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>;
1259                         clocks = <&rcc LPTIM5_K>;
1260                         clock-names = "mux";
1261                         wakeup-source;
1262                         status = "disabled";
1263
1264                         pwm {
1265                                 compatible = "st,stm32-pwm-lp";
1266                                 #pwm-cells = <3>;
1267                                 status = "disabled";
1268                         };
1269                 };
1270
1271                 vrefbuf: vrefbuf@50025000 {
1272                         compatible = "st,stm32-vrefbuf";
1273                         reg = <0x50025000 0x8>;
1274                         regulator-min-microvolt = <1500000>;
1275                         regulator-max-microvolt = <2500000>;
1276                         clocks = <&rcc VREF>;
1277                         status = "disabled";
1278                 };
1279
1280                 sai4: sai@50027000 {
1281                         compatible = "st,stm32h7-sai";
1282                         #address-cells = <1>;
1283                         #size-cells = <1>;
1284                         ranges = <0 0x50027000 0x400>;
1285                         reg = <0x50027000 0x4>, <0x500273f0 0x10>;
1286                         interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
1287                         resets = <&rcc SAI4_R>;
1288                         status = "disabled";
1289
1290                         sai4a: audio-controller@50027004 {
1291                                 #sound-dai-cells = <0>;
1292                                 compatible = "st,stm32-sai-sub-a";
1293                                 reg = <0x04 0x1c>;
1294                                 clocks = <&rcc SAI4_K>;
1295                                 clock-names = "sai_ck";
1296                                 dmas = <&dmamux1 99 0x400 0x01>;
1297                                 status = "disabled";
1298                         };
1299
1300                         sai4b: audio-controller@50027024 {
1301                                 #sound-dai-cells = <0>;
1302                                 compatible = "st,stm32-sai-sub-b";
1303                                 reg = <0x24 0x1c>;
1304                                 clocks = <&rcc SAI4_K>;
1305                                 clock-names = "sai_ck";
1306                                 dmas = <&dmamux1 100 0x400 0x01>;
1307                                 status = "disabled";
1308                         };
1309                 };
1310
1311                 dts: thermal@50028000 {
1312                         compatible = "st,stm32-thermal";
1313                         reg = <0x50028000 0x100>;
1314                         interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1315                         clocks = <&rcc TMPSENS>;
1316                         clock-names = "pclk";
1317                         #thermal-sensor-cells = <0>;
1318                         status = "disabled";
1319                 };
1320
1321                 hash1: hash@54002000 {
1322                         compatible = "st,stm32f756-hash";
1323                         reg = <0x54002000 0x400>;
1324                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1325                         clocks = <&rcc HASH1>;
1326                         resets = <&rcc HASH1_R>;
1327                         dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>;
1328                         dma-names = "in";
1329                         dma-maxburst = <2>;
1330                         status = "disabled";
1331                 };
1332
1333                 rng1: rng@54003000 {
1334                         compatible = "st,stm32-rng";
1335                         reg = <0x54003000 0x400>;
1336                         clocks = <&rcc RNG1_K>;
1337                         resets = <&rcc RNG1_R>;
1338                         status = "disabled";
1339                 };
1340
1341                 mdma1: dma-controller@58000000 {
1342                         compatible = "st,stm32h7-mdma";
1343                         reg = <0x58000000 0x1000>;
1344                         interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1345                         clocks = <&rcc MDMA>;
1346                         resets = <&rcc MDMA_R>;
1347                         #dma-cells = <5>;
1348                         dma-channels = <32>;
1349                         dma-requests = <48>;
1350                 };
1351
1352                 fmc: memory-controller@58002000 {
1353                         #address-cells = <2>;
1354                         #size-cells = <1>;
1355                         compatible = "st,stm32mp1-fmc2-ebi";
1356                         reg = <0x58002000 0x1000>;
1357                         clocks = <&rcc FMC_K>;
1358                         resets = <&rcc FMC_R>;
1359                         status = "disabled";
1360
1361                         ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
1362                                  <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
1363                                  <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
1364                                  <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
1365                                  <4 0 0x80000000 0x10000000>; /* NAND */
1366
1367                         nand-controller@4,0 {
1368                                 #address-cells = <1>;
1369                                 #size-cells = <0>;
1370                                 compatible = "st,stm32mp1-fmc2-nfc";
1371                                 reg = <4 0x00000000 0x1000>,
1372                                       <4 0x08010000 0x1000>,
1373                                       <4 0x08020000 0x1000>,
1374                                       <4 0x01000000 0x1000>,
1375                                       <4 0x09010000 0x1000>,
1376                                       <4 0x09020000 0x1000>;
1377                                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1378                                 dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
1379                                        <&mdma1 20 0x2 0x12000a08 0x0 0x0>,
1380                                        <&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
1381                                 dma-names = "tx", "rx", "ecc";
1382                                 status = "disabled";
1383                         };
1384                 };
1385
1386                 qspi: spi@58003000 {
1387                         compatible = "st,stm32f469-qspi";
1388                         reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
1389                         reg-names = "qspi", "qspi_mm";
1390                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
1391                         dmas = <&mdma1 22 0x2 0x100002 0x0 0x0>,
1392                                <&mdma1 22 0x2 0x100008 0x0 0x0>;
1393                         dma-names = "tx", "rx";
1394                         clocks = <&rcc QSPI_K>;
1395                         resets = <&rcc QSPI_R>;
1396                         #address-cells = <1>;
1397                         #size-cells = <0>;
1398                         status = "disabled";
1399                 };
1400
1401                 sdmmc1: sdmmc@58005000 {
1402                         compatible = "arm,pl18x", "arm,primecell";
1403                         arm,primecell-periphid = <0x00253180>;
1404                         reg = <0x58005000 0x1000>;
1405                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1406                         interrupt-names = "cmd_irq";
1407                         clocks = <&rcc SDMMC1_K>;
1408                         clock-names = "apb_pclk";
1409                         resets = <&rcc SDMMC1_R>;
1410                         cap-sd-highspeed;
1411                         cap-mmc-highspeed;
1412                         max-frequency = <120000000>;
1413                         status = "disabled";
1414                 };
1415
1416                 sdmmc2: sdmmc@58007000 {
1417                         compatible = "arm,pl18x", "arm,primecell";
1418                         arm,primecell-periphid = <0x00253180>;
1419                         reg = <0x58007000 0x1000>;
1420                         interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
1421                         interrupt-names = "cmd_irq";
1422                         clocks = <&rcc SDMMC2_K>;
1423                         clock-names = "apb_pclk";
1424                         resets = <&rcc SDMMC2_R>;
1425                         cap-sd-highspeed;
1426                         cap-mmc-highspeed;
1427                         max-frequency = <120000000>;
1428                         status = "disabled";
1429                 };
1430
1431                 crc1: crc@58009000 {
1432                         compatible = "st,stm32f7-crc";
1433                         reg = <0x58009000 0x400>;
1434                         clocks = <&rcc CRC1>;
1435                         status = "disabled";
1436                 };
1437
1438                 stmmac_axi_config_0: stmmac-axi-config {
1439                         snps,wr_osr_lmt = <0x7>;
1440                         snps,rd_osr_lmt = <0x7>;
1441                         snps,blen = <0 0 0 0 16 8 4>;
1442                 };
1443
1444                 ethernet0: ethernet@5800a000 {
1445                         compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
1446                         reg = <0x5800a000 0x2000>;
1447                         reg-names = "stmmaceth";
1448                         interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1449                         interrupt-names = "macirq";
1450                         clock-names = "stmmaceth",
1451                                       "mac-clk-tx",
1452                                       "mac-clk-rx",
1453                                       "eth-ck",
1454                                       "ethstp";
1455                         clocks = <&rcc ETHMAC>,
1456                                  <&rcc ETHTX>,
1457                                  <&rcc ETHRX>,
1458                                  <&rcc ETHCK_K>,
1459                                  <&rcc ETHSTP>;
1460                         st,syscon = <&syscfg 0x4>;
1461                         snps,mixed-burst;
1462                         snps,pbl = <2>;
1463                         snps,en-tx-lpi-clockgating;
1464                         snps,axi-config = <&stmmac_axi_config_0>;
1465                         snps,tso;
1466                         status = "disabled";
1467                 };
1468
1469                 usbh_ohci: usb@5800c000 {
1470                         compatible = "generic-ohci";
1471                         reg = <0x5800c000 0x1000>;
1472                         clocks = <&rcc USBH>;
1473                         resets = <&rcc USBH_R>;
1474                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1475                         status = "disabled";
1476                 };
1477
1478                 usbh_ehci: usb@5800d000 {
1479                         compatible = "generic-ehci";
1480                         reg = <0x5800d000 0x1000>;
1481                         clocks = <&rcc USBH>;
1482                         resets = <&rcc USBH_R>;
1483                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1484                         companion = <&usbh_ohci>;
1485                         status = "disabled";
1486                 };
1487
1488                 ltdc: display-controller@5a001000 {
1489                         compatible = "st,stm32-ltdc";
1490                         reg = <0x5a001000 0x400>;
1491                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1492                                      <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1493                         clocks = <&rcc LTDC_PX>;
1494                         clock-names = "lcd";
1495                         resets = <&rcc LTDC_R>;
1496                         status = "disabled";
1497
1498                         port {
1499                                 #address-cells = <1>;
1500                                 #size-cells = <0>;
1501                         };
1502                 };
1503
1504                 iwdg2: watchdog@5a002000 {
1505                         compatible = "st,stm32mp1-iwdg";
1506                         reg = <0x5a002000 0x400>;
1507                         clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
1508                         clock-names = "pclk", "lsi";
1509                         status = "disabled";
1510                 };
1511
1512                 usbphyc: usbphyc@5a006000 {
1513                         #address-cells = <1>;
1514                         #size-cells = <0>;
1515                         compatible = "st,stm32mp1-usbphyc";
1516                         reg = <0x5a006000 0x1000>;
1517                         clocks = <&rcc USBPHY_K>;
1518                         resets = <&rcc USBPHY_R>;
1519                         vdda1v1-supply = <&reg11>;
1520                         vdda1v8-supply = <&reg18>;
1521                         status = "disabled";
1522
1523                         usbphyc_port0: usb-phy@0 {
1524                                 #phy-cells = <0>;
1525                                 reg = <0>;
1526                         };
1527
1528                         usbphyc_port1: usb-phy@1 {
1529                                 #phy-cells = <1>;
1530                                 reg = <1>;
1531                         };
1532                 };
1533
1534                 usart1: serial@5c000000 {
1535                         compatible = "st,stm32h7-uart";
1536                         reg = <0x5c000000 0x400>;
1537                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1538                         clocks = <&rcc USART1_K>;
1539                         status = "disabled";
1540                 };
1541
1542                 spi6: spi@5c001000 {
1543                         #address-cells = <1>;
1544                         #size-cells = <0>;
1545                         compatible = "st,stm32h7-spi";
1546                         reg = <0x5c001000 0x400>;
1547                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1548                         clocks = <&rcc SPI6_K>;
1549                         resets = <&rcc SPI6_R>;
1550                         dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
1551                                <&mdma1 35 0x0 0x40002 0x0 0x0>;
1552                         dma-names = "rx", "tx";
1553                         status = "disabled";
1554                 };
1555
1556                 i2c4: i2c@5c002000 {
1557                         compatible = "st,stm32mp15-i2c";
1558                         reg = <0x5c002000 0x400>;
1559                         interrupt-names = "event", "error";
1560                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1561                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1562                         clocks = <&rcc I2C4_K>;
1563                         resets = <&rcc I2C4_R>;
1564                         #address-cells = <1>;
1565                         #size-cells = <0>;
1566                         st,syscfg-fmp = <&syscfg 0x4 0x8>;
1567                         wakeup-source;
1568                         status = "disabled";
1569                 };
1570
1571                 rtc: rtc@5c004000 {
1572                         compatible = "st,stm32mp1-rtc";
1573                         reg = <0x5c004000 0x400>;
1574                         clocks = <&rcc RTCAPB>, <&rcc RTC>;
1575                         clock-names = "pclk", "rtc_ck";
1576                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1577                         status = "disabled";
1578                 };
1579
1580                 bsec: efuse@5c005000 {
1581                         compatible = "st,stm32mp15-bsec";
1582                         reg = <0x5c005000 0x400>;
1583                         #address-cells = <1>;
1584                         #size-cells = <1>;
1585                         part_number_otp: part_number_otp@4 {
1586                                 reg = <0x4 0x1>;
1587                         };
1588                         ts_cal1: calib@5c {
1589                                 reg = <0x5c 0x2>;
1590                         };
1591                         ts_cal2: calib@5e {
1592                                 reg = <0x5e 0x2>;
1593                         };
1594                 };
1595
1596                 i2c6: i2c@5c009000 {
1597                         compatible = "st,stm32mp15-i2c";
1598                         reg = <0x5c009000 0x400>;
1599                         interrupt-names = "event", "error";
1600                         interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1601                                      <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1602                         clocks = <&rcc I2C6_K>;
1603                         resets = <&rcc I2C6_R>;
1604                         #address-cells = <1>;
1605                         #size-cells = <0>;
1606                         st,syscfg-fmp = <&syscfg 0x4 0x20>;
1607                         wakeup-source;
1608                         status = "disabled";
1609                 };
1610
1611                 tamp: tamp@5c00a000 {
1612                         compatible = "st,stm32-tamp", "syscon", "simple-mfd";
1613                         reg = <0x5c00a000 0x400>;
1614                 };
1615
1616                 /*
1617                  * Break node order to solve dependency probe issue between
1618                  * pinctrl and exti.
1619                  */
1620                 pinctrl: pin-controller@50002000 {
1621                         #address-cells = <1>;
1622                         #size-cells = <1>;
1623                         compatible = "st,stm32mp157-pinctrl";
1624                         ranges = <0 0x50002000 0xa400>;
1625                         interrupt-parent = <&exti>;
1626                         st,syscfg = <&exti 0x60 0xff>;
1627                         hwlocks = <&hwspinlock 0>;
1628                         pins-are-numbered;
1629
1630                         gpioa: gpio@50002000 {
1631                                 gpio-controller;
1632                                 #gpio-cells = <2>;
1633                                 interrupt-controller;
1634                                 #interrupt-cells = <2>;
1635                                 reg = <0x0 0x400>;
1636                                 clocks = <&rcc GPIOA>;
1637                                 st,bank-name = "GPIOA";
1638                                 status = "disabled";
1639                         };
1640
1641                         gpiob: gpio@50003000 {
1642                                 gpio-controller;
1643                                 #gpio-cells = <2>;
1644                                 interrupt-controller;
1645                                 #interrupt-cells = <2>;
1646                                 reg = <0x1000 0x400>;
1647                                 clocks = <&rcc GPIOB>;
1648                                 st,bank-name = "GPIOB";
1649                                 status = "disabled";
1650                         };
1651
1652                         gpioc: gpio@50004000 {
1653                                 gpio-controller;
1654                                 #gpio-cells = <2>;
1655                                 interrupt-controller;
1656                                 #interrupt-cells = <2>;
1657                                 reg = <0x2000 0x400>;
1658                                 clocks = <&rcc GPIOC>;
1659                                 st,bank-name = "GPIOC";
1660                                 status = "disabled";
1661                         };
1662
1663                         gpiod: gpio@50005000 {
1664                                 gpio-controller;
1665                                 #gpio-cells = <2>;
1666                                 interrupt-controller;
1667                                 #interrupt-cells = <2>;
1668                                 reg = <0x3000 0x400>;
1669                                 clocks = <&rcc GPIOD>;
1670                                 st,bank-name = "GPIOD";
1671                                 status = "disabled";
1672                         };
1673
1674                         gpioe: gpio@50006000 {
1675                                 gpio-controller;
1676                                 #gpio-cells = <2>;
1677                                 interrupt-controller;
1678                                 #interrupt-cells = <2>;
1679                                 reg = <0x4000 0x400>;
1680                                 clocks = <&rcc GPIOE>;
1681                                 st,bank-name = "GPIOE";
1682                                 status = "disabled";
1683                         };
1684
1685                         gpiof: gpio@50007000 {
1686                                 gpio-controller;
1687                                 #gpio-cells = <2>;
1688                                 interrupt-controller;
1689                                 #interrupt-cells = <2>;
1690                                 reg = <0x5000 0x400>;
1691                                 clocks = <&rcc GPIOF>;
1692                                 st,bank-name = "GPIOF";
1693                                 status = "disabled";
1694                         };
1695
1696                         gpiog: gpio@50008000 {
1697                                 gpio-controller;
1698                                 #gpio-cells = <2>;
1699                                 interrupt-controller;
1700                                 #interrupt-cells = <2>;
1701                                 reg = <0x6000 0x400>;
1702                                 clocks = <&rcc GPIOG>;
1703                                 st,bank-name = "GPIOG";
1704                                 status = "disabled";
1705                         };
1706
1707                         gpioh: gpio@50009000 {
1708                                 gpio-controller;
1709                                 #gpio-cells = <2>;
1710                                 interrupt-controller;
1711                                 #interrupt-cells = <2>;
1712                                 reg = <0x7000 0x400>;
1713                                 clocks = <&rcc GPIOH>;
1714                                 st,bank-name = "GPIOH";
1715                                 status = "disabled";
1716                         };
1717
1718                         gpioi: gpio@5000a000 {
1719                                 gpio-controller;
1720                                 #gpio-cells = <2>;
1721                                 interrupt-controller;
1722                                 #interrupt-cells = <2>;
1723                                 reg = <0x8000 0x400>;
1724                                 clocks = <&rcc GPIOI>;
1725                                 st,bank-name = "GPIOI";
1726                                 status = "disabled";
1727                         };
1728
1729                         gpioj: gpio@5000b000 {
1730                                 gpio-controller;
1731                                 #gpio-cells = <2>;
1732                                 interrupt-controller;
1733                                 #interrupt-cells = <2>;
1734                                 reg = <0x9000 0x400>;
1735                                 clocks = <&rcc GPIOJ>;
1736                                 st,bank-name = "GPIOJ";
1737                                 status = "disabled";
1738                         };
1739
1740                         gpiok: gpio@5000c000 {
1741                                 gpio-controller;
1742                                 #gpio-cells = <2>;
1743                                 interrupt-controller;
1744                                 #interrupt-cells = <2>;
1745                                 reg = <0xa000 0x400>;
1746                                 clocks = <&rcc GPIOK>;
1747                                 st,bank-name = "GPIOK";
1748                                 status = "disabled";
1749                         };
1750                 };
1751
1752                 pinctrl_z: pin-controller-z@54004000 {
1753                         #address-cells = <1>;
1754                         #size-cells = <1>;
1755                         compatible = "st,stm32mp157-z-pinctrl";
1756                         ranges = <0 0x54004000 0x400>;
1757                         pins-are-numbered;
1758                         interrupt-parent = <&exti>;
1759                         st,syscfg = <&exti 0x60 0xff>;
1760                         hwlocks = <&hwspinlock 0>;
1761
1762                         gpioz: gpio@54004000 {
1763                                 gpio-controller;
1764                                 #gpio-cells = <2>;
1765                                 interrupt-controller;
1766                                 #interrupt-cells = <2>;
1767                                 reg = <0 0x400>;
1768                                 clocks = <&rcc GPIOZ>;
1769                                 st,bank-name = "GPIOZ";
1770                                 st,bank-ioport = <11>;
1771                                 status = "disabled";
1772                         };
1773                 };
1774         };
1775
1776         mlahb: ahb {
1777                 compatible = "st,mlahb", "simple-bus";
1778                 #address-cells = <1>;
1779                 #size-cells = <1>;
1780                 ranges;
1781                 dma-ranges = <0x00000000 0x38000000 0x10000>,
1782                              <0x10000000 0x10000000 0x60000>,
1783                              <0x30000000 0x30000000 0x60000>;
1784
1785                 m4_rproc: m4@10000000 {
1786                         compatible = "st,stm32mp1-m4";
1787                         reg = <0x10000000 0x40000>,
1788                               <0x30000000 0x40000>,
1789                               <0x38000000 0x10000>;
1790                         resets = <&rcc MCU_R>;
1791                         st,syscfg-holdboot = <&rcc 0x10C 0x1>;
1792                         st,syscfg-tz = <&rcc 0x000 0x1>;
1793                         st,syscfg-pdds = <&pwr_mcu 0x0 0x1>;
1794                         st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>;
1795                         st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>;
1796                         status = "disabled";
1797                 };
1798         };
1799 };