arch/arm/dts/stm32mp151.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /*
   3  * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
   4  * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
   5  */
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/stm32mp1-clks.h>
   8 #include <dt-bindings/reset/stm32mp1-resets.h>
   9
  10 / {
  11         #address-cells = <1>;
  12         #size-cells = <1>;
  13
  14         cpus {
  15                 #address-cells = <1>;
  16                 #size-cells = <0>;
  17
  18                 cpu0: cpu@0 {
  19                         compatible = "arm,cortex-a7";
  20                         clock-frequency = <650000000>;
  21                         device_type = "cpu";
  22                         reg = <0>;
  23                         operating-points-v2 = <&cpu0_opp_table>;
  24                         nvmem-cells = <&part_number_otp>;
  25                         nvmem-cell-names = "part_number";
  26                 };
  27         };
  28
  29         cpu0_opp_table: cpu0-opp-table {
  30                 compatible = "operating-points-v2";
  31                 opp-shared;
  32                 opp-650000000 {
  33                         opp-hz = /bits/ 64 <650000000>;
  34                         opp-microvolt = <1200000>;
  35                         opp-supported-hw = <0x1>;
  36                 };
  37                 opp-800000000 {
  38                         opp-hz = /bits/ 64 <800000000>;
  39                         opp-microvolt = <1350000>;
  40                         opp-supported-hw = <0x2>;
  41                 };
  42         };
  43
  44         psci {
  45                 compatible = "arm,psci-1.0";
  46                 method = "smc";
  47         };
  48
  49         intc: interrupt-controller@a0021000 {
  50                 compatible = "arm,cortex-a7-gic";
  51                 #interrupt-cells = <3>;
  52                 interrupt-controller;
  53                 reg = <0xa0021000 0x1000>,
  54                       <0xa0022000 0x2000>;
  55         };
  56
  57         timer {
  58                 compatible = "arm,armv7-timer";
  59                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  60                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  61                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  62                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  63                 interrupt-parent = <&intc>;
  64         };
  65
  66         clocks {
  67                 clk_hse: clk-hse {
  68                         #clock-cells = <0>;
  69                         compatible = "fixed-clock";
  70                         clock-frequency = <24000000>;
  71                 };
  72
  73                 clk_hsi: clk-hsi {
  74                         #clock-cells = <0>;
  75                         compatible = "fixed-clock";
  76                         clock-frequency = <64000000>;
  77                 };
  78
  79                 clk_lse: clk-lse {
  80                         #clock-cells = <0>;
  81                         compatible = "fixed-clock";
  82                         clock-frequency = <32768>;
  83                 };
  84
  85                 clk_lsi: clk-lsi {
  86                         #clock-cells = <0>;
  87                         compatible = "fixed-clock";
  88                         clock-frequency = <32000>;
  89                 };
  90
  91                 clk_csi: clk-csi {
  92                         #clock-cells = <0>;
  93                         compatible = "fixed-clock";
  94                         clock-frequency = <4000000>;
  95                 };
  96         };
  97
  98         thermal-zones {
  99                 cpu_thermal: cpu-thermal {
 100                         polling-delay-passive = <0>;
 101                         polling-delay = <0>;
 102                         thermal-sensors = <&dts>;
 103
 104                         trips {
 105                                 cpu_alert1: cpu-alert1 {
 106                                         temperature = <85000>;
 107                                         hysteresis = <0>;
 108                                         type = "passive";
 109                                 };
 110
 111                                 cpu-crit {
 112                                         temperature = <120000>;
 113                                         hysteresis = <0>;
 114                                         type = "critical";
 115                                 };
 116                         };
 117
 118                         cooling-maps {
 119                         };
 120                 };
 121         };
 122
 123         booster: regulator-booster {
 124                 compatible = "st,stm32mp1-booster";
 125                 st,syscfg = <&syscfg>;
 126                 status = "disabled";
 127         };
 128
 129         soc {
 130                 compatible = "simple-bus";
 131                 #address-cells = <1>;
 132                 #size-cells = <1>;
 133                 interrupt-parent = <&intc>;
 134                 ranges;
 135
 136                 timers2: timer@40000000 {
 137                         #address-cells = <1>;
 138                         #size-cells = <0>;
 139                         compatible = "st,stm32-timers";
 140                         reg = <0x40000000 0x400>;
 141                         clocks = <&rcc TIM2_K>;
 142                         clock-names = "int";
 143                         dmas = <&dmamux1 18 0x400 0x1>,
 144                                <&dmamux1 19 0x400 0x1>,
 145                                <&dmamux1 20 0x400 0x1>,
 146                                <&dmamux1 21 0x400 0x1>,
 147                                <&dmamux1 22 0x400 0x1>;
 148                         dma-names = "ch1", "ch2", "ch3", "ch4", "up";
 149                         status = "disabled";
 150
 151                         pwm {
 152                                 compatible = "st,stm32-pwm";
 153                                 #pwm-cells = <3>;
 154                                 status = "disabled";
 155                         };
 156
 157                         timer@1 {
 158                                 compatible = "st,stm32h7-timer-trigger";
 159                                 reg = <1>;
 160                                 status = "disabled";
 161                         };
 162
 163                         counter {
 164                                 compatible = "st,stm32-timer-counter";
 165                                 status = "disabled";
 166                         };
 167                 };
 168
 169                 timers3: timer@40001000 {
 170                         #address-cells = <1>;
 171                         #size-cells = <0>;
 172                         compatible = "st,stm32-timers";
 173                         reg = <0x40001000 0x400>;
 174                         clocks = <&rcc TIM3_K>;
 175                         clock-names = "int";
 176                         dmas = <&dmamux1 23 0x400 0x1>,
 177                                <&dmamux1 24 0x400 0x1>,
 178                                <&dmamux1 25 0x400 0x1>,
 179                                <&dmamux1 26 0x400 0x1>,
 180                                <&dmamux1 27 0x400 0x1>,
 181                                <&dmamux1 28 0x400 0x1>;
 182                         dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
 183                         status = "disabled";
 184
 185                         pwm {
 186                                 compatible = "st,stm32-pwm";
 187                                 #pwm-cells = <3>;
 188                                 status = "disabled";
 189                         };
 190
 191                         timer@2 {
 192                                 compatible = "st,stm32h7-timer-trigger";
 193                                 reg = <2>;
 194                                 status = "disabled";
 195                         };
 196
 197                         counter {
 198                                 compatible = "st,stm32-timer-counter";
 199                                 status = "disabled";
 200                         };
 201                 };
 202
 203                 timers4: timer@40002000 {
 204                         #address-cells = <1>;
 205                         #size-cells = <0>;
 206                         compatible = "st,stm32-timers";
 207                         reg = <0x40002000 0x400>;
 208                         clocks = <&rcc TIM4_K>;
 209                         clock-names = "int";
 210                         dmas = <&dmamux1 29 0x400 0x1>,
 211                                <&dmamux1 30 0x400 0x1>,
 212                                <&dmamux1 31 0x400 0x1>,
 213                                <&dmamux1 32 0x400 0x1>;
 214                         dma-names = "ch1", "ch2", "ch3", "ch4";
 215                         status = "disabled";
 216
 217                         pwm {
 218                                 compatible = "st,stm32-pwm";
 219                                 #pwm-cells = <3>;
 220                                 status = "disabled";
 221                         };
 222
 223                         timer@3 {
 224                                 compatible = "st,stm32h7-timer-trigger";
 225                                 reg = <3>;
 226                                 status = "disabled";
 227                         };
 228
 229                         counter {
 230                                 compatible = "st,stm32-timer-counter";
 231                                 status = "disabled";
 232                         };
 233                 };
 234
 235                 timers5: timer@40003000 {
 236                         #address-cells = <1>;
 237                         #size-cells = <0>;
 238                         compatible = "st,stm32-timers";
 239                         reg = <0x40003000 0x400>;
 240                         clocks = <&rcc TIM5_K>;
 241                         clock-names = "int";
 242                         dmas = <&dmamux1 55 0x400 0x1>,
 243                                <&dmamux1 56 0x400 0x1>,
 244                                <&dmamux1 57 0x400 0x1>,
 245                                <&dmamux1 58 0x400 0x1>,
 246                                <&dmamux1 59 0x400 0x1>,
 247                                <&dmamux1 60 0x400 0x1>;
 248                         dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
 249                         status = "disabled";
 250
 251                         pwm {
 252                                 compatible = "st,stm32-pwm";
 253                                 #pwm-cells = <3>;
 254                                 status = "disabled";
 255                         };
 256
 257                         timer@4 {
 258                                 compatible = "st,stm32h7-timer-trigger";
 259                                 reg = <4>;
 260                                 status = "disabled";
 261                         };
 262
 263                         counter {
 264                                 compatible = "st,stm32-timer-counter";
 265                                 status = "disabled";
 266                         };
 267                 };
 268
 269                 timers6: timer@40004000 {
 270                         #address-cells = <1>;
 271                         #size-cells = <0>;
 272                         compatible = "st,stm32-timers";
 273                         reg = <0x40004000 0x400>;
 274                         clocks = <&rcc TIM6_K>;
 275                         clock-names = "int";
 276                         dmas = <&dmamux1 69 0x400 0x1>;
 277                         dma-names = "up";
 278                         status = "disabled";
 279
 280                         timer@5 {
 281                                 compatible = "st,stm32h7-timer-trigger";
 282                                 reg = <5>;
 283                                 status = "disabled";
 284                         };
 285                 };
 286
 287                 timers7: timer@40005000 {
 288                         #address-cells = <1>;
 289                         #size-cells = <0>;
 290                         compatible = "st,stm32-timers";
 291                         reg = <0x40005000 0x400>;
 292                         clocks = <&rcc TIM7_K>;
 293                         clock-names = "int";
 294                         dmas = <&dmamux1 70 0x400 0x1>;
 295                         dma-names = "up";
 296                         status = "disabled";
 297
 298                         timer@6 {
 299                                 compatible = "st,stm32h7-timer-trigger";
 300                                 reg = <6>;
 301                                 status = "disabled";
 302                         };
 303                 };
 304
 305                 timers12: timer@40006000 {
 306                         #address-cells = <1>;
 307                         #size-cells = <0>;
 308                         compatible = "st,stm32-timers";
 309                         reg = <0x40006000 0x400>;
 310                         clocks = <&rcc TIM12_K>;
 311                         clock-names = "int";
 312                         status = "disabled";
 313
 314                         pwm {
 315                                 compatible = "st,stm32-pwm";
 316                                 #pwm-cells = <3>;
 317                                 status = "disabled";
 318                         };
 319
 320                         timer@11 {
 321                                 compatible = "st,stm32h7-timer-trigger";
 322                                 reg = <11>;
 323                                 status = "disabled";
 324                         };
 325                 };
 326
 327                 timers13: timer@40007000 {
 328                         #address-cells = <1>;
 329                         #size-cells = <0>;
 330                         compatible = "st,stm32-timers";
 331                         reg = <0x40007000 0x400>;
 332                         clocks = <&rcc TIM13_K>;
 333                         clock-names = "int";
 334                         status = "disabled";
 335
 336                         pwm {
 337                                 compatible = "st,stm32-pwm";
 338                                 #pwm-cells = <3>;
 339                                 status = "disabled";
 340                         };
 341
 342                         timer@12 {
 343                                 compatible = "st,stm32h7-timer-trigger";
 344                                 reg = <12>;
 345                                 status = "disabled";
 346                         };
 347                 };
 348
 349                 timers14: timer@40008000 {
 350                         #address-cells = <1>;
 351                         #size-cells = <0>;
 352                         compatible = "st,stm32-timers";
 353                         reg = <0x40008000 0x400>;
 354                         clocks = <&rcc TIM14_K>;
 355                         clock-names = "int";
 356                         status = "disabled";
 357
 358                         pwm {
 359                                 compatible = "st,stm32-pwm";
 360                                 #pwm-cells = <3>;
 361                                 status = "disabled";
 362                         };
 363
 364                         timer@13 {
 365                                 compatible = "st,stm32h7-timer-trigger";
 366                                 reg = <13>;
 367                                 status = "disabled";
 368                         };
 369                 };
 370
 371                 lptimer1: timer@40009000 {
 372                         #address-cells = <1>;
 373                         #size-cells = <0>;
 374                         compatible = "st,stm32-lptimer";
 375                         reg = <0x40009000 0x400>;
 376                         clocks = <&rcc LPTIM1_K>;
 377                         clock-names = "mux";
 378                         status = "disabled";
 379
 380                         pwm {
 381                                 compatible = "st,stm32-pwm-lp";
 382                                 #pwm-cells = <3>;
 383                                 status = "disabled";
 384                         };
 385
 386                         trigger@0 {
 387                                 compatible = "st,stm32-lptimer-trigger";
 388                                 reg = <0>;
 389                                 status = "disabled";
 390                         };
 391
 392                         counter {
 393                                 compatible = "st,stm32-lptimer-counter";
 394                                 status = "disabled";
 395                         };
 396                 };
 397
 398                 spi2: spi@4000b000 {
 399                         #address-cells = <1>;
 400                         #size-cells = <0>;
 401                         compatible = "st,stm32h7-spi";
 402                         reg = <0x4000b000 0x400>;
 403                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 404                         clocks = <&rcc SPI2_K>;
 405                         resets = <&rcc SPI2_R>;
 406                         dmas = <&dmamux1 39 0x400 0x05>,
 407                                <&dmamux1 40 0x400 0x05>;
 408                         dma-names = "rx", "tx";
 409                         status = "disabled";
 410                 };
 411
 412                 i2s2: audio-controller@4000b000 {
 413                         compatible = "st,stm32h7-i2s";
 414                         #sound-dai-cells = <0>;
 415                         reg = <0x4000b000 0x400>;
 416                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 417                         dmas = <&dmamux1 39 0x400 0x01>,
 418                                <&dmamux1 40 0x400 0x01>;
 419                         dma-names = "rx", "tx";
 420                         status = "disabled";
 421                 };
 422
 423                 spi3: spi@4000c000 {
 424                         #address-cells = <1>;
 425                         #size-cells = <0>;
 426                         compatible = "st,stm32h7-spi";
 427                         reg = <0x4000c000 0x400>;
 428                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 429                         clocks = <&rcc SPI3_K>;
 430                         resets = <&rcc SPI3_R>;
 431                         dmas = <&dmamux1 61 0x400 0x05>,
 432                                <&dmamux1 62 0x400 0x05>;
 433                         dma-names = "rx", "tx";
 434                         status = "disabled";
 435                 };
 436
 437                 i2s3: audio-controller@4000c000 {
 438                         compatible = "st,stm32h7-i2s";
 439                         #sound-dai-cells = <0>;
 440                         reg = <0x4000c000 0x400>;
 441                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 442                         dmas = <&dmamux1 61 0x400 0x01>,
 443                                <&dmamux1 62 0x400 0x01>;
 444                         dma-names = "rx", "tx";
 445                         status = "disabled";
 446                 };
 447
 448                 spdifrx: audio-controller@4000d000 {
 449                         compatible = "st,stm32h7-spdifrx";
 450                         #sound-dai-cells = <0>;
 451                         reg = <0x4000d000 0x400>;
 452                         clocks = <&rcc SPDIF_K>;
 453                         clock-names = "kclk";
 454                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 455                         dmas = <&dmamux1 93 0x400 0x01>,
 456                                <&dmamux1 94 0x400 0x01>;
 457                         dma-names = "rx", "rx-ctrl";
 458                         status = "disabled";
 459                 };
 460
 461                 usart2: serial@4000e000 {
 462                         compatible = "st,stm32h7-uart";
 463                         reg = <0x4000e000 0x400>;
 464                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 465                         clocks = <&rcc USART2_K>;
 466                         status = "disabled";
 467                 };
 468
 469                 usart3: serial@4000f000 {
 470                         compatible = "st,stm32h7-uart";
 471                         reg = <0x4000f000 0x400>;
 472                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 473                         clocks = <&rcc USART3_K>;
 474                         status = "disabled";
 475                 };
 476
 477                 uart4: serial@40010000 {
 478                         compatible = "st,stm32h7-uart";
 479                         reg = <0x40010000 0x400>;
 480                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 481                         clocks = <&rcc UART4_K>;
 482                         status = "disabled";
 483                 };
 484
 485                 uart5: serial@40011000 {
 486                         compatible = "st,stm32h7-uart";
 487                         reg = <0x40011000 0x400>;
 488                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 489                         clocks = <&rcc UART5_K>;
 490                         status = "disabled";
 491                 };
 492
 493                 i2c1: i2c@40012000 {
 494                         compatible = "st,stm32mp15-i2c";
 495                         reg = <0x40012000 0x400>;
 496                         interrupt-names = "event", "error";
 497                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
 498                                      <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 499                         clocks = <&rcc I2C1_K>;
 500                         resets = <&rcc I2C1_R>;
 501                         #address-cells = <1>;
 502                         #size-cells = <0>;
 503                         st,syscfg-fmp = <&syscfg 0x4 0x1>;
 504                         wakeup-source;
 505                         status = "disabled";
 506                 };
 507
 508                 i2c2: i2c@40013000 {
 509                         compatible = "st,stm32mp15-i2c";
 510                         reg = <0x40013000 0x400>;
 511                         interrupt-names = "event", "error";
 512                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 513                                      <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 514                         clocks = <&rcc I2C2_K>;
 515                         resets = <&rcc I2C2_R>;
 516                         #address-cells = <1>;
 517                         #size-cells = <0>;
 518                         st,syscfg-fmp = <&syscfg 0x4 0x2>;
 519                         wakeup-source;
 520                         status = "disabled";
 521                 };
 522
 523                 i2c3: i2c@40014000 {
 524                         compatible = "st,stm32mp15-i2c";
 525                         reg = <0x40014000 0x400>;
 526                         interrupt-names = "event", "error";
 527                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 528                                      <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 529                         clocks = <&rcc I2C3_K>;
 530                         resets = <&rcc I2C3_R>;
 531                         #address-cells = <1>;
 532                         #size-cells = <0>;
 533                         st,syscfg-fmp = <&syscfg 0x4 0x4>;
 534                         wakeup-source;
 535                         status = "disabled";
 536                 };
 537
 538                 i2c5: i2c@40015000 {
 539                         compatible = "st,stm32mp15-i2c";
 540                         reg = <0x40015000 0x400>;
 541                         interrupt-names = "event", "error";
 542                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 543                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 544                         clocks = <&rcc I2C5_K>;
 545                         resets = <&rcc I2C5_R>;
 546                         #address-cells = <1>;
 547                         #size-cells = <0>;
 548                         st,syscfg-fmp = <&syscfg 0x4 0x10>;
 549                         wakeup-source;
 550                         status = "disabled";
 551                 };
 552
 553                 cec: cec@40016000 {
 554                         compatible = "st,stm32-cec";
 555                         reg = <0x40016000 0x400>;
 556                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 557                         clocks = <&rcc CEC_K>, <&clk_lse>;
 558                         clock-names = "cec", "hdmi-cec";
 559                         status = "disabled";
 560                 };
 561
 562                 dac: dac@40017000 {
 563                         compatible = "st,stm32h7-dac-core";
 564                         reg = <0x40017000 0x400>;
 565                         clocks = <&rcc DAC12>;
 566                         clock-names = "pclk";
 567                         #address-cells = <1>;
 568                         #size-cells = <0>;
 569                         status = "disabled";
 570
 571                         dac1: dac@1 {
 572                                 compatible = "st,stm32-dac";
 573                                 #io-channel-cells = <1>;
 574                                 reg = <1>;
 575                                 status = "disabled";
 576                         };
 577
 578                         dac2: dac@2 {
 579                                 compatible = "st,stm32-dac";
 580                                 #io-channel-cells = <1>;
 581                                 reg = <2>;
 582                                 status = "disabled";
 583                         };
 584                 };
 585
 586                 uart7: serial@40018000 {
 587                         compatible = "st,stm32h7-uart";
 588                         reg = <0x40018000 0x400>;
 589                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 590                         clocks = <&rcc UART7_K>;
 591                         status = "disabled";
 592                 };
 593
 594                 uart8: serial@40019000 {
 595                         compatible = "st,stm32h7-uart";
 596                         reg = <0x40019000 0x400>;
 597                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 598                         clocks = <&rcc UART8_K>;
 599                         status = "disabled";
 600                 };
 601
 602                 timers1: timer@44000000 {
 603                         #address-cells = <1>;
 604                         #size-cells = <0>;
 605                         compatible = "st,stm32-timers";
 606                         reg = <0x44000000 0x400>;
 607                         clocks = <&rcc TIM1_K>;
 608                         clock-names = "int";
 609                         dmas = <&dmamux1 11 0x400 0x1>,
 610                                <&dmamux1 12 0x400 0x1>,
 611                                <&dmamux1 13 0x400 0x1>,
 612                                <&dmamux1 14 0x400 0x1>,
 613                                <&dmamux1 15 0x400 0x1>,
 614                                <&dmamux1 16 0x400 0x1>,
 615                                <&dmamux1 17 0x400 0x1>;
 616                         dma-names = "ch1", "ch2", "ch3", "ch4",
 617                                     "up", "trig", "com";
 618                         status = "disabled";
 619
 620                         pwm {
 621                                 compatible = "st,stm32-pwm";
 622                                 #pwm-cells = <3>;
 623                                 status = "disabled";
 624                         };
 625
 626                         timer@0 {
 627                                 compatible = "st,stm32h7-timer-trigger";
 628                                 reg = <0>;
 629                                 status = "disabled";
 630                         };
 631
 632                         counter {
 633                                 compatible = "st,stm32-timer-counter";
 634                                 status = "disabled";
 635                         };
 636                 };
 637
 638                 timers8: timer@44001000 {
 639                         #address-cells = <1>;
 640                         #size-cells = <0>;
 641                         compatible = "st,stm32-timers";
 642                         reg = <0x44001000 0x400>;
 643                         clocks = <&rcc TIM8_K>;
 644                         clock-names = "int";
 645                         dmas = <&dmamux1 47 0x400 0x1>,
 646                                <&dmamux1 48 0x400 0x1>,
 647                                <&dmamux1 49 0x400 0x1>,
 648                                <&dmamux1 50 0x400 0x1>,
 649                                <&dmamux1 51 0x400 0x1>,
 650                                <&dmamux1 52 0x400 0x1>,
 651                                <&dmamux1 53 0x400 0x1>;
 652                         dma-names = "ch1", "ch2", "ch3", "ch4",
 653                                     "up", "trig", "com";
 654                         status = "disabled";
 655
 656                         pwm {
 657                                 compatible = "st,stm32-pwm";
 658                                 #pwm-cells = <3>;
 659                                 status = "disabled";
 660                         };
 661
 662                         timer@7 {
 663                                 compatible = "st,stm32h7-timer-trigger";
 664                                 reg = <7>;
 665                                 status = "disabled";
 666                         };
 667
 668                         counter {
 669                                 compatible = "st,stm32-timer-counter";
 670                                 status = "disabled";
 671                         };
 672                 };
 673
 674                 usart6: serial@44003000 {
 675                         compatible = "st,stm32h7-uart";
 676                         reg = <0x44003000 0x400>;
 677                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 678                         clocks = <&rcc USART6_K>;
 679                         status = "disabled";
 680                 };
 681
 682                 spi1: spi@44004000 {
 683                         #address-cells = <1>;
 684                         #size-cells = <0>;
 685                         compatible = "st,stm32h7-spi";
 686                         reg = <0x44004000 0x400>;
 687                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 688                         clocks = <&rcc SPI1_K>;
 689                         resets = <&rcc SPI1_R>;
 690                         dmas = <&dmamux1 37 0x400 0x05>,
 691                                <&dmamux1 38 0x400 0x05>;
 692                         dma-names = "rx", "tx";
 693                         status = "disabled";
 694                 };
 695
 696                 i2s1: audio-controller@44004000 {
 697                         compatible = "st,stm32h7-i2s";
 698                         #sound-dai-cells = <0>;
 699                         reg = <0x44004000 0x400>;
 700                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 701                         dmas = <&dmamux1 37 0x400 0x01>,
 702                                <&dmamux1 38 0x400 0x01>;
 703                         dma-names = "rx", "tx";
 704                         status = "disabled";
 705                 };
 706
 707                 spi4: spi@44005000 {
 708                         #address-cells = <1>;
 709                         #size-cells = <0>;
 710                         compatible = "st,stm32h7-spi";
 711                         reg = <0x44005000 0x400>;
 712                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 713                         clocks = <&rcc SPI4_K>;
 714                         resets = <&rcc SPI4_R>;
 715                         dmas = <&dmamux1 83 0x400 0x05>,
 716                                <&dmamux1 84 0x400 0x05>;
 717                         dma-names = "rx", "tx";
 718                         status = "disabled";
 719                 };
 720
 721                 timers15: timer@44006000 {
 722                         #address-cells = <1>;
 723                         #size-cells = <0>;
 724                         compatible = "st,stm32-timers";
 725                         reg = <0x44006000 0x400>;
 726                         clocks = <&rcc TIM15_K>;
 727                         clock-names = "int";
 728                         dmas = <&dmamux1 105 0x400 0x1>,
 729                                <&dmamux1 106 0x400 0x1>,
 730                                <&dmamux1 107 0x400 0x1>,
 731                                <&dmamux1 108 0x400 0x1>;
 732                         dma-names = "ch1", "up", "trig", "com";
 733                         status = "disabled";
 734
 735                         pwm {
 736                                 compatible = "st,stm32-pwm";
 737                                 #pwm-cells = <3>;
 738                                 status = "disabled";
 739                         };
 740
 741                         timer@14 {
 742                                 compatible = "st,stm32h7-timer-trigger";
 743                                 reg = <14>;
 744                                 status = "disabled";
 745                         };
 746                 };
 747
 748                 timers16: timer@44007000 {
 749                         #address-cells = <1>;
 750                         #size-cells = <0>;
 751                         compatible = "st,stm32-timers";
 752                         reg = <0x44007000 0x400>;
 753                         clocks = <&rcc TIM16_K>;
 754                         clock-names = "int";
 755                         dmas = <&dmamux1 109 0x400 0x1>,
 756                                <&dmamux1 110 0x400 0x1>;
 757                         dma-names = "ch1", "up";
 758                         status = "disabled";
 759
 760                         pwm {
 761                                 compatible = "st,stm32-pwm";
 762                                 #pwm-cells = <3>;
 763                                 status = "disabled";
 764                         };
 765                         timer@15 {
 766                                 compatible = "st,stm32h7-timer-trigger";
 767                                 reg = <15>;
 768                                 status = "disabled";
 769                         };
 770                 };
 771
 772                 timers17: timer@44008000 {
 773                         #address-cells = <1>;
 774                         #size-cells = <0>;
 775                         compatible = "st,stm32-timers";
 776                         reg = <0x44008000 0x400>;
 777                         clocks = <&rcc TIM17_K>;
 778                         clock-names = "int";
 779                         dmas = <&dmamux1 111 0x400 0x1>,
 780                                <&dmamux1 112 0x400 0x1>;
 781                         dma-names = "ch1", "up";
 782                         status = "disabled";
 783
 784                         pwm {
 785                                 compatible = "st,stm32-pwm";
 786                                 #pwm-cells = <3>;
 787                                 status = "disabled";
 788                         };
 789
 790                         timer@16 {
 791                                 compatible = "st,stm32h7-timer-trigger";
 792                                 reg = <16>;
 793                                 status = "disabled";
 794                         };
 795                 };
 796
 797                 spi5: spi@44009000 {
 798                         #address-cells = <1>;
 799                         #size-cells = <0>;
 800                         compatible = "st,stm32h7-spi";
 801                         reg = <0x44009000 0x400>;
 802                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 803                         clocks = <&rcc SPI5_K>;
 804                         resets = <&rcc SPI5_R>;
 805                         dmas = <&dmamux1 85 0x400 0x05>,
 806                                <&dmamux1 86 0x400 0x05>;
 807                         dma-names = "rx", "tx";
 808                         status = "disabled";
 809                 };
 810
 811                 sai1: sai@4400a000 {
 812                         compatible = "st,stm32h7-sai";
 813                         #address-cells = <1>;
 814                         #size-cells = <1>;
 815                         ranges = <0 0x4400a000 0x400>;
 816                         reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
 817                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 818                         resets = <&rcc SAI1_R>;
 819                         status = "disabled";
 820
 821                         sai1a: audio-controller@4400a004 {
 822                                 #sound-dai-cells = <0>;
 823
 824                                 compatible = "st,stm32-sai-sub-a";
 825                                 reg = <0x4 0x1c>;
 826                                 clocks = <&rcc SAI1_K>;
 827                                 clock-names = "sai_ck";
 828                                 dmas = <&dmamux1 87 0x400 0x01>;
 829                                 status = "disabled";
 830                         };
 831
 832                         sai1b: audio-controller@4400a024 {
 833                                 #sound-dai-cells = <0>;
 834                                 compatible = "st,stm32-sai-sub-b";
 835                                 reg = <0x24 0x1c>;
 836                                 clocks = <&rcc SAI1_K>;
 837                                 clock-names = "sai_ck";
 838                                 dmas = <&dmamux1 88 0x400 0x01>;
 839                                 status = "disabled";
 840                         };
 841                 };
 842
 843                 sai2: sai@4400b000 {
 844                         compatible = "st,stm32h7-sai";
 845                         #address-cells = <1>;
 846                         #size-cells = <1>;
 847                         ranges = <0 0x4400b000 0x400>;
 848                         reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
 849                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 850                         resets = <&rcc SAI2_R>;
 851                         status = "disabled";
 852
 853                         sai2a: audio-controller@4400b004 {
 854                                 #sound-dai-cells = <0>;
 855                                 compatible = "st,stm32-sai-sub-a";
 856                                 reg = <0x4 0x1c>;
 857                                 clocks = <&rcc SAI2_K>;
 858                                 clock-names = "sai_ck";
 859                                 dmas = <&dmamux1 89 0x400 0x01>;
 860                                 status = "disabled";
 861                         };
 862
 863                         sai2b: audio-controller@4400b024 {
 864                                 #sound-dai-cells = <0>;
 865                                 compatible = "st,stm32-sai-sub-b";
 866                                 reg = <0x24 0x1c>;
 867                                 clocks = <&rcc SAI2_K>;
 868                                 clock-names = "sai_ck";
 869                                 dmas = <&dmamux1 90 0x400 0x01>;
 870                                 status = "disabled";
 871                         };
 872                 };
 873
 874                 sai3: sai@4400c000 {
 875                         compatible = "st,stm32h7-sai";
 876                         #address-cells = <1>;
 877                         #size-cells = <1>;
 878                         ranges = <0 0x4400c000 0x400>;
 879                         reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
 880                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 881                         resets = <&rcc SAI3_R>;
 882                         status = "disabled";
 883
 884                         sai3a: audio-controller@4400c004 {
 885                                 #sound-dai-cells = <0>;
 886                                 compatible = "st,stm32-sai-sub-a";
 887                                 reg = <0x04 0x1c>;
 888                                 clocks = <&rcc SAI3_K>;
 889                                 clock-names = "sai_ck";
 890                                 dmas = <&dmamux1 113 0x400 0x01>;
 891                                 status = "disabled";
 892                         };
 893
 894                         sai3b: audio-controller@4400c024 {
 895                                 #sound-dai-cells = <0>;
 896                                 compatible = "st,stm32-sai-sub-b";
 897                                 reg = <0x24 0x1c>;
 898                                 clocks = <&rcc SAI3_K>;
 899                                 clock-names = "sai_ck";
 900                                 dmas = <&dmamux1 114 0x400 0x01>;
 901                                 status = "disabled";
 902                         };
 903                 };
 904
 905                 dfsdm: dfsdm@4400d000 {
 906                         compatible = "st,stm32mp1-dfsdm";
 907                         reg = <0x4400d000 0x800>;
 908                         clocks = <&rcc DFSDM_K>;
 909                         clock-names = "dfsdm";
 910                         #address-cells = <1>;
 911                         #size-cells = <0>;
 912                         status = "disabled";
 913
 914                         dfsdm0: filter@0 {
 915                                 compatible = "st,stm32-dfsdm-adc";
 916                                 #io-channel-cells = <1>;
 917                                 reg = <0>;
 918                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 919                                 dmas = <&dmamux1 101 0x400 0x01>;
 920                                 dma-names = "rx";
 921                                 status = "disabled";
 922                         };
 923
 924                         dfsdm1: filter@1 {
 925                                 compatible = "st,stm32-dfsdm-adc";
 926                                 #io-channel-cells = <1>;
 927                                 reg = <1>;
 928                                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 929                                 dmas = <&dmamux1 102 0x400 0x01>;
 930                                 dma-names = "rx";
 931                                 status = "disabled";
 932                         };
 933
 934                         dfsdm2: filter@2 {
 935                                 compatible = "st,stm32-dfsdm-adc";
 936                                 #io-channel-cells = <1>;
 937                                 reg = <2>;
 938                                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 939                                 dmas = <&dmamux1 103 0x400 0x01>;
 940                                 dma-names = "rx";
 941                                 status = "disabled";
 942                         };
 943
 944                         dfsdm3: filter@3 {
 945                                 compatible = "st,stm32-dfsdm-adc";
 946                                 #io-channel-cells = <1>;
 947                                 reg = <3>;
 948                                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 949                                 dmas = <&dmamux1 104 0x400 0x01>;
 950                                 dma-names = "rx";
 951                                 status = "disabled";
 952                         };
 953
 954                         dfsdm4: filter@4 {
 955                                 compatible = "st,stm32-dfsdm-adc";
 956                                 #io-channel-cells = <1>;
 957                                 reg = <4>;
 958                                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 959                                 dmas = <&dmamux1 91 0x400 0x01>;
 960                                 dma-names = "rx";
 961                                 status = "disabled";
 962                         };
 963
 964                         dfsdm5: filter@5 {
 965                                 compatible = "st,stm32-dfsdm-adc";
 966                                 #io-channel-cells = <1>;
 967                                 reg = <5>;
 968                                 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 969                                 dmas = <&dmamux1 92 0x400 0x01>;
 970                                 dma-names = "rx";
 971                                 status = "disabled";
 972                         };
 973                 };
 974
 975                 dma1: dma-controller@48000000 {
 976                         compatible = "st,stm32-dma";
 977                         reg = <0x48000000 0x400>;
 978                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 979                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 980                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 981                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 982                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 983                                      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 984                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 985                                      <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 986                         clocks = <&rcc DMA1>;
 987                         resets = <&rcc DMA1_R>;
 988                         #dma-cells = <4>;
 989                         st,mem2mem;
 990                         dma-requests = <8>;
 991                 };
 992
 993                 dma2: dma-controller@48001000 {
 994                         compatible = "st,stm32-dma";
 995                         reg = <0x48001000 0x400>;
 996                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
 997                                      <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
 998                                      <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 999                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
1000                                      <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
1001                                      <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
1002                                      <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1003                                      <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1004                         clocks = <&rcc DMA2>;
1005                         resets = <&rcc DMA2_R>;
1006                         #dma-cells = <4>;
1007                         st,mem2mem;
1008                         dma-requests = <8>;
1009                 };
1010
1011                 dmamux1: dma-router@48002000 {
1012                         compatible = "st,stm32h7-dmamux";
1013                         reg = <0x48002000 0x1c>;
1014                         #dma-cells = <3>;
1015                         dma-requests = <128>;
1016                         dma-masters = <&dma1 &dma2>;
1017                         dma-channels = <16>;
1018                         clocks = <&rcc DMAMUX>;
1019                         resets = <&rcc DMAMUX_R>;
1020                 };
1021
1022                 adc: adc@48003000 {
1023                         compatible = "st,stm32mp1-adc-core";
1024                         reg = <0x48003000 0x400>;
1025                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
1026                                      <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1027                         clocks = <&rcc ADC12>, <&rcc ADC12_K>;
1028                         clock-names = "bus", "adc";
1029                         interrupt-controller;
1030                         st,syscfg = <&syscfg>;
1031                         #interrupt-cells = <1>;
1032                         #address-cells = <1>;
1033                         #size-cells = <0>;
1034                         status = "disabled";
1035
1036                         adc1: adc@0 {
1037                                 compatible = "st,stm32mp1-adc";
1038                                 #io-channel-cells = <1>;
1039                                 reg = <0x0>;
1040                                 interrupt-parent = <&adc>;
1041                                 interrupts = <0>;
1042                                 dmas = <&dmamux1 9 0x400 0x01>;
1043                                 dma-names = "rx";
1044                                 status = "disabled";
1045                         };
1046
1047                         adc2: adc@100 {
1048                                 compatible = "st,stm32mp1-adc";
1049                                 #io-channel-cells = <1>;
1050                                 reg = <0x100>;
1051                                 interrupt-parent = <&adc>;
1052                                 interrupts = <1>;
1053                                 dmas = <&dmamux1 10 0x400 0x01>;
1054                                 dma-names = "rx";
1055                                 status = "disabled";
1056                         };
1057                 };
1058
1059                 sdmmc3: sdmmc@48004000 {
1060                         compatible = "arm,pl18x", "arm,primecell";
1061                         arm,primecell-periphid = <0x10153180>;
1062                         reg = <0x48004000 0x400>;
1063                         interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
1064                         interrupt-names = "cmd_irq";
1065                         clocks = <&rcc SDMMC3_K>;
1066                         clock-names = "apb_pclk";
1067                         resets = <&rcc SDMMC3_R>;
1068                         cap-sd-highspeed;
1069                         cap-mmc-highspeed;
1070                         max-frequency = <120000000>;
1071                         status = "disabled";
1072                 };
1073
1074                 usbotg_hs: usb-otg@49000000 {
1075                         compatible = "st,stm32mp15-hsotg", "snps,dwc2";
1076                         reg = <0x49000000 0x10000>;
1077                         clocks = <&rcc USBO_K>;
1078                         clock-names = "otg";
1079                         resets = <&rcc USBO_R>;
1080                         reset-names = "dwc2";
1081                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1082                         g-rx-fifo-size = <256>;
1083                         g-np-tx-fifo-size = <32>;
1084                         g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
1085                         dr_mode = "otg";
1086                         usb33d-supply = <&usb33>;
1087                         status = "disabled";
1088                 };
1089
1090                 hwspinlock: hwspinlock@4c000000 {
1091                         compatible = "st,stm32-hwspinlock";
1092                         #hwlock-cells = <1>;
1093                         reg = <0x4c000000 0x400>;
1094                         clocks = <&rcc HSEM>;
1095                         clock-names = "hwspinlock";
1096                 };
1097
1098                 ipcc: mailbox@4c001000 {
1099                         compatible = "st,stm32mp1-ipcc";
1100                         #mbox-cells = <1>;
1101                         reg = <0x4c001000 0x400>;
1102                         st,proc-id = <0>;
1103                         interrupts-extended =
1104                                 <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1105                                 <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1106                                 <&exti 61 1>;
1107                         interrupt-names = "rx", "tx", "wakeup";
1108                         clocks = <&rcc IPCC>;
1109                         wakeup-source;
1110                         status = "disabled";
1111                 };
1112
1113                 dcmi: dcmi@4c006000 {
1114                         compatible = "st,stm32-dcmi";
1115                         reg = <0x4c006000 0x400>;
1116                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1117                         resets = <&rcc CAMITF_R>;
1118                         clocks = <&rcc DCMI>;
1119                         clock-names = "mclk";
1120                         dmas = <&dmamux1 75 0x400 0x0d>;
1121                         dma-names = "tx";
1122                         status = "disabled";
1123                 };
1124
1125                 rcc: rcc@50000000 {
1126                         compatible = "st,stm32mp1-rcc", "syscon";
1127                         reg = <0x50000000 0x1000>;
1128                         #clock-cells = <1>;
1129                         #reset-cells = <1>;
1130                 };
1131
1132                 pwr_regulators: pwr@50001000 {
1133                         compatible = "st,stm32mp1,pwr-reg";
1134                         reg = <0x50001000 0x10>;
1135
1136                         reg11: reg11 {
1137                                 regulator-name = "reg11";
1138                                 regulator-min-microvolt = <1100000>;
1139                                 regulator-max-microvolt = <1100000>;
1140                         };
1141
1142                         reg18: reg18 {
1143                                 regulator-name = "reg18";
1144                                 regulator-min-microvolt = <1800000>;
1145                                 regulator-max-microvolt = <1800000>;
1146                         };
1147
1148                         usb33: usb33 {
1149                                 regulator-name = "usb33";
1150                                 regulator-min-microvolt = <3300000>;
1151                                 regulator-max-microvolt = <3300000>;
1152                         };
1153                 };
1154
1155                 pwr_mcu: pwr_mcu@50001014 {
1156                         compatible = "st,stm32mp151-pwr-mcu", "syscon";
1157                         reg = <0x50001014 0x4>;
1158                 };
1159
1160                 exti: interrupt-controller@5000d000 {
1161                         compatible = "st,stm32mp1-exti", "syscon";
1162                         interrupt-controller;
1163                         #interrupt-cells = <2>;
1164                         reg = <0x5000d000 0x400>;
1165                 };
1166
1167                 syscfg: syscon@50020000 {
1168                         compatible = "st,stm32mp157-syscfg", "syscon";
1169                         reg = <0x50020000 0x400>;
1170                         clocks = <&rcc SYSCFG>;
1171                 };
1172
1173                 lptimer2: timer@50021000 {
1174                         #address-cells = <1>;
1175                         #size-cells = <0>;
1176                         compatible = "st,stm32-lptimer";
1177                         reg = <0x50021000 0x400>;
1178                         clocks = <&rcc LPTIM2_K>;
1179                         clock-names = "mux";
1180                         status = "disabled";
1181
1182                         pwm {
1183                                 compatible = "st,stm32-pwm-lp";
1184                                 #pwm-cells = <3>;
1185                                 status = "disabled";
1186                         };
1187
1188                         trigger@1 {
1189                                 compatible = "st,stm32-lptimer-trigger";
1190                                 reg = <1>;
1191                                 status = "disabled";
1192                         };
1193
1194                         counter {
1195                                 compatible = "st,stm32-lptimer-counter";
1196                                 status = "disabled";
1197                         };
1198                 };
1199
1200                 lptimer3: timer@50022000 {
1201                         #address-cells = <1>;
1202                         #size-cells = <0>;
1203                         compatible = "st,stm32-lptimer";
1204                         reg = <0x50022000 0x400>;
1205                         clocks = <&rcc LPTIM3_K>;
1206                         clock-names = "mux";
1207                         status = "disabled";
1208
1209                         pwm {
1210                                 compatible = "st,stm32-pwm-lp";
1211                                 #pwm-cells = <3>;
1212                                 status = "disabled";
1213                         };
1214
1215                         trigger@2 {
1216                                 compatible = "st,stm32-lptimer-trigger";
1217                                 reg = <2>;
1218                                 status = "disabled";
1219                         };
1220                 };
1221
1222                 lptimer4: timer@50023000 {
1223                         compatible = "st,stm32-lptimer";
1224                         reg = <0x50023000 0x400>;
1225                         clocks = <&rcc LPTIM4_K>;
1226                         clock-names = "mux";
1227                         status = "disabled";
1228
1229                         pwm {
1230                                 compatible = "st,stm32-pwm-lp";
1231                                 #pwm-cells = <3>;
1232                                 status = "disabled";
1233                         };
1234                 };
1235
1236                 lptimer5: timer@50024000 {
1237                         compatible = "st,stm32-lptimer";
1238                         reg = <0x50024000 0x400>;
1239                         clocks = <&rcc LPTIM5_K>;
1240                         clock-names = "mux";
1241                         status = "disabled";
1242
1243                         pwm {
1244                                 compatible = "st,stm32-pwm-lp";
1245                                 #pwm-cells = <3>;
1246                                 status = "disabled";
1247                         };
1248                 };
1249
1250                 vrefbuf: vrefbuf@50025000 {
1251                         compatible = "st,stm32-vrefbuf";
1252                         reg = <0x50025000 0x8>;
1253                         regulator-min-microvolt = <1500000>;
1254                         regulator-max-microvolt = <2500000>;
1255                         clocks = <&rcc VREF>;
1256                         status = "disabled";
1257                 };
1258
1259                 sai4: sai@50027000 {
1260                         compatible = "st,stm32h7-sai";
1261                         #address-cells = <1>;
1262                         #size-cells = <1>;
1263                         ranges = <0 0x50027000 0x400>;
1264                         reg = <0x50027000 0x4>, <0x500273f0 0x10>;
1265                         interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
1266                         resets = <&rcc SAI4_R>;
1267                         status = "disabled";
1268
1269                         sai4a: audio-controller@50027004 {
1270                                 #sound-dai-cells = <0>;
1271                                 compatible = "st,stm32-sai-sub-a";
1272                                 reg = <0x04 0x1c>;
1273                                 clocks = <&rcc SAI4_K>;
1274                                 clock-names = "sai_ck";
1275                                 dmas = <&dmamux1 99 0x400 0x01>;
1276                                 status = "disabled";
1277                         };
1278
1279                         sai4b: audio-controller@50027024 {
1280                                 #sound-dai-cells = <0>;
1281                                 compatible = "st,stm32-sai-sub-b";
1282                                 reg = <0x24 0x1c>;
1283                                 clocks = <&rcc SAI4_K>;
1284                                 clock-names = "sai_ck";
1285                                 dmas = <&dmamux1 100 0x400 0x01>;
1286                                 status = "disabled";
1287                         };
1288                 };
1289
1290                 dts: thermal@50028000 {
1291                         compatible = "st,stm32-thermal";
1292                         reg = <0x50028000 0x100>;
1293                         interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1294                         clocks = <&rcc TMPSENS>;
1295                         clock-names = "pclk";
1296                         #thermal-sensor-cells = <0>;
1297                         status = "disabled";
1298                 };
1299
1300                 hash1: hash@54002000 {
1301                         compatible = "st,stm32f756-hash";
1302                         reg = <0x54002000 0x400>;
1303                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1304                         clocks = <&rcc HASH1>;
1305                         resets = <&rcc HASH1_R>;
1306                         dmas = <&mdma1 31 0x10 0x1000A02 0x0 0x0>;
1307                         dma-names = "in";
1308                         dma-maxburst = <2>;
1309                         status = "disabled";
1310                 };
1311
1312                 rng1: rng@54003000 {
1313                         compatible = "st,stm32-rng";
1314                         reg = <0x54003000 0x400>;
1315                         clocks = <&rcc RNG1_K>;
1316                         resets = <&rcc RNG1_R>;
1317                         status = "disabled";
1318                 };
1319
1320                 mdma1: dma-controller@58000000 {
1321                         compatible = "st,stm32h7-mdma";
1322                         reg = <0x58000000 0x1000>;
1323                         interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1324                         clocks = <&rcc MDMA>;
1325                         resets = <&rcc MDMA_R>;
1326                         #dma-cells = <5>;
1327                         dma-channels = <32>;
1328                         dma-requests = <48>;
1329                 };
1330
1331                 fmc: memory-controller@58002000 {
1332                         #address-cells = <2>;
1333                         #size-cells = <1>;
1334                         compatible = "st,stm32mp1-fmc2-ebi";
1335                         reg = <0x58002000 0x1000>;
1336                         clocks = <&rcc FMC_K>;
1337                         resets = <&rcc FMC_R>;
1338                         status = "disabled";
1339
1340                         ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
1341                                  <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
1342                                  <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
1343                                  <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
1344                                  <4 0 0x80000000 0x10000000>; /* NAND */
1345
1346                         nand-controller@4,0 {
1347                                 #address-cells = <1>;
1348                                 #size-cells = <0>;
1349                                 compatible = "st,stm32mp1-fmc2-nfc";
1350                                 reg = <4 0x00000000 0x1000>,
1351                                       <4 0x08010000 0x1000>,
1352                                       <4 0x08020000 0x1000>,
1353                                       <4 0x01000000 0x1000>,
1354                                       <4 0x09010000 0x1000>,
1355                                       <4 0x09020000 0x1000>;
1356                                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1357                                 dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
1358                                        <&mdma1 20 0x2 0x12000a08 0x0 0x0>,
1359                                        <&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
1360                                 dma-names = "tx", "rx", "ecc";
1361                                 status = "disabled";
1362                         };
1363                 };
1364
1365                 qspi: spi@58003000 {
1366                         compatible = "st,stm32f469-qspi";
1367                         reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
1368                         reg-names = "qspi", "qspi_mm";
1369                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
1370                         dmas = <&mdma1 22 0x10 0x100002 0x0 0x0>,
1371                                <&mdma1 22 0x10 0x100008 0x0 0x0>;
1372                         dma-names = "tx", "rx";
1373                         clocks = <&rcc QSPI_K>;
1374                         resets = <&rcc QSPI_R>;
1375                         #address-cells = <1>;
1376                         #size-cells = <0>;
1377                         status = "disabled";
1378                 };
1379
1380                 sdmmc1: sdmmc@58005000 {
1381                         compatible = "arm,pl18x", "arm,primecell";
1382                         arm,primecell-periphid = <0x10153180>;
1383                         reg = <0x58005000 0x1000>;
1384                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1385                         interrupt-names = "cmd_irq";
1386                         clocks = <&rcc SDMMC1_K>;
1387                         clock-names = "apb_pclk";
1388                         resets = <&rcc SDMMC1_R>;
1389                         cap-sd-highspeed;
1390                         cap-mmc-highspeed;
1391                         max-frequency = <120000000>;
1392                         status = "disabled";
1393                 };
1394
1395                 sdmmc2: sdmmc@58007000 {
1396                         compatible = "arm,pl18x", "arm,primecell";
1397                         arm,primecell-periphid = <0x10153180>;
1398                         reg = <0x58007000 0x1000>;
1399                         interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
1400                         interrupt-names = "cmd_irq";
1401                         clocks = <&rcc SDMMC2_K>;
1402                         clock-names = "apb_pclk";
1403                         resets = <&rcc SDMMC2_R>;
1404                         cap-sd-highspeed;
1405                         cap-mmc-highspeed;
1406                         max-frequency = <120000000>;
1407                         status = "disabled";
1408                 };
1409
1410                 crc1: crc@58009000 {
1411                         compatible = "st,stm32f7-crc";
1412                         reg = <0x58009000 0x400>;
1413                         clocks = <&rcc CRC1>;
1414                         status = "disabled";
1415                 };
1416
1417                 stmmac_axi_config_0: stmmac-axi-config {
1418                         snps,wr_osr_lmt = <0x7>;
1419                         snps,rd_osr_lmt = <0x7>;
1420                         snps,blen = <0 0 0 0 16 8 4>;
1421                 };
1422
1423                 ethernet0: ethernet@5800a000 {
1424                         compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
1425                         reg = <0x5800a000 0x2000>;
1426                         reg-names = "stmmaceth";
1427                         interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1428                         interrupt-names = "macirq";
1429                         clock-names = "stmmaceth",
1430                                       "mac-clk-tx",
1431                                       "mac-clk-rx",
1432                                       "eth-ck",
1433                                       "ethstp";
1434                         clocks = <&rcc ETHMAC>,
1435                                  <&rcc ETHTX>,
1436                                  <&rcc ETHRX>,
1437                                  <&rcc ETHCK_K>,
1438                                  <&rcc ETHSTP>;
1439                         st,syscon = <&syscfg 0x4>;
1440                         snps,mixed-burst;
1441                         snps,pbl = <2>;
1442                         snps,en-tx-lpi-clockgating;
1443                         snps,axi-config = <&stmmac_axi_config_0>;
1444                         snps,tso;
1445                         status = "disabled";
1446                 };
1447
1448                 usbh_ohci: usbh-ohci@5800c000 {
1449                         compatible = "generic-ohci";
1450                         reg = <0x5800c000 0x1000>;
1451                         clocks = <&rcc USBH>;
1452                         resets = <&rcc USBH_R>;
1453                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1454                         status = "disabled";
1455                 };
1456
1457                 usbh_ehci: usbh-ehci@5800d000 {
1458                         compatible = "generic-ehci";
1459                         reg = <0x5800d000 0x1000>;
1460                         clocks = <&rcc USBH>;
1461                         resets = <&rcc USBH_R>;
1462                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1463                         companion = <&usbh_ohci>;
1464                         status = "disabled";
1465                 };
1466
1467                 ltdc: display-controller@5a001000 {
1468                         compatible = "st,stm32-ltdc";
1469                         reg = <0x5a001000 0x400>;
1470                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1471                                      <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1472                         clocks = <&rcc LTDC_PX>;
1473                         clock-names = "lcd";
1474                         resets = <&rcc LTDC_R>;
1475                         status = "disabled";
1476
1477                         port {
1478                                 #address-cells = <1>;
1479                                 #size-cells = <0>;
1480                         };
1481                 };
1482
1483                 iwdg2: watchdog@5a002000 {
1484                         compatible = "st,stm32mp1-iwdg";
1485                         reg = <0x5a002000 0x400>;
1486                         clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
1487                         clock-names = "pclk", "lsi";
1488                         status = "disabled";
1489                 };
1490
1491                 usbphyc: usbphyc@5a006000 {
1492                         #address-cells = <1>;
1493                         #size-cells = <0>;
1494                         compatible = "st,stm32mp1-usbphyc";
1495                         reg = <0x5a006000 0x1000>;
1496                         clocks = <&rcc USBPHY_K>;
1497                         resets = <&rcc USBPHY_R>;
1498                         vdda1v1-supply = <&reg11>;
1499                         vdda1v8-supply = <&reg18>;
1500                         status = "disabled";
1501
1502                         usbphyc_port0: usb-phy@0 {
1503                                 #phy-cells = <0>;
1504                                 reg = <0>;
1505                         };
1506
1507                         usbphyc_port1: usb-phy@1 {
1508                                 #phy-cells = <1>;
1509                                 reg = <1>;
1510                         };
1511                 };
1512
1513                 usart1: serial@5c000000 {
1514                         compatible = "st,stm32h7-uart";
1515                         reg = <0x5c000000 0x400>;
1516                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1517                         clocks = <&rcc USART1_K>;
1518                         status = "disabled";
1519                 };
1520
1521                 spi6: spi@5c001000 {
1522                         #address-cells = <1>;
1523                         #size-cells = <0>;
1524                         compatible = "st,stm32h7-spi";
1525                         reg = <0x5c001000 0x400>;
1526                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1527                         clocks = <&rcc SPI6_K>;
1528                         resets = <&rcc SPI6_R>;
1529                         dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
1530                                <&mdma1 35 0x0 0x40002 0x0 0x0>;
1531                         dma-names = "rx", "tx";
1532                         status = "disabled";
1533                 };
1534
1535                 i2c4: i2c@5c002000 {
1536                         compatible = "st,stm32mp15-i2c";
1537                         reg = <0x5c002000 0x400>;
1538                         interrupt-names = "event", "error";
1539                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1540                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1541                         clocks = <&rcc I2C4_K>;
1542                         resets = <&rcc I2C4_R>;
1543                         #address-cells = <1>;
1544                         #size-cells = <0>;
1545                         st,syscfg-fmp = <&syscfg 0x4 0x8>;
1546                         wakeup-source;
1547                         status = "disabled";
1548                 };
1549
1550                 rtc: rtc@5c004000 {
1551                         compatible = "st,stm32mp1-rtc";
1552                         reg = <0x5c004000 0x400>;
1553                         clocks = <&rcc RTCAPB>, <&rcc RTC>;
1554                         clock-names = "pclk", "rtc_ck";
1555                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1556                         status = "disabled";
1557                 };
1558
1559                 bsec: efuse@5c005000 {
1560                         compatible = "st,stm32mp15-bsec";
1561                         reg = <0x5c005000 0x400>;
1562                         #address-cells = <1>;
1563                         #size-cells = <1>;
1564                         part_number_otp: part_number_otp@4 {
1565                                 reg = <0x4 0x1>;
1566                         };
1567                         ts_cal1: calib@5c {
1568                                 reg = <0x5c 0x2>;
1569                         };
1570                         ts_cal2: calib@5e {
1571                                 reg = <0x5e 0x2>;
1572                         };
1573                 };
1574
1575                 i2c6: i2c@5c009000 {
1576                         compatible = "st,stm32mp15-i2c";
1577                         reg = <0x5c009000 0x400>;
1578                         interrupt-names = "event", "error";
1579                         interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1580                                      <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1581                         clocks = <&rcc I2C6_K>;
1582                         resets = <&rcc I2C6_R>;
1583                         #address-cells = <1>;
1584                         #size-cells = <0>;
1585                         st,syscfg-fmp = <&syscfg 0x4 0x20>;
1586                         wakeup-source;
1587                         status = "disabled";
1588                 };
1589
1590                 /*
1591                  * Break node order to solve dependency probe issue between
1592                  * pinctrl and exti.
1593                  */
1594                 pinctrl: pin-controller@50002000 {
1595                         #address-cells = <1>;
1596                         #size-cells = <1>;
1597                         compatible = "st,stm32mp157-pinctrl";
1598                         ranges = <0 0x50002000 0xa400>;
1599                         interrupt-parent = <&exti>;
1600                         st,syscfg = <&exti 0x60 0xff>;
1601                         hwlocks = <&hwspinlock 0>;
1602                         pins-are-numbered;
1603
1604                         gpioa: gpio@50002000 {
1605                                 gpio-controller;
1606                                 #gpio-cells = <2>;
1607                                 interrupt-controller;
1608                                 #interrupt-cells = <2>;
1609                                 reg = <0x0 0x400>;
1610                                 clocks = <&rcc GPIOA>;
1611                                 st,bank-name = "GPIOA";
1612                                 status = "disabled";
1613                         };
1614
1615                         gpiob: gpio@50003000 {
1616                                 gpio-controller;
1617                                 #gpio-cells = <2>;
1618                                 interrupt-controller;
1619                                 #interrupt-cells = <2>;
1620                                 reg = <0x1000 0x400>;
1621                                 clocks = <&rcc GPIOB>;
1622                                 st,bank-name = "GPIOB";
1623                                 status = "disabled";
1624                         };
1625
1626                         gpioc: gpio@50004000 {
1627                                 gpio-controller;
1628                                 #gpio-cells = <2>;
1629                                 interrupt-controller;
1630                                 #interrupt-cells = <2>;
1631                                 reg = <0x2000 0x400>;
1632                                 clocks = <&rcc GPIOC>;
1633                                 st,bank-name = "GPIOC";
1634                                 status = "disabled";
1635                         };
1636
1637                         gpiod: gpio@50005000 {
1638                                 gpio-controller;
1639                                 #gpio-cells = <2>;
1640                                 interrupt-controller;
1641                                 #interrupt-cells = <2>;
1642                                 reg = <0x3000 0x400>;
1643                                 clocks = <&rcc GPIOD>;
1644                                 st,bank-name = "GPIOD";
1645                                 status = "disabled";
1646                         };
1647
1648                         gpioe: gpio@50006000 {
1649                                 gpio-controller;
1650                                 #gpio-cells = <2>;
1651                                 interrupt-controller;
1652                                 #interrupt-cells = <2>;
1653                                 reg = <0x4000 0x400>;
1654                                 clocks = <&rcc GPIOE>;
1655                                 st,bank-name = "GPIOE";
1656                                 status = "disabled";
1657                         };
1658
1659                         gpiof: gpio@50007000 {
1660                                 gpio-controller;
1661                                 #gpio-cells = <2>;
1662                                 interrupt-controller;
1663                                 #interrupt-cells = <2>;
1664                                 reg = <0x5000 0x400>;
1665                                 clocks = <&rcc GPIOF>;
1666                                 st,bank-name = "GPIOF";
1667                                 status = "disabled";
1668                         };
1669
1670                         gpiog: gpio@50008000 {
1671                                 gpio-controller;
1672                                 #gpio-cells = <2>;
1673                                 interrupt-controller;
1674                                 #interrupt-cells = <2>;
1675                                 reg = <0x6000 0x400>;
1676                                 clocks = <&rcc GPIOG>;
1677                                 st,bank-name = "GPIOG";
1678                                 status = "disabled";
1679                         };
1680
1681                         gpioh: gpio@50009000 {
1682                                 gpio-controller;
1683                                 #gpio-cells = <2>;
1684                                 interrupt-controller;
1685                                 #interrupt-cells = <2>;
1686                                 reg = <0x7000 0x400>;
1687                                 clocks = <&rcc GPIOH>;
1688                                 st,bank-name = "GPIOH";
1689                                 status = "disabled";
1690                         };
1691
1692                         gpioi: gpio@5000a000 {
1693                                 gpio-controller;
1694                                 #gpio-cells = <2>;
1695                                 interrupt-controller;
1696                                 #interrupt-cells = <2>;
1697                                 reg = <0x8000 0x400>;
1698                                 clocks = <&rcc GPIOI>;
1699                                 st,bank-name = "GPIOI";
1700                                 status = "disabled";
1701                         };
1702
1703                         gpioj: gpio@5000b000 {
1704                                 gpio-controller;
1705                                 #gpio-cells = <2>;
1706                                 interrupt-controller;
1707                                 #interrupt-cells = <2>;
1708                                 reg = <0x9000 0x400>;
1709                                 clocks = <&rcc GPIOJ>;
1710                                 st,bank-name = "GPIOJ";
1711                                 status = "disabled";
1712                         };
1713
1714                         gpiok: gpio@5000c000 {
1715                                 gpio-controller;
1716                                 #gpio-cells = <2>;
1717                                 interrupt-controller;
1718                                 #interrupt-cells = <2>;
1719                                 reg = <0xa000 0x400>;
1720                                 clocks = <&rcc GPIOK>;
1721                                 st,bank-name = "GPIOK";
1722                                 status = "disabled";
1723                         };
1724                 };
1725
1726                 pinctrl_z: pin-controller-z@54004000 {
1727                         #address-cells = <1>;
1728                         #size-cells = <1>;
1729                         compatible = "st,stm32mp157-z-pinctrl";
1730                         ranges = <0 0x54004000 0x400>;
1731                         pins-are-numbered;
1732                         interrupt-parent = <&exti>;
1733                         st,syscfg = <&exti 0x60 0xff>;
1734                         hwlocks = <&hwspinlock 0>;
1735
1736                         gpioz: gpio@54004000 {
1737                                 gpio-controller;
1738                                 #gpio-cells = <2>;
1739                                 interrupt-controller;
1740                                 #interrupt-cells = <2>;
1741                                 reg = <0 0x400>;
1742                                 clocks = <&rcc GPIOZ>;
1743                                 st,bank-name = "GPIOZ";
1744                                 st,bank-ioport = <11>;
1745                                 status = "disabled";
1746                         };
1747                 };
1748         };
1749
1750         mlahb: ahb {
1751                 compatible = "st,mlahb", "simple-bus";
1752                 #address-cells = <1>;
1753                 #size-cells = <1>;
1754                 ranges;
1755                 dma-ranges = <0x00000000 0x38000000 0x10000>,
1756                              <0x10000000 0x10000000 0x60000>,
1757                              <0x30000000 0x30000000 0x60000>;
1758
1759                 m4_rproc: m4@10000000 {
1760                         compatible = "st,stm32mp1-m4";
1761                         reg = <0x10000000 0x40000>,
1762                               <0x30000000 0x40000>,
1763                               <0x38000000 0x10000>;
1764                         resets = <&rcc MCU_R>;
1765                         st,syscfg-holdboot = <&rcc 0x10C 0x1>;
1766                         st,syscfg-tz = <&rcc 0x000 0x1>;
1767                         st,syscfg-pdds = <&pwr_mcu 0x0 0x1>;
1768                         status = "disabled";
1769                 };
1770         };
1771 };