arch/arm/dts/stm32mp15-u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright : STMicroelectronics 2018
   4  */
   5
   6 / {
   7         aliases {
   8                 gpio0 = &gpioa;
   9                 gpio1 = &gpiob;
  10                 gpio2 = &gpioc;
  11                 gpio3 = &gpiod;
  12                 gpio4 = &gpioe;
  13                 gpio5 = &gpiof;
  14                 gpio6 = &gpiog;
  15                 gpio7 = &gpioh;
  16                 gpio8 = &gpioi;
  17                 gpio9 = &gpioj;
  18                 gpio10 = &gpiok;
  19                 gpio25 = &gpioz;
  20                 pinctrl0 = &pinctrl;
  21                 pinctrl1 = &pinctrl_z;
  22         };
  23
  24         clocks {
  25                 u-boot,dm-pre-reloc;
  26         };
  27
  28         /* need PSCI for sysreset during board_f */
  29         psci {
  30                 u-boot,dm-pre-proper;
  31         };
  32
  33         reboot {
  34                 u-boot,dm-pre-reloc;
  35         };
  36
  37         soc {
  38                 u-boot,dm-pre-reloc;
  39
  40                 ddr: ddr@5a003000 {
  41                         u-boot,dm-pre-reloc;
  42
  43                         compatible = "st,stm32mp1-ddr";
  44
  45                         reg = <0x5A003000 0x550
  46                                0x5A004000 0x234>;
  47
  48                         clocks = <&rcc AXIDCG>,
  49                                  <&rcc DDRC1>,
  50                                  <&rcc DDRC2>,
  51                                  <&rcc DDRPHYC>,
  52                                  <&rcc DDRCAPB>,
  53                                  <&rcc DDRPHYCAPB>;
  54
  55                         clock-names = "axidcg",
  56                                       "ddrc1",
  57                                       "ddrc2",
  58                                       "ddrphyc",
  59                                       "ddrcapb",
  60                                       "ddrphycapb";
  61
  62                         status = "okay";
  63                 };
  64         };
  65 };
  66
  67 &bsec {
  68         u-boot,dm-pre-reloc;
  69 };
  70
  71 &clk_csi {
  72         u-boot,dm-pre-reloc;
  73 };
  74
  75 &clk_hsi {
  76         u-boot,dm-pre-reloc;
  77 };
  78
  79 &clk_hse {
  80         u-boot,dm-pre-reloc;
  81 };
  82
  83 &clk_lsi {
  84         u-boot,dm-pre-reloc;
  85 };
  86
  87 &clk_lse {
  88         u-boot,dm-pre-reloc;
  89 };
  90
  91 &cpu0_opp_table {
  92         u-boot,dm-spl;
  93         opp-650000000 {
  94                 u-boot,dm-spl;
  95         };
  96         opp-800000000 {
  97                 u-boot,dm-spl;
  98         };
  99 };
 100
 101 &gpioa {
 102         u-boot,dm-pre-reloc;
 103 };
 104
 105 &gpiob {
 106         u-boot,dm-pre-reloc;
 107 };
 108
 109 &gpioc {
 110         u-boot,dm-pre-reloc;
 111 };
 112
 113 &gpiod {
 114         u-boot,dm-pre-reloc;
 115 };
 116
 117 &gpioe {
 118         u-boot,dm-pre-reloc;
 119 };
 120
 121 &gpiof {
 122         u-boot,dm-pre-reloc;
 123 };
 124
 125 &gpiog {
 126         u-boot,dm-pre-reloc;
 127 };
 128
 129 &gpioh {
 130         u-boot,dm-pre-reloc;
 131 };
 132
 133 &gpioi {
 134         u-boot,dm-pre-reloc;
 135 };
 136
 137 &gpioj {
 138         u-boot,dm-pre-reloc;
 139 };
 140
 141 &gpiok {
 142         u-boot,dm-pre-reloc;
 143 };
 144
 145 &gpioz {
 146         u-boot,dm-pre-reloc;
 147 };
 148
 149 &iwdg2 {
 150         u-boot,dm-pre-reloc;
 151 };
 152
 153 /* pre-reloc probe = reserve video frame buffer in video_reserve() */
 154 &ltdc {
 155         u-boot,dm-pre-proper;
 156 };
 157
 158 &pinctrl {
 159         u-boot,dm-pre-reloc;
 160 };
 161
 162 &pinctrl_z {
 163         u-boot,dm-pre-reloc;
 164 };
 165
 166 &pwr_regulators {
 167         u-boot,dm-pre-reloc;
 168 };
 169
 170 &rcc {
 171         u-boot,dm-pre-reloc;
 172         #address-cells = <1>;
 173         #size-cells = <0>;
 174 };
 175
 176 &sdmmc1 {
 177         compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
 178 };
 179
 180 &sdmmc2 {
 181         compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
 182 };
 183
 184 &sdmmc3 {
 185         compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
 186 };
 187
 188 &usbotg_hs {
 189         compatible = "st,stm32mp1-hsotg", "snps,dwc2";
 190 };