arch/arm/dts/stm32mp15-u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright : STMicroelectronics 2018
   4  */
   5
   6 / {
   7         aliases {
   8                 gpio0 = &gpioa;
   9                 gpio1 = &gpiob;
  10                 gpio2 = &gpioc;
  11                 gpio3 = &gpiod;
  12                 gpio4 = &gpioe;
  13                 gpio5 = &gpiof;
  14                 gpio6 = &gpiog;
  15                 gpio7 = &gpioh;
  16                 gpio8 = &gpioi;
  17                 gpio9 = &gpioj;
  18                 gpio10 = &gpiok;
  19                 gpio25 = &gpioz;
  20                 pinctrl0 = &pinctrl;
  21                 pinctrl1 = &pinctrl_z;
  22         };
  23
  24         binman: binman {
  25                 multiple-images;
  26         };
  27
  28         clocks {
  29                 u-boot,dm-pre-reloc;
  30         };
  31
  32         /* need PSCI for sysreset during board_f */
  33         psci {
  34                 u-boot,dm-pre-proper;
  35         };
  36
  37         reboot {
  38                 u-boot,dm-pre-reloc;
  39                 compatible = "syscon-reboot";
  40                 regmap = <&rcc>;
  41                 offset = <0x404>;
  42                 mask = <0x1>;
  43         };
  44
  45         soc {
  46                 u-boot,dm-pre-reloc;
  47
  48                 ddr: ddr@5a003000 {
  49                         u-boot,dm-pre-reloc;
  50
  51                         compatible = "st,stm32mp1-ddr";
  52
  53                         reg = <0x5A003000 0x550
  54                                0x5A004000 0x234>;
  55
  56                         clocks = <&rcc AXIDCG>,
  57                                  <&rcc DDRC1>,
  58                                  <&rcc DDRC2>,
  59                                  <&rcc DDRPHYC>,
  60                                  <&rcc DDRCAPB>,
  61                                  <&rcc DDRPHYCAPB>;
  62
  63                         clock-names = "axidcg",
  64                                       "ddrc1",
  65                                       "ddrc2",
  66                                       "ddrphyc",
  67                                       "ddrcapb",
  68                                       "ddrphycapb";
  69
  70                         status = "okay";
  71                 };
  72         };
  73 };
  74
  75 &bsec {
  76         u-boot,dm-pre-reloc;
  77 };
  78
  79 &clk_csi {
  80         u-boot,dm-pre-reloc;
  81 };
  82
  83 &clk_hsi {
  84         u-boot,dm-pre-reloc;
  85 };
  86
  87 &clk_hse {
  88         u-boot,dm-pre-reloc;
  89 };
  90
  91 &clk_lsi {
  92         u-boot,dm-pre-reloc;
  93 };
  94
  95 &clk_lse {
  96         u-boot,dm-pre-reloc;
  97 };
  98
  99 &cpu0_opp_table {
 100         u-boot,dm-spl;
 101         opp-650000000 {
 102                 u-boot,dm-spl;
 103         };
 104         opp-800000000 {
 105                 u-boot,dm-spl;
 106         };
 107 };
 108
 109 &gpioa {
 110         u-boot,dm-pre-reloc;
 111 };
 112
 113 &gpiob {
 114         u-boot,dm-pre-reloc;
 115 };
 116
 117 &gpioc {
 118         u-boot,dm-pre-reloc;
 119 };
 120
 121 &gpiod {
 122         u-boot,dm-pre-reloc;
 123 };
 124
 125 &gpioe {
 126         u-boot,dm-pre-reloc;
 127 };
 128
 129 &gpiof {
 130         u-boot,dm-pre-reloc;
 131 };
 132
 133 &gpiog {
 134         u-boot,dm-pre-reloc;
 135 };
 136
 137 &gpioh {
 138         u-boot,dm-pre-reloc;
 139 };
 140
 141 &gpioi {
 142         u-boot,dm-pre-reloc;
 143 };
 144
 145 &gpioj {
 146         u-boot,dm-pre-reloc;
 147 };
 148
 149 &gpiok {
 150         u-boot,dm-pre-reloc;
 151 };
 152
 153 &gpioz {
 154         u-boot,dm-pre-reloc;
 155 };
 156
 157 &iwdg2 {
 158         u-boot,dm-pre-reloc;
 159 };
 160
 161 /* pre-reloc probe = reserve video frame buffer in video_reserve() */
 162 &ltdc {
 163         u-boot,dm-pre-proper;
 164 };
 165
 166 /* temp = waiting kernel update */
 167 &m4_rproc {
 168         resets = <&rcc MCU_R>,
 169                  <&rcc MCU_HOLD_BOOT_R>;
 170         reset-names = "mcu_rst", "hold_boot";
 171 };
 172
 173 &pinctrl {
 174         u-boot,dm-pre-reloc;
 175 };
 176
 177 &pinctrl_z {
 178         u-boot,dm-pre-reloc;
 179 };
 180
 181 &pwr_regulators {
 182         u-boot,dm-pre-reloc;
 183 };
 184
 185 &rcc {
 186         u-boot,dm-pre-reloc;
 187         #address-cells = <1>;
 188         #size-cells = <0>;
 189 };
 190
 191 &sdmmc1 {
 192         compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
 193 };
 194
 195 &sdmmc2 {
 196         compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
 197 };
 198
 199 &sdmmc3 {
 200         compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
 201 };
 202
 203 &usart1 {
 204         resets = <&rcc USART1_R>;
 205 };
 206
 207 &usart2 {
 208         resets = <&rcc USART2_R>;
 209 };
 210
 211 &usart3 {
 212         resets = <&rcc USART3_R>;
 213 };
 214
 215 &uart4 {
 216         resets = <&rcc UART4_R>;
 217 };
 218
 219 &uart5 {
 220         resets = <&rcc UART5_R>;
 221 };
 222
 223 &usart6 {
 224         resets = <&rcc USART6_R>;
 225 };
 226
 227 &uart7 {
 228         resets = <&rcc UART7_R>;
 229 };
 230
 231 &uart8{
 232         resets = <&rcc UART8_R>;
 233 };
 234
 235 #if defined(CONFIG_STM32MP15x_STM32IMAGE)
 236 &binman {
 237         u-boot-stm32 {
 238                 filename = "u-boot.stm32";
 239                 mkimage {
 240                         args = "-T stm32image -a 0xC0100000 -e 0xC0100000";
 241                         u-boot {
 242                         };
 243                 };
 244         };
 245 };
 246 #endif
 247
 248 #if defined(CONFIG_SPL)
 249 &binman {
 250         spl-stm32 {
 251                 filename = "u-boot-spl.stm32";
 252                 mkimage {
 253                         args = "-T stm32image -a 0x2FFC2500 -e 0x2FFC2500";
 254                         u-boot-spl {
 255                         };
 256                 };
 257         };
 258 };
 259 #endif