arch/arm/dts/stm32mp131.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /*
   3  * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
   4  * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
   5  */
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/stm32mp13-clks.h>
   8 #include <dt-bindings/reset/stm32mp13-resets.h>
   9
  10 / {
  11         #address-cells = <1>;
  12         #size-cells = <1>;
  13
  14         cpus {
  15                 #address-cells = <1>;
  16                 #size-cells = <0>;
  17
  18                 cpu0: cpu@0 {
  19                         compatible = "arm,cortex-a7";
  20                         device_type = "cpu";
  21                         reg = <0>;
  22                 };
  23         };
  24
  25         arm-pmu {
  26                 compatible = "arm,cortex-a7-pmu";
  27                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
  28                 interrupt-affinity = <&cpu0>;
  29                 interrupt-parent = <&intc>;
  30         };
  31
  32         firmware {
  33                 optee {
  34                         method = "smc";
  35                         compatible = "linaro,optee-tz";
  36                 };
  37
  38                 scmi: scmi {
  39                         compatible = "linaro,scmi-optee";
  40                         #address-cells = <1>;
  41                         #size-cells = <0>;
  42                         linaro,optee-channel-id = <0>;
  43                         shmem = <&scmi_shm>;
  44
  45                         scmi_clk: protocol@14 {
  46                                 reg = <0x14>;
  47                                 #clock-cells = <1>;
  48                         };
  49
  50                         scmi_reset: protocol@16 {
  51                                 reg = <0x16>;
  52                                 #reset-cells = <1>;
  53                         };
  54                 };
  55         };
  56
  57         intc: interrupt-controller@a0021000 {
  58                 compatible = "arm,cortex-a7-gic";
  59                 #interrupt-cells = <3>;
  60                 interrupt-controller;
  61                 reg = <0xa0021000 0x1000>,
  62                       <0xa0022000 0x2000>;
  63         };
  64
  65         psci {
  66                 compatible = "arm,psci-1.0";
  67                 method = "smc";
  68         };
  69
  70         timer {
  71                 compatible = "arm,armv7-timer";
  72                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
  73                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
  74                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
  75                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
  76                 interrupt-parent = <&intc>;
  77                 always-on;
  78         };
  79
  80         soc {
  81                 compatible = "simple-bus";
  82                 #address-cells = <1>;
  83                 #size-cells = <1>;
  84                 interrupt-parent = <&intc>;
  85                 ranges;
  86
  87                 scmi_sram: sram@2ffff000 {
  88                         compatible = "mmio-sram";
  89                         reg = <0x2ffff000 0x1000>;
  90                         #address-cells = <1>;
  91                         #size-cells = <1>;
  92                         ranges = <0 0x2ffff000 0x1000>;
  93
  94                         scmi_shm: scmi-sram@0 {
  95                                 compatible = "arm,scmi-shmem";
  96                                 reg = <0 0x80>;
  97                         };
  98                 };
  99
 100                 uart4: serial@40010000 {
 101                         compatible = "st,stm32h7-uart";
 102                         reg = <0x40010000 0x400>;
 103                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 104                         clocks = <&rcc UART4_K>;
 105                         resets = <&rcc UART4_R>;
 106                         status = "disabled";
 107                 };
 108
 109                 dma1: dma-controller@48000000 {
 110                         compatible = "st,stm32-dma";
 111                         reg = <0x48000000 0x400>;
 112                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 113                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 114                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 115                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 116                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 117                                      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 118                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 119                                      <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 120                         clocks = <&rcc DMA1>;
 121                         resets = <&rcc DMA1_R>;
 122                         #dma-cells = <4>;
 123                         st,mem2mem;
 124                         dma-requests = <8>;
 125                 };
 126
 127                 dma2: dma-controller@48001000 {
 128                         compatible = "st,stm32-dma";
 129                         reg = <0x48001000 0x400>;
 130                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
 131                                      <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 132                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 133                                      <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 134                                      <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
 135                                      <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
 136                                      <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 137                                      <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 138                         clocks = <&rcc DMA2>;
 139                         resets = <&rcc DMA2_R>;
 140                         #dma-cells = <4>;
 141                         st,mem2mem;
 142                         dma-requests = <8>;
 143                 };
 144
 145                 dmamux1: dma-router@48002000 {
 146                         compatible = "st,stm32h7-dmamux";
 147                         reg = <0x48002000 0x40>;
 148                         clocks = <&rcc DMAMUX1>;
 149                         resets = <&rcc DMAMUX1_R>;
 150                         #dma-cells = <3>;
 151                         dma-masters = <&dma1 &dma2>;
 152                         dma-requests = <128>;
 153                         dma-channels = <16>;
 154                 };
 155
 156                 rcc: rcc@50000000 {
 157                         compatible = "st,stm32mp13-rcc", "syscon";
 158                         reg = <0x50000000 0x1000>;
 159                         #clock-cells = <1>;
 160                         #reset-cells = <1>;
 161                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 162
 163                         clock-names = "hse", "hsi", "csi", "lse", "lsi";
 164                         clocks = <&scmi_clk CK_SCMI_HSE>,
 165                                  <&scmi_clk CK_SCMI_HSI>,
 166                                  <&scmi_clk CK_SCMI_CSI>,
 167                                  <&scmi_clk CK_SCMI_LSE>,
 168                                  <&scmi_clk CK_SCMI_LSI>;
 169                 };
 170
 171                 exti: interrupt-controller@5000d000 {
 172                         compatible = "st,stm32mp13-exti", "syscon";
 173                         interrupt-controller;
 174                         #interrupt-cells = <2>;
 175                         reg = <0x5000d000 0x400>;
 176                 };
 177
 178                 syscfg: syscon@50020000 {
 179                         compatible = "st,stm32mp157-syscfg", "syscon";
 180                         reg = <0x50020000 0x400>;
 181                         clocks = <&rcc SYSCFG>;
 182                 };
 183
 184                 mdma: dma-controller@58000000 {
 185                         compatible = "st,stm32h7-mdma";
 186                         reg = <0x58000000 0x1000>;
 187                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 188                         clocks = <&rcc MDMA>;
 189                         #dma-cells = <5>;
 190                         dma-channels = <32>;
 191                         dma-requests = <48>;
 192                 };
 193
 194                 sdmmc1: mmc@58005000 {
 195                         compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
 196                         arm,primecell-periphid = <0x20253180>;
 197                         reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
 198                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 199                         clocks = <&rcc SDMMC1_K>;
 200                         clock-names = "apb_pclk";
 201                         resets = <&rcc SDMMC1_R>;
 202                         cap-sd-highspeed;
 203                         cap-mmc-highspeed;
 204                         max-frequency = <130000000>;
 205                         status = "disabled";
 206                 };
 207
 208                 sdmmc2: mmc@58007000 {
 209                         compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
 210                         arm,primecell-periphid = <0x20253180>;
 211                         reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
 212                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 213                         clocks = <&rcc SDMMC2_K>;
 214                         clock-names = "apb_pclk";
 215                         resets = <&rcc SDMMC2_R>;
 216
 217                         cap-sd-highspeed;
 218                         cap-mmc-highspeed;
 219                         max-frequency = <130000000>;
 220                         status = "disabled";
 221                 };
 222
 223                 iwdg2: watchdog@5a002000 {
 224                         compatible = "st,stm32mp1-iwdg";
 225                         reg = <0x5a002000 0x400>;
 226                         clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
 227                         clock-names = "pclk", "lsi";
 228                         status = "disabled";
 229                 };
 230
 231                 rtc: rtc@5c004000 {
 232                         compatible = "st,stm32mp1-rtc";
 233                         reg = <0x5c004000 0x400>;
 234                         interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
 235                         clocks = <&scmi_clk CK_SCMI_RTCAPB>,
 236                                  <&scmi_clk CK_SCMI_RTC>;
 237                         clock-names = "pclk", "rtc_ck";
 238                         status = "disabled";
 239                 };
 240
 241                 bsec: efuse@5c005000 {
 242                         compatible = "st,stm32mp13-bsec";
 243                         reg = <0x5c005000 0x400>;
 244                         #address-cells = <1>;
 245                         #size-cells = <1>;
 246
 247                         part_number_otp: part_number_otp@4 {
 248                                 reg = <0x4 0x2>;
 249                         };
 250                         ts_cal1: calib@5c {
 251                                 reg = <0x5c 0x2>;
 252                         };
 253                         ts_cal2: calib@5e {
 254                                 reg = <0x5e 0x2>;
 255                         };
 256                 };
 257
 258                 /*
 259                  * Break node order to solve dependency probe issue between
 260                  * pinctrl and exti.
 261                  */
 262                 pinctrl: pinctrl@50002000 {
 263                         #address-cells = <1>;
 264                         #size-cells = <1>;
 265                         compatible = "st,stm32mp135-pinctrl";
 266                         ranges = <0 0x50002000 0x8400>;
 267                         interrupt-parent = <&exti>;
 268                         st,syscfg = <&exti 0x60 0xff>;
 269                         pins-are-numbered;
 270
 271                         gpioa: gpio@50002000 {
 272                                 gpio-controller;
 273                                 #gpio-cells = <2>;
 274                                 interrupt-controller;
 275                                 #interrupt-cells = <2>;
 276                                 reg = <0x0 0x400>;
 277                                 clocks = <&rcc GPIOA>;
 278                                 st,bank-name = "GPIOA";
 279                                 ngpios = <16>;
 280                                 gpio-ranges = <&pinctrl 0 0 16>;
 281                         };
 282
 283                         gpiob: gpio@50003000 {
 284                                 gpio-controller;
 285                                 #gpio-cells = <2>;
 286                                 interrupt-controller;
 287                                 #interrupt-cells = <2>;
 288                                 reg = <0x1000 0x400>;
 289                                 clocks = <&rcc GPIOB>;
 290                                 st,bank-name = "GPIOB";
 291                                 ngpios = <16>;
 292                                 gpio-ranges = <&pinctrl 0 16 16>;
 293                         };
 294
 295                         gpioc: gpio@50004000 {
 296                                 gpio-controller;
 297                                 #gpio-cells = <2>;
 298                                 interrupt-controller;
 299                                 #interrupt-cells = <2>;
 300                                 reg = <0x2000 0x400>;
 301                                 clocks = <&rcc GPIOC>;
 302                                 st,bank-name = "GPIOC";
 303                                 ngpios = <16>;
 304                                 gpio-ranges = <&pinctrl 0 32 16>;
 305                         };
 306
 307                         gpiod: gpio@50005000 {
 308                                 gpio-controller;
 309                                 #gpio-cells = <2>;
 310                                 interrupt-controller;
 311                                 #interrupt-cells = <2>;
 312                                 reg = <0x3000 0x400>;
 313                                 clocks = <&rcc GPIOD>;
 314                                 st,bank-name = "GPIOD";
 315                                 ngpios = <16>;
 316                                 gpio-ranges = <&pinctrl 0 48 16>;
 317                         };
 318
 319                         gpioe: gpio@50006000 {
 320                                 gpio-controller;
 321                                 #gpio-cells = <2>;
 322                                 interrupt-controller;
 323                                 #interrupt-cells = <2>;
 324                                 reg = <0x4000 0x400>;
 325                                 clocks = <&rcc GPIOE>;
 326                                 st,bank-name = "GPIOE";
 327                                 ngpios = <16>;
 328                                 gpio-ranges = <&pinctrl 0 64 16>;
 329                         };
 330
 331                         gpiof: gpio@50007000 {
 332                                 gpio-controller;
 333                                 #gpio-cells = <2>;
 334                                 interrupt-controller;
 335                                 #interrupt-cells = <2>;
 336                                 reg = <0x5000 0x400>;
 337                                 clocks = <&rcc GPIOF>;
 338                                 st,bank-name = "GPIOF";
 339                                 ngpios = <16>;
 340                                 gpio-ranges = <&pinctrl 0 80 16>;
 341                         };
 342
 343                         gpiog: gpio@50008000 {
 344                                 gpio-controller;
 345                                 #gpio-cells = <2>;
 346                                 interrupt-controller;
 347                                 #interrupt-cells = <2>;
 348                                 reg = <0x6000 0x400>;
 349                                 clocks = <&rcc GPIOG>;
 350                                 st,bank-name = "GPIOG";
 351                                 ngpios = <16>;
 352                                 gpio-ranges = <&pinctrl 0 96 16>;
 353                         };
 354
 355                         gpioh: gpio@50009000 {
 356                                 gpio-controller;
 357                                 #gpio-cells = <2>;
 358                                 interrupt-controller;
 359                                 #interrupt-cells = <2>;
 360                                 reg = <0x7000 0x400>;
 361                                 clocks = <&rcc GPIOH>;
 362                                 st,bank-name = "GPIOH";
 363                                 ngpios = <15>;
 364                                 gpio-ranges = <&pinctrl 0 112 15>;
 365                         };
 366
 367                         gpioi: gpio@5000a000 {
 368                                 gpio-controller;
 369                                 #gpio-cells = <2>;
 370                                 interrupt-controller;
 371                                 #interrupt-cells = <2>;
 372                                 reg = <0x8000 0x400>;
 373                                 clocks = <&rcc GPIOI>;
 374                                 st,bank-name = "GPIOI";
 375                                 ngpios = <8>;
 376                                 gpio-ranges = <&pinctrl 0 128 8>;
 377                         };
 378                 };
 379         };
 380 };