1 // SPDX-License-Identifier: GPL-2.0+ OR X11
3 * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
7 #include "armv7-m.dtsi"
8 #include <dt-bindings/clock/stm32h7-clks.h>
9 #include <dt-bindings/mfd/stm32h7-rcc.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
19 compatible = "fixed-clock";
20 clock-frequency = <0>;
25 compatible = "fixed-clock";
26 clock-frequency = <32768>;
31 compatible = "fixed-clock";
32 clock-frequency = <0>;
37 timer5: timer@40000c00 {
38 compatible = "st,stm32-timer";
39 reg = <0x40000c00 0x400>;
41 clocks = <&rcc TIM5_CK>;
44 lptimer1: timer@40002400 {
47 compatible = "st,stm32-lptimer";
48 reg = <0x40002400 0x400>;
49 clocks = <&rcc LPTIM1_CK>;
54 compatible = "st,stm32-pwm-lp";
60 compatible = "st,stm32-lptimer-trigger";
66 compatible = "st,stm32-lptimer-counter";
74 compatible = "st,stm32h7-spi";
75 reg = <0x40003800 0x400>;
77 resets = <&rcc STM32H7_APB1L_RESET(SPI2)>;
78 clocks = <&rcc SPI2_CK>;
86 compatible = "st,stm32h7-spi";
87 reg = <0x40003c00 0x400>;
89 resets = <&rcc STM32H7_APB1L_RESET(SPI3)>;
90 clocks = <&rcc SPI3_CK>;
94 usart2: serial@40004400 {
95 compatible = "st,stm32h7-uart";
96 reg = <0x40004400 0x400>;
99 clocks = <&rcc USART2_CK>;
103 compatible = "st,stm32f7-i2c";
104 #address-cells = <1>;
106 reg = <0x40005400 0x400>;
109 resets = <&rcc STM32H7_APB1L_RESET(I2C1)>;
110 clocks = <&rcc I2C1_CK>;
115 compatible = "st,stm32f7-i2c";
116 #address-cells = <1>;
118 reg = <0x40005800 0x400>;
121 resets = <&rcc STM32H7_APB1L_RESET(I2C2)>;
122 clocks = <&rcc I2C2_CK>;
127 compatible = "st,stm32f7-i2c";
128 #address-cells = <1>;
130 reg = <0x40005C00 0x400>;
133 resets = <&rcc STM32H7_APB1L_RESET(I2C3)>;
134 clocks = <&rcc I2C3_CK>;
139 compatible = "st,stm32h7-dac-core";
140 reg = <0x40007400 0x400>;
141 clocks = <&rcc DAC12_CK>;
142 clock-names = "pclk";
143 #address-cells = <1>;
148 compatible = "st,stm32-dac";
149 #io-channel-cells = <1>;
155 compatible = "st,stm32-dac";
156 #io-channel-cells = <1>;
162 usart1: serial@40011000 {
163 compatible = "st,stm32h7-uart";
164 reg = <0x40011000 0x400>;
167 clocks = <&rcc USART1_CK>;
171 #address-cells = <1>;
173 compatible = "st,stm32h7-spi";
174 reg = <0x40013000 0x400>;
176 resets = <&rcc STM32H7_APB2_RESET(SPI1)>;
177 clocks = <&rcc SPI1_CK>;
182 #address-cells = <1>;
184 compatible = "st,stm32h7-spi";
185 reg = <0x40013400 0x400>;
187 resets = <&rcc STM32H7_APB2_RESET(SPI4)>;
188 clocks = <&rcc SPI4_CK>;
193 #address-cells = <1>;
195 compatible = "st,stm32h7-spi";
196 reg = <0x40015000 0x400>;
198 resets = <&rcc STM32H7_APB2_RESET(SPI5)>;
199 clocks = <&rcc SPI5_CK>;
203 dma1: dma-controller@40020000 {
204 compatible = "st,stm32-dma";
205 reg = <0x40020000 0x400>;
214 clocks = <&rcc DMA1_CK>;
221 dma2: dma-controller@40020400 {
222 compatible = "st,stm32-dma";
223 reg = <0x40020400 0x400>;
232 clocks = <&rcc DMA2_CK>;
239 dmamux1: dma-router@40020800 {
240 compatible = "st,stm32h7-dmamux";
241 reg = <0x40020800 0x1c>;
244 dma-requests = <128>;
245 dma-masters = <&dma1 &dma2>;
246 clocks = <&rcc DMA1_CK>;
249 adc_12: adc@40022000 {
250 compatible = "st,stm32h7-adc-core";
251 reg = <0x40022000 0x400>;
253 clocks = <&rcc ADC12_CK>;
255 interrupt-controller;
256 #interrupt-cells = <1>;
257 #address-cells = <1>;
262 compatible = "st,stm32h7-adc";
263 #io-channel-cells = <1>;
265 interrupt-parent = <&adc_12>;
271 compatible = "st,stm32h7-adc";
272 #io-channel-cells = <1>;
274 interrupt-parent = <&adc_12>;
280 usbotg_hs: usb@40040000 {
281 compatible = "st,stm32f7-hsotg";
282 reg = <0x40040000 0x40000>;
284 clocks = <&rcc USB1OTG_CK>;
286 g-rx-fifo-size = <256>;
287 g-np-tx-fifo-size = <32>;
288 g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
292 usbotg_fs: usb@40080000 {
293 compatible = "st,stm32f4x9-fsotg";
294 reg = <0x40080000 0x40000>;
296 clocks = <&rcc USB2OTG_CK>;
301 ltdc: display-controller@50001000 {
302 compatible = "st,stm32-ltdc";
303 reg = <0x50001000 0x200>;
304 interrupts = <88>, <89>;
305 resets = <&rcc STM32H7_APB3_RESET(LTDC)>;
306 clocks = <&rcc LTDC_CK>;
311 mdma1: dma-controller@52000000 {
312 compatible = "st,stm32h7-mdma";
313 reg = <0x52000000 0x1000>;
315 clocks = <&rcc MDMA_CK>;
321 sdmmc1: sdmmc@52007000 {
322 compatible = "arm,pl18x", "arm,primecell";
323 arm,primecell-periphid = <0x10153180>;
324 reg = <0x52007000 0x1000>;
326 interrupt-names = "cmd_irq";
327 clocks = <&rcc SDMMC1_CK>;
328 clock-names = "apb_pclk";
329 resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>;
332 max-frequency = <120000000>;
335 exti: interrupt-controller@58000000 {
336 compatible = "st,stm32h7-exti";
337 interrupt-controller;
338 #interrupt-cells = <2>;
339 reg = <0x58000000 0x400>;
340 interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <62>, <76>;
343 syscfg: syscon@58000400 {
344 compatible = "st,stm32-syscfg", "syscon";
345 reg = <0x58000400 0x400>;
349 #address-cells = <1>;
351 compatible = "st,stm32h7-spi";
352 reg = <0x58001400 0x400>;
354 resets = <&rcc STM32H7_APB4_RESET(SPI6)>;
355 clocks = <&rcc SPI6_CK>;
360 compatible = "st,stm32f7-i2c";
361 #address-cells = <1>;
363 reg = <0x58001C00 0x400>;
366 resets = <&rcc STM32H7_APB4_RESET(I2C4)>;
367 clocks = <&rcc I2C4_CK>;
371 lptimer2: timer@58002400 {
372 #address-cells = <1>;
374 compatible = "st,stm32-lptimer";
375 reg = <0x58002400 0x400>;
376 clocks = <&rcc LPTIM2_CK>;
381 compatible = "st,stm32-pwm-lp";
387 compatible = "st,stm32-lptimer-trigger";
393 compatible = "st,stm32-lptimer-counter";
398 lptimer3: timer@58002800 {
399 #address-cells = <1>;
401 compatible = "st,stm32-lptimer";
402 reg = <0x58002800 0x400>;
403 clocks = <&rcc LPTIM3_CK>;
408 compatible = "st,stm32-pwm-lp";
414 compatible = "st,stm32-lptimer-trigger";
420 lptimer4: timer@58002c00 {
421 #address-cells = <1>;
423 compatible = "st,stm32-lptimer";
424 reg = <0x58002c00 0x400>;
425 clocks = <&rcc LPTIM4_CK>;
430 compatible = "st,stm32-pwm-lp";
436 lptimer5: timer@58003000 {
437 #address-cells = <1>;
439 compatible = "st,stm32-lptimer";
440 reg = <0x58003000 0x400>;
441 clocks = <&rcc LPTIM5_CK>;
446 compatible = "st,stm32-pwm-lp";
452 vrefbuf: regulator@58003c00 {
453 compatible = "st,stm32-vrefbuf";
454 reg = <0x58003C00 0x8>;
455 clocks = <&rcc VREF_CK>;
456 regulator-min-microvolt = <1500000>;
457 regulator-max-microvolt = <2500000>;
462 compatible = "st,stm32h7-rtc";
463 reg = <0x58004000 0x400>;
464 clocks = <&rcc RTCAPB_CK>, <&rcc RTC_CK>;
465 clock-names = "pclk", "rtc_ck";
466 assigned-clocks = <&rcc RTC_CK>;
467 assigned-clock-parents = <&rcc LSE_CK>;
468 interrupt-parent = <&exti>;
469 interrupts = <17 IRQ_TYPE_EDGE_RISING>;
470 st,syscfg = <&pwrcfg 0x00 0x100>;
474 rcc: reset-clock-controller@58024400 {
475 compatible = "st,stm32h743-rcc", "st,stm32-rcc";
476 reg = <0x58024400 0x400>;
479 clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>;
480 st,syscfg = <&pwrcfg>;
483 pwrcfg: power-config@58024800 {
484 compatible = "st,stm32-power-config", "syscon";
485 reg = <0x58024800 0x400>;
488 adc_3: adc@58026000 {
489 compatible = "st,stm32h7-adc-core";
490 reg = <0x58026000 0x400>;
492 clocks = <&rcc ADC3_CK>;
494 interrupt-controller;
495 #interrupt-cells = <1>;
496 #address-cells = <1>;
501 compatible = "st,stm32h7-adc";
502 #io-channel-cells = <1>;
504 interrupt-parent = <&adc_3>;
510 mac: ethernet@40028000 {
511 compatible = "st,stm32-dwmac", "snps,dwmac-4.10a";
512 reg = <0x40028000 0x8000>;
513 reg-names = "stmmaceth";
515 interrupt-names = "macirq";
516 clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
517 clocks = <&rcc ETH1MAC_CK>, <&rcc ETH1TX_CK>, <&rcc ETH1RX_CK>;
518 st,syscon = <&syscfg 0x4>;
526 clock-frequency = <250000000>;