arch/arm/dts/stm32h743.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
   4  *
   5  */
   6
   7 #include "armv7-m.dtsi"
   8 #include <dt-bindings/clock/stm32h7-clks.h>
   9 #include <dt-bindings/mfd/stm32h7-rcc.h>
  10 #include <dt-bindings/interrupt-controller/irq.h>
  11
  12 / {
  13         #address-cells = <1>;
  14         #size-cells = <1>;
  15
  16         clocks {
  17                 clk_hse: clk-hse {
  18                         #clock-cells = <0>;
  19                         compatible = "fixed-clock";
  20                         clock-frequency = <0>;
  21                 };
  22
  23                 clk_lse: clk-lse {
  24                         #clock-cells = <0>;
  25                         compatible = "fixed-clock";
  26                         clock-frequency = <32768>;
  27                 };
  28
  29                 clk_i2s: i2s_ckin {
  30                         #clock-cells = <0>;
  31                         compatible = "fixed-clock";
  32                         clock-frequency = <0>;
  33                 };
  34         };
  35
  36         soc {
  37                 timer5: timer@40000c00 {
  38                         compatible = "st,stm32-timer";
  39                         reg = <0x40000c00 0x400>;
  40                         interrupts = <50>;
  41                         clocks = <&rcc TIM5_CK>;
  42                 };
  43
  44                 lptimer1: timer@40002400 {
  45                         #address-cells = <1>;
  46                         #size-cells = <0>;
  47                         compatible = "st,stm32-lptimer";
  48                         reg = <0x40002400 0x400>;
  49                         clocks = <&rcc LPTIM1_CK>;
  50                         clock-names = "mux";
  51                         status = "disabled";
  52
  53                         pwm {
  54                                 compatible = "st,stm32-pwm-lp";
  55                                 #pwm-cells = <3>;
  56                                 status = "disabled";
  57                         };
  58
  59                         trigger@0 {
  60                                 compatible = "st,stm32-lptimer-trigger";
  61                                 reg = <0>;
  62                                 status = "disabled";
  63                         };
  64
  65                         counter {
  66                                 compatible = "st,stm32-lptimer-counter";
  67                                 status = "disabled";
  68                         };
  69                 };
  70
  71                 spi2: spi@40003800 {
  72                         #address-cells = <1>;
  73                         #size-cells = <0>;
  74                         compatible = "st,stm32h7-spi";
  75                         reg = <0x40003800 0x400>;
  76                         interrupts = <36>;
  77                         resets = <&rcc STM32H7_APB1L_RESET(SPI2)>;
  78                         clocks = <&rcc SPI2_CK>;
  79                         status = "disabled";
  80
  81                 };
  82
  83                 spi3: spi@40003c00 {
  84                         #address-cells = <1>;
  85                         #size-cells = <0>;
  86                         compatible = "st,stm32h7-spi";
  87                         reg = <0x40003c00 0x400>;
  88                         interrupts = <51>;
  89                         resets = <&rcc STM32H7_APB1L_RESET(SPI3)>;
  90                         clocks = <&rcc SPI3_CK>;
  91                         status = "disabled";
  92                 };
  93
  94                 usart2: serial@40004400 {
  95                         compatible = "st,stm32h7-uart";
  96                         reg = <0x40004400 0x400>;
  97                         interrupts = <38>;
  98                         status = "disabled";
  99                         clocks = <&rcc USART2_CK>;
 100                 };
 101
 102                 usart3: serial@40004800 {
 103                         compatible = "st,stm32h7-uart";
 104                         reg = <0x40004800 0x400>;
 105                         interrupts = <39>;
 106                         status = "disabled";
 107                         clocks = <&rcc USART3_CK>;
 108                 };
 109
 110                 uart4: serial@40004c00 {
 111                         compatible = "st,stm32h7-uart";
 112                         reg = <0x40004c00 0x400>;
 113                         interrupts = <52>;
 114                         status = "disabled";
 115                         clocks = <&rcc UART4_CK>;
 116                 };
 117
 118                 i2c1: i2c@40005400 {
 119                         compatible = "st,stm32f7-i2c";
 120                         #address-cells = <1>;
 121                         #size-cells = <0>;
 122                         reg = <0x40005400 0x400>;
 123                         interrupts = <31>,
 124                                      <32>;
 125                         resets = <&rcc STM32H7_APB1L_RESET(I2C1)>;
 126                         clocks = <&rcc I2C1_CK>;
 127                         status = "disabled";
 128                 };
 129
 130                 i2c2: i2c@40005800 {
 131                         compatible = "st,stm32f7-i2c";
 132                         #address-cells = <1>;
 133                         #size-cells = <0>;
 134                         reg = <0x40005800 0x400>;
 135                         interrupts = <33>,
 136                                      <34>;
 137                         resets = <&rcc STM32H7_APB1L_RESET(I2C2)>;
 138                         clocks = <&rcc I2C2_CK>;
 139                         status = "disabled";
 140                 };
 141
 142                 i2c3: i2c@40005c00 {
 143                         compatible = "st,stm32f7-i2c";
 144                         #address-cells = <1>;
 145                         #size-cells = <0>;
 146                         reg = <0x40005C00 0x400>;
 147                         interrupts = <72>,
 148                                      <73>;
 149                         resets = <&rcc STM32H7_APB1L_RESET(I2C3)>;
 150                         clocks = <&rcc I2C3_CK>;
 151                         status = "disabled";
 152                 };
 153
 154                 dac: dac@40007400 {
 155                         compatible = "st,stm32h7-dac-core";
 156                         reg = <0x40007400 0x400>;
 157                         clocks = <&rcc DAC12_CK>;
 158                         clock-names = "pclk";
 159                         #address-cells = <1>;
 160                         #size-cells = <0>;
 161                         status = "disabled";
 162
 163                         dac1: dac@1 {
 164                                 compatible = "st,stm32-dac";
 165                                 #io-channel-cells = <1>;
 166                                 reg = <1>;
 167                                 status = "disabled";
 168                         };
 169
 170                         dac2: dac@2 {
 171                                 compatible = "st,stm32-dac";
 172                                 #io-channel-cells = <1>;
 173                                 reg = <2>;
 174                                 status = "disabled";
 175                         };
 176                 };
 177
 178                 usart1: serial@40011000 {
 179                         compatible = "st,stm32h7-uart";
 180                         reg = <0x40011000 0x400>;
 181                         interrupts = <37>;
 182                         status = "disabled";
 183                         clocks = <&rcc USART1_CK>;
 184                 };
 185
 186                 spi1: spi@40013000 {
 187                         #address-cells = <1>;
 188                         #size-cells = <0>;
 189                         compatible = "st,stm32h7-spi";
 190                         reg = <0x40013000 0x400>;
 191                         interrupts = <35>;
 192                         resets = <&rcc STM32H7_APB2_RESET(SPI1)>;
 193                         clocks = <&rcc SPI1_CK>;
 194                         status = "disabled";
 195                 };
 196
 197                 spi4: spi@40013400 {
 198                         #address-cells = <1>;
 199                         #size-cells = <0>;
 200                         compatible = "st,stm32h7-spi";
 201                         reg = <0x40013400 0x400>;
 202                         interrupts = <84>;
 203                         resets = <&rcc STM32H7_APB2_RESET(SPI4)>;
 204                         clocks = <&rcc SPI4_CK>;
 205                         status = "disabled";
 206                 };
 207
 208                 spi5: spi@40015000 {
 209                         #address-cells = <1>;
 210                         #size-cells = <0>;
 211                         compatible = "st,stm32h7-spi";
 212                         reg = <0x40015000 0x400>;
 213                         interrupts = <85>;
 214                         resets = <&rcc STM32H7_APB2_RESET(SPI5)>;
 215                         clocks = <&rcc SPI5_CK>;
 216                         status = "disabled";
 217                 };
 218
 219                 dma1: dma-controller@40020000 {
 220                         compatible = "st,stm32-dma";
 221                         reg = <0x40020000 0x400>;
 222                         interrupts = <11>,
 223                                      <12>,
 224                                      <13>,
 225                                      <14>,
 226                                      <15>,
 227                                      <16>,
 228                                      <17>,
 229                                      <47>;
 230                         clocks = <&rcc DMA1_CK>;
 231                         #dma-cells = <4>;
 232                         st,mem2mem;
 233                         dma-requests = <8>;
 234                         status = "disabled";
 235                 };
 236
 237                 dma2: dma-controller@40020400 {
 238                         compatible = "st,stm32-dma";
 239                         reg = <0x40020400 0x400>;
 240                         interrupts = <56>,
 241                                      <57>,
 242                                      <58>,
 243                                      <59>,
 244                                      <60>,
 245                                      <68>,
 246                                      <69>,
 247                                      <70>;
 248                         clocks = <&rcc DMA2_CK>;
 249                         #dma-cells = <4>;
 250                         st,mem2mem;
 251                         dma-requests = <8>;
 252                         status = "disabled";
 253                 };
 254
 255                 dmamux1: dma-router@40020800 {
 256                         compatible = "st,stm32h7-dmamux";
 257                         reg = <0x40020800 0x40>;
 258                         #dma-cells = <3>;
 259                         dma-channels = <16>;
 260                         dma-requests = <128>;
 261                         dma-masters = <&dma1 &dma2>;
 262                         clocks = <&rcc DMA1_CK>;
 263                 };
 264
 265                 adc_12: adc@40022000 {
 266                         compatible = "st,stm32h7-adc-core";
 267                         reg = <0x40022000 0x400>;
 268                         interrupts = <18>;
 269                         clocks = <&rcc ADC12_CK>;
 270                         clock-names = "bus";
 271                         interrupt-controller;
 272                         #interrupt-cells = <1>;
 273                         #address-cells = <1>;
 274                         #size-cells = <0>;
 275                         status = "disabled";
 276
 277                         adc1: adc@0 {
 278                                 compatible = "st,stm32h7-adc";
 279                                 #io-channel-cells = <1>;
 280                                 reg = <0x0>;
 281                                 interrupt-parent = <&adc_12>;
 282                                 interrupts = <0>;
 283                                 status = "disabled";
 284                         };
 285
 286                         adc2: adc@100 {
 287                                 compatible = "st,stm32h7-adc";
 288                                 #io-channel-cells = <1>;
 289                                 reg = <0x100>;
 290                                 interrupt-parent = <&adc_12>;
 291                                 interrupts = <1>;
 292                                 status = "disabled";
 293                         };
 294                 };
 295
 296                 usbotg_hs: usb@40040000 {
 297                         compatible = "st,stm32f7-hsotg";
 298                         reg = <0x40040000 0x40000>;
 299                         interrupts = <77>;
 300                         clocks = <&rcc USB1OTG_CK>;
 301                         clock-names = "otg";
 302                         g-rx-fifo-size = <256>;
 303                         g-np-tx-fifo-size = <32>;
 304                         g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
 305                         status = "disabled";
 306                 };
 307
 308                 usbotg_fs: usb@40080000 {
 309                         compatible = "st,stm32f4x9-fsotg";
 310                         reg = <0x40080000 0x40000>;
 311                         interrupts = <101>;
 312                         clocks = <&rcc USB2OTG_CK>;
 313                         clock-names = "otg";
 314                         status = "disabled";
 315                 };
 316
 317                 ltdc: display-controller@50001000 {
 318                         compatible = "st,stm32-ltdc";
 319                         reg = <0x50001000 0x200>;
 320                         interrupts = <88>, <89>;
 321                         resets = <&rcc STM32H7_APB3_RESET(LTDC)>;
 322                         clocks = <&rcc LTDC_CK>;
 323                         clock-names = "lcd";
 324                         status = "disabled";
 325                 };
 326
 327                 mdma1: dma-controller@52000000 {
 328                         compatible = "st,stm32h7-mdma";
 329                         reg = <0x52000000 0x1000>;
 330                         interrupts = <122>;
 331                         clocks = <&rcc MDMA_CK>;
 332                         #dma-cells = <5>;
 333                         dma-channels = <16>;
 334                         dma-requests = <32>;
 335                 };
 336
 337                 sdmmc1: sdmmc@52007000 {
 338                         compatible = "arm,pl18x", "arm,primecell";
 339                         arm,primecell-periphid = <0x10153180>;
 340                         reg = <0x52007000 0x1000>;
 341                         interrupts = <49>;
 342                         interrupt-names = "cmd_irq";
 343                         clocks = <&rcc SDMMC1_CK>;
 344                         clock-names = "apb_pclk";
 345                         resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>;
 346                         cap-sd-highspeed;
 347                         cap-mmc-highspeed;
 348                         max-frequency = <120000000>;
 349                 };
 350
 351                 sdmmc2: sdmmc@48022400 {
 352                         compatible = "arm,pl18x", "arm,primecell";
 353                         arm,primecell-periphid = <0x10153180>;
 354                         reg = <0x48022400 0x400>;
 355                         interrupts = <124>;
 356                         interrupt-names = "cmd_irq";
 357                         clocks = <&rcc SDMMC2_CK>;
 358                         clock-names = "apb_pclk";
 359                         resets = <&rcc STM32H7_AHB2_RESET(SDMMC2)>;
 360                         cap-sd-highspeed;
 361                         cap-mmc-highspeed;
 362                         max-frequency = <120000000>;
 363                 };
 364
 365                 exti: interrupt-controller@58000000 {
 366                         compatible = "st,stm32h7-exti";
 367                         interrupt-controller;
 368                         #interrupt-cells = <2>;
 369                         reg = <0x58000000 0x400>;
 370                         interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <62>, <76>;
 371                 };
 372
 373                 syscfg: syscon@58000400 {
 374                         compatible = "st,stm32-syscfg", "syscon";
 375                         reg = <0x58000400 0x400>;
 376                 };
 377
 378                 spi6: spi@58001400 {
 379                         #address-cells = <1>;
 380                         #size-cells = <0>;
 381                         compatible = "st,stm32h7-spi";
 382                         reg = <0x58001400 0x400>;
 383                         interrupts = <86>;
 384                         resets = <&rcc STM32H7_APB4_RESET(SPI6)>;
 385                         clocks = <&rcc SPI6_CK>;
 386                         status = "disabled";
 387                 };
 388
 389                 i2c4: i2c@58001c00 {
 390                         compatible = "st,stm32f7-i2c";
 391                         #address-cells = <1>;
 392                         #size-cells = <0>;
 393                         reg = <0x58001C00 0x400>;
 394                         interrupts = <95>,
 395                                      <96>;
 396                         resets = <&rcc STM32H7_APB4_RESET(I2C4)>;
 397                         clocks = <&rcc I2C4_CK>;
 398                         status = "disabled";
 399                 };
 400
 401                 lptimer2: timer@58002400 {
 402                         #address-cells = <1>;
 403                         #size-cells = <0>;
 404                         compatible = "st,stm32-lptimer";
 405                         reg = <0x58002400 0x400>;
 406                         clocks = <&rcc LPTIM2_CK>;
 407                         clock-names = "mux";
 408                         status = "disabled";
 409
 410                         pwm {
 411                                 compatible = "st,stm32-pwm-lp";
 412                                 #pwm-cells = <3>;
 413                                 status = "disabled";
 414                         };
 415
 416                         trigger@1 {
 417                                 compatible = "st,stm32-lptimer-trigger";
 418                                 reg = <1>;
 419                                 status = "disabled";
 420                         };
 421
 422                         counter {
 423                                 compatible = "st,stm32-lptimer-counter";
 424                                 status = "disabled";
 425                         };
 426                 };
 427
 428                 lptimer3: timer@58002800 {
 429                         #address-cells = <1>;
 430                         #size-cells = <0>;
 431                         compatible = "st,stm32-lptimer";
 432                         reg = <0x58002800 0x400>;
 433                         clocks = <&rcc LPTIM3_CK>;
 434                         clock-names = "mux";
 435                         status = "disabled";
 436
 437                         pwm {
 438                                 compatible = "st,stm32-pwm-lp";
 439                                 #pwm-cells = <3>;
 440                                 status = "disabled";
 441                         };
 442
 443                         trigger@2 {
 444                                 compatible = "st,stm32-lptimer-trigger";
 445                                 reg = <2>;
 446                                 status = "disabled";
 447                         };
 448                 };
 449
 450                 lptimer4: timer@58002c00 {
 451                         #address-cells = <1>;
 452                         #size-cells = <0>;
 453                         compatible = "st,stm32-lptimer";
 454                         reg = <0x58002c00 0x400>;
 455                         clocks = <&rcc LPTIM4_CK>;
 456                         clock-names = "mux";
 457                         status = "disabled";
 458
 459                         pwm {
 460                                 compatible = "st,stm32-pwm-lp";
 461                                 #pwm-cells = <3>;
 462                                 status = "disabled";
 463                         };
 464                 };
 465
 466                 lptimer5: timer@58003000 {
 467                         #address-cells = <1>;
 468                         #size-cells = <0>;
 469                         compatible = "st,stm32-lptimer";
 470                         reg = <0x58003000 0x400>;
 471                         clocks = <&rcc LPTIM5_CK>;
 472                         clock-names = "mux";
 473                         status = "disabled";
 474
 475                         pwm {
 476                                 compatible = "st,stm32-pwm-lp";
 477                                 #pwm-cells = <3>;
 478                                 status = "disabled";
 479                         };
 480                 };
 481
 482                 vrefbuf: regulator@58003c00 {
 483                         compatible = "st,stm32-vrefbuf";
 484                         reg = <0x58003C00 0x8>;
 485                         clocks = <&rcc VREF_CK>;
 486                         regulator-min-microvolt = <1500000>;
 487                         regulator-max-microvolt = <2500000>;
 488                         status = "disabled";
 489                 };
 490
 491                 rtc: rtc@58004000 {
 492                         compatible = "st,stm32h7-rtc";
 493                         reg = <0x58004000 0x400>;
 494                         clocks = <&rcc RTCAPB_CK>, <&rcc RTC_CK>;
 495                         clock-names = "pclk", "rtc_ck";
 496                         assigned-clocks = <&rcc RTC_CK>;
 497                         assigned-clock-parents = <&rcc LSE_CK>;
 498                         interrupt-parent = <&exti>;
 499                         interrupts = <17 IRQ_TYPE_EDGE_RISING>;
 500                         st,syscfg = <&pwrcfg 0x00 0x100>;
 501                         status = "disabled";
 502                 };
 503
 504                 rcc: reset-clock-controller@58024400 {
 505                         compatible = "st,stm32h743-rcc", "st,stm32-rcc";
 506                         reg = <0x58024400 0x400>;
 507                         #clock-cells = <1>;
 508                         #reset-cells = <1>;
 509                         clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>;
 510                         st,syscfg = <&pwrcfg>;
 511                 };
 512
 513                 pwrcfg: power-config@58024800 {
 514                         compatible = "st,stm32-power-config", "syscon";
 515                         reg = <0x58024800 0x400>;
 516                 };
 517
 518                 adc_3: adc@58026000 {
 519                         compatible = "st,stm32h7-adc-core";
 520                         reg = <0x58026000 0x400>;
 521                         interrupts = <127>;
 522                         clocks = <&rcc ADC3_CK>;
 523                         clock-names = "bus";
 524                         interrupt-controller;
 525                         #interrupt-cells = <1>;
 526                         #address-cells = <1>;
 527                         #size-cells = <0>;
 528                         status = "disabled";
 529
 530                         adc3: adc@0 {
 531                                 compatible = "st,stm32h7-adc";
 532                                 #io-channel-cells = <1>;
 533                                 reg = <0x0>;
 534                                 interrupt-parent = <&adc_3>;
 535                                 interrupts = <0>;
 536                                 status = "disabled";
 537                         };
 538                 };
 539
 540                 mac: ethernet@40028000 {
 541                         compatible = "st,stm32-dwmac", "snps,dwmac-4.10a";
 542                         reg = <0x40028000 0x8000>;
 543                         reg-names = "stmmaceth";
 544                         interrupts = <61>;
 545                         interrupt-names = "macirq";
 546                         clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
 547                         clocks = <&rcc ETH1MAC_CK>, <&rcc ETH1TX_CK>, <&rcc ETH1RX_CK>;
 548                         st,syscon = <&syscfg 0x4>;
 549                         snps,pbl = <8>;
 550                         status = "disabled";
 551                 };
 552
 553                 pinctrl: pin-controller@58020000 {
 554                         #address-cells = <1>;
 555                         #size-cells = <1>;
 556                         compatible = "st,stm32h743-pinctrl";
 557                         ranges = <0 0x58020000 0x3000>;
 558                         interrupt-parent = <&exti>;
 559                         st,syscfg = <&syscfg 0x8>;
 560                         pins-are-numbered;
 561
 562                         gpioa: gpio@58020000 {
 563                                 gpio-controller;
 564                                 #gpio-cells = <2>;
 565                                 reg = <0x0 0x400>;
 566                                 clocks = <&rcc GPIOA_CK>;
 567                                 st,bank-name = "GPIOA";
 568                                 interrupt-controller;
 569                                 #interrupt-cells = <2>;
 570                                 ngpios = <16>;
 571                                 gpio-ranges = <&pinctrl 0 0 16>;
 572                         };
 573
 574                         gpiob: gpio@58020400 {
 575                                 gpio-controller;
 576                                 #gpio-cells = <2>;
 577                                 reg = <0x400 0x400>;
 578                                 clocks = <&rcc GPIOB_CK>;
 579                                 st,bank-name = "GPIOB";
 580                                 interrupt-controller;
 581                                 #interrupt-cells = <2>;
 582                                 ngpios = <16>;
 583                                 gpio-ranges = <&pinctrl 0 16 16>;
 584                         };
 585
 586                         gpioc: gpio@58020800 {
 587                                 gpio-controller;
 588                                 #gpio-cells = <2>;
 589                                 reg = <0x800 0x400>;
 590                                 clocks = <&rcc GPIOC_CK>;
 591                                 st,bank-name = "GPIOC";
 592                                 interrupt-controller;
 593                                 #interrupt-cells = <2>;
 594                                 ngpios = <16>;
 595                                 gpio-ranges = <&pinctrl 0 32 16>;
 596                         };
 597
 598                         gpiod: gpio@58020c00 {
 599                                 gpio-controller;
 600                                 #gpio-cells = <2>;
 601                                 reg = <0xc00 0x400>;
 602                                 clocks = <&rcc GPIOD_CK>;
 603                                 st,bank-name = "GPIOD";
 604                                 interrupt-controller;
 605                                 #interrupt-cells = <2>;
 606                                 ngpios = <16>;
 607                                 gpio-ranges = <&pinctrl 0 48 16>;
 608                         };
 609
 610                         gpioe: gpio@58021000 {
 611                                 gpio-controller;
 612                                 #gpio-cells = <2>;
 613                                 reg = <0x1000 0x400>;
 614                                 clocks = <&rcc GPIOE_CK>;
 615                                 st,bank-name = "GPIOE";
 616                                 interrupt-controller;
 617                                 #interrupt-cells = <2>;
 618                                 ngpios = <16>;
 619                                 gpio-ranges = <&pinctrl 0 64 16>;
 620                         };
 621
 622                         gpiof: gpio@58021400 {
 623                                 gpio-controller;
 624                                 #gpio-cells = <2>;
 625                                 reg = <0x1400 0x400>;
 626                                 clocks = <&rcc GPIOF_CK>;
 627                                 st,bank-name = "GPIOF";
 628                                 interrupt-controller;
 629                                 #interrupt-cells = <2>;
 630                                 ngpios = <16>;
 631                                 gpio-ranges = <&pinctrl 0 80 16>;
 632                         };
 633
 634                         gpiog: gpio@58021800 {
 635                                 gpio-controller;
 636                                 #gpio-cells = <2>;
 637                                 reg = <0x1800 0x400>;
 638                                 clocks = <&rcc GPIOG_CK>;
 639                                 st,bank-name = "GPIOG";
 640                                 interrupt-controller;
 641                                 #interrupt-cells = <2>;
 642                                 ngpios = <16>;
 643                                 gpio-ranges = <&pinctrl 0 96 16>;
 644                         };
 645
 646                         gpioh: gpio@58021c00 {
 647                                 gpio-controller;
 648                                 #gpio-cells = <2>;
 649                                 reg = <0x1c00 0x400>;
 650                                 clocks = <&rcc GPIOH_CK>;
 651                                 st,bank-name = "GPIOH";
 652                                 interrupt-controller;
 653                                 #interrupt-cells = <2>;
 654                                 ngpios = <16>;
 655                                 gpio-ranges = <&pinctrl 0 112 16>;
 656                         };
 657
 658                         gpioi: gpio@58022000 {
 659                                 gpio-controller;
 660                                 #gpio-cells = <2>;
 661                                 reg = <0x2000 0x400>;
 662                                 clocks = <&rcc GPIOI_CK>;
 663                                 st,bank-name = "GPIOI";
 664                                 interrupt-controller;
 665                                 #interrupt-cells = <2>;
 666                                 ngpios = <16>;
 667                                 gpio-ranges = <&pinctrl 0 128 16>;
 668                         };
 669
 670                         gpioj: gpio@58022400 {
 671                                 gpio-controller;
 672                                 #gpio-cells = <2>;
 673                                 reg = <0x2400 0x400>;
 674                                 clocks = <&rcc GPIOJ_CK>;
 675                                 st,bank-name = "GPIOJ";
 676                                 interrupt-controller;
 677                                 #interrupt-cells = <2>;
 678                                 ngpios = <16>;
 679                                 gpio-ranges = <&pinctrl 0 144 16>;
 680                         };
 681
 682                         gpiok: gpio@58022800 {
 683                                 gpio-controller;
 684                                 #gpio-cells = <2>;
 685                                 reg = <0x2800 0x400>;
 686                                 clocks = <&rcc GPIOK_CK>;
 687                                 st,bank-name = "GPIOK";
 688                                 interrupt-controller;
 689                                 #interrupt-cells = <2>;
 690                                 ngpios = <8>;
 691                                 gpio-ranges = <&pinctrl 0 160 8>;
 692                         };
 693                 };
 694         };
 695 };
 696
 697 &systick {
 698         clock-frequency = <250000000>;
 699         status = "okay";
 700 };