arch/arm/dts/stm32h743.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
   4  *
   5  */
   6
   7 #include "armv7-m.dtsi"
   8 #include <dt-bindings/clock/stm32h7-clks.h>
   9 #include <dt-bindings/mfd/stm32h7-rcc.h>
  10 #include <dt-bindings/interrupt-controller/irq.h>
  11
  12 / {
  13         #address-cells = <1>;
  14         #size-cells = <1>;
  15
  16         clocks {
  17                 clk_hse: clk-hse {
  18                         #clock-cells = <0>;
  19                         compatible = "fixed-clock";
  20                         clock-frequency = <0>;
  21                 };
  22
  23                 clk_lse: clk-lse {
  24                         #clock-cells = <0>;
  25                         compatible = "fixed-clock";
  26                         clock-frequency = <32768>;
  27                 };
  28
  29                 clk_i2s: i2s_ckin {
  30                         #clock-cells = <0>;
  31                         compatible = "fixed-clock";
  32                         clock-frequency = <0>;
  33                 };
  34         };
  35
  36         soc {
  37                 timer5: timer@40000c00 {
  38                         compatible = "st,stm32-timer";
  39                         reg = <0x40000c00 0x400>;
  40                         interrupts = <50>;
  41                         clocks = <&rcc TIM5_CK>;
  42                 };
  43
  44                 lptimer1: timer@40002400 {
  45                         #address-cells = <1>;
  46                         #size-cells = <0>;
  47                         compatible = "st,stm32-lptimer";
  48                         reg = <0x40002400 0x400>;
  49                         clocks = <&rcc LPTIM1_CK>;
  50                         clock-names = "mux";
  51                         status = "disabled";
  52
  53                         pwm {
  54                                 compatible = "st,stm32-pwm-lp";
  55                                 #pwm-cells = <3>;
  56                                 status = "disabled";
  57                         };
  58
  59                         trigger@0 {
  60                                 compatible = "st,stm32-lptimer-trigger";
  61                                 reg = <0>;
  62                                 status = "disabled";
  63                         };
  64
  65                         counter {
  66                                 compatible = "st,stm32-lptimer-counter";
  67                                 status = "disabled";
  68                         };
  69                 };
  70
  71                 spi2: spi@40003800 {
  72                         #address-cells = <1>;
  73                         #size-cells = <0>;
  74                         compatible = "st,stm32h7-spi";
  75                         reg = <0x40003800 0x400>;
  76                         interrupts = <36>;
  77                         clocks = <&rcc SPI2_CK>;
  78                         status = "disabled";
  79
  80                 };
  81
  82                 spi3: spi@40003c00 {
  83                         #address-cells = <1>;
  84                         #size-cells = <0>;
  85                         compatible = "st,stm32h7-spi";
  86                         reg = <0x40003c00 0x400>;
  87                         interrupts = <51>;
  88                         clocks = <&rcc SPI3_CK>;
  89                         status = "disabled";
  90                 };
  91
  92                 usart2: serial@40004400 {
  93                         compatible = "st,stm32f7-uart";
  94                         reg = <0x40004400 0x400>;
  95                         interrupts = <38>;
  96                         status = "disabled";
  97                         clocks = <&rcc USART2_CK>;
  98                 };
  99
 100                 i2c1: i2c@40005400 {
 101                         compatible = "st,stm32f7-i2c";
 102                         #address-cells = <1>;
 103                         #size-cells = <0>;
 104                         reg = <0x40005400 0x400>;
 105                         interrupts = <31>,
 106                                      <32>;
 107                         resets = <&rcc STM32H7_APB1L_RESET(I2C1)>;
 108                         clocks = <&rcc I2C1_CK>;
 109                         status = "disabled";
 110                 };
 111
 112                 i2c2: i2c@40005800 {
 113                         compatible = "st,stm32f7-i2c";
 114                         #address-cells = <1>;
 115                         #size-cells = <0>;
 116                         reg = <0x40005800 0x400>;
 117                         interrupts = <33>,
 118                                      <34>;
 119                         resets = <&rcc STM32H7_APB1L_RESET(I2C2)>;
 120                         clocks = <&rcc I2C2_CK>;
 121                         status = "disabled";
 122                 };
 123
 124                 i2c3: i2c@40005C00 {
 125                         compatible = "st,stm32f7-i2c";
 126                         #address-cells = <1>;
 127                         #size-cells = <0>;
 128                         reg = <0x40005C00 0x400>;
 129                         interrupts = <72>,
 130                                      <73>;
 131                         resets = <&rcc STM32H7_APB1L_RESET(I2C3)>;
 132                         clocks = <&rcc I2C3_CK>;
 133                         status = "disabled";
 134                 };
 135
 136                 dac: dac@40007400 {
 137                         compatible = "st,stm32h7-dac-core";
 138                         reg = <0x40007400 0x400>;
 139                         clocks = <&rcc DAC12_CK>;
 140                         clock-names = "pclk";
 141                         #address-cells = <1>;
 142                         #size-cells = <0>;
 143                         status = "disabled";
 144
 145                         dac1: dac@1 {
 146                                 compatible = "st,stm32-dac";
 147                                 #io-channels-cells = <1>;
 148                                 reg = <1>;
 149                                 status = "disabled";
 150                         };
 151
 152                         dac2: dac@2 {
 153                                 compatible = "st,stm32-dac";
 154                                 #io-channels-cells = <1>;
 155                                 reg = <2>;
 156                                 status = "disabled";
 157                         };
 158                 };
 159
 160                 usart1: serial@40011000 {
 161                         compatible = "st,stm32f7-uart";
 162                         reg = <0x40011000 0x400>;
 163                         interrupts = <37>;
 164                         status = "disabled";
 165                         clocks = <&rcc USART1_CK>;
 166                 };
 167
 168                 spi1: spi@40013000 {
 169                         #address-cells = <1>;
 170                         #size-cells = <0>;
 171                         compatible = "st,stm32h7-spi";
 172                         reg = <0x40013000 0x400>;
 173                         interrupts = <35>;
 174                         clocks = <&rcc SPI1_CK>;
 175                         status = "disabled";
 176                 };
 177
 178                 spi4: spi@40013400 {
 179                         #address-cells = <1>;
 180                         #size-cells = <0>;
 181                         compatible = "st,stm32h7-spi";
 182                         reg = <0x40013400 0x400>;
 183                         interrupts = <84>;
 184                         clocks = <&rcc SPI4_CK>;
 185                         status = "disabled";
 186                 };
 187
 188                 spi5: spi@40015000 {
 189                         #address-cells = <1>;
 190                         #size-cells = <0>;
 191                         compatible = "st,stm32h7-spi";
 192                         reg = <0x40015000 0x400>;
 193                         interrupts = <85>;
 194                         clocks = <&rcc SPI5_CK>;
 195                         status = "disabled";
 196                 };
 197
 198                 dma1: dma@40020000 {
 199                         compatible = "st,stm32-dma";
 200                         reg = <0x40020000 0x400>;
 201                         interrupts = <11>,
 202                                      <12>,
 203                                      <13>,
 204                                      <14>,
 205                                      <15>,
 206                                      <16>,
 207                                      <17>,
 208                                      <47>;
 209                         clocks = <&rcc DMA1_CK>;
 210                         #dma-cells = <4>;
 211                         st,mem2mem;
 212                         dma-requests = <8>;
 213                         status = "disabled";
 214                 };
 215
 216                 dma2: dma@40020400 {
 217                         compatible = "st,stm32-dma";
 218                         reg = <0x40020400 0x400>;
 219                         interrupts = <56>,
 220                                      <57>,
 221                                      <58>,
 222                                      <59>,
 223                                      <60>,
 224                                      <68>,
 225                                      <69>,
 226                                      <70>;
 227                         clocks = <&rcc DMA2_CK>;
 228                         #dma-cells = <4>;
 229                         st,mem2mem;
 230                         dma-requests = <8>;
 231                         status = "disabled";
 232                 };
 233
 234                 dmamux1: dma-router@40020800 {
 235                         compatible = "st,stm32h7-dmamux";
 236                         reg = <0x40020800 0x1c>;
 237                         #dma-cells = <3>;
 238                         dma-channels = <16>;
 239                         dma-requests = <128>;
 240                         dma-masters = <&dma1 &dma2>;
 241                         clocks = <&rcc DMA1_CK>;
 242                 };
 243
 244                 adc_12: adc@40022000 {
 245                         compatible = "st,stm32h7-adc-core";
 246                         reg = <0x40022000 0x400>;
 247                         interrupts = <18>;
 248                         clocks = <&rcc ADC12_CK>;
 249                         clock-names = "bus";
 250                         interrupt-controller;
 251                         #interrupt-cells = <1>;
 252                         #address-cells = <1>;
 253                         #size-cells = <0>;
 254                         status = "disabled";
 255
 256                         adc1: adc@0 {
 257                                 compatible = "st,stm32h7-adc";
 258                                 #io-channel-cells = <1>;
 259                                 reg = <0x0>;
 260                                 interrupt-parent = <&adc_12>;
 261                                 interrupts = <0>;
 262                                 status = "disabled";
 263                         };
 264
 265                         adc2: adc@100 {
 266                                 compatible = "st,stm32h7-adc";
 267                                 #io-channel-cells = <1>;
 268                                 reg = <0x100>;
 269                                 interrupt-parent = <&adc_12>;
 270                                 interrupts = <1>;
 271                                 status = "disabled";
 272                         };
 273                 };
 274
 275                 usbotg_hs: usb@40040000 {
 276                         compatible = "st,stm32f7-hsotg";
 277                         reg = <0x40040000 0x40000>;
 278                         interrupts = <77>;
 279                         clocks = <&rcc USB1OTG_CK>;
 280                         clock-names = "otg";
 281                         g-rx-fifo-size = <256>;
 282                         g-np-tx-fifo-size = <32>;
 283                         g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
 284                         status = "disabled";
 285                 };
 286
 287                 usbotg_fs: usb@40080000 {
 288                         compatible = "st,stm32f4x9-fsotg";
 289                         reg = <0x40080000 0x40000>;
 290                         interrupts = <101>;
 291                         clocks = <&rcc USB2OTG_CK>;
 292                         clock-names = "otg";
 293                         status = "disabled";
 294                 };
 295
 296                 mdma1: dma@52000000 {
 297                         compatible = "st,stm32h7-mdma";
 298                         reg = <0x52000000 0x1000>;
 299                         interrupts = <122>;
 300                         clocks = <&rcc MDMA_CK>;
 301                         #dma-cells = <5>;
 302                         dma-channels = <16>;
 303                         dma-requests = <32>;
 304                 };
 305
 306                 sdmmc1: sdmmc@52007000 {
 307                         compatible = "arm,pl18x", "arm,primecell";
 308                         arm,primecell-periphid = <0x10153180>;
 309                         reg = <0x52007000 0x1000>;
 310                         interrupts = <49>;
 311                         interrupt-names = "cmd_irq";
 312                         clocks = <&rcc SDMMC1_CK>;
 313                         clock-names = "apb_pclk";
 314                         resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>;
 315                         cap-sd-highspeed;
 316                         cap-mmc-highspeed;
 317                         max-frequency = <120000000>;
 318                 };
 319
 320                 exti: interrupt-controller@58000000 {
 321                         compatible = "st,stm32h7-exti";
 322                         interrupt-controller;
 323                         #interrupt-cells = <2>;
 324                         reg = <0x58000000 0x400>;
 325                         interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <62>, <76>;
 326                 };
 327
 328                 syscfg: system-config@58000400 {
 329                         compatible = "syscon";
 330                         reg = <0x58000400 0x400>;
 331                 };
 332
 333                 spi6: spi@58001400 {
 334                         #address-cells = <1>;
 335                         #size-cells = <0>;
 336                         compatible = "st,stm32h7-spi";
 337                         reg = <0x58001400 0x400>;
 338                         interrupts = <86>;
 339                         clocks = <&rcc SPI6_CK>;
 340                         status = "disabled";
 341                 };
 342
 343                 i2c4: i2c@58001C00 {
 344                         compatible = "st,stm32f7-i2c";
 345                         #address-cells = <1>;
 346                         #size-cells = <0>;
 347                         reg = <0x58001C00 0x400>;
 348                         interrupts = <95>,
 349                                      <96>;
 350                         resets = <&rcc STM32H7_APB4_RESET(I2C4)>;
 351                         clocks = <&rcc I2C4_CK>;
 352                         status = "disabled";
 353                 };
 354
 355                 lptimer2: timer@58002400 {
 356                         #address-cells = <1>;
 357                         #size-cells = <0>;
 358                         compatible = "st,stm32-lptimer";
 359                         reg = <0x58002400 0x400>;
 360                         clocks = <&rcc LPTIM2_CK>;
 361                         clock-names = "mux";
 362                         status = "disabled";
 363
 364                         pwm {
 365                                 compatible = "st,stm32-pwm-lp";
 366                                 #pwm-cells = <3>;
 367                                 status = "disabled";
 368                         };
 369
 370                         trigger@1 {
 371                                 compatible = "st,stm32-lptimer-trigger";
 372                                 reg = <1>;
 373                                 status = "disabled";
 374                         };
 375
 376                         counter {
 377                                 compatible = "st,stm32-lptimer-counter";
 378                                 status = "disabled";
 379                         };
 380                 };
 381
 382                 lptimer3: timer@58002800 {
 383                         #address-cells = <1>;
 384                         #size-cells = <0>;
 385                         compatible = "st,stm32-lptimer";
 386                         reg = <0x58002800 0x400>;
 387                         clocks = <&rcc LPTIM3_CK>;
 388                         clock-names = "mux";
 389                         status = "disabled";
 390
 391                         pwm {
 392                                 compatible = "st,stm32-pwm-lp";
 393                                 #pwm-cells = <3>;
 394                                 status = "disabled";
 395                         };
 396
 397                         trigger@2 {
 398                                 compatible = "st,stm32-lptimer-trigger";
 399                                 reg = <2>;
 400                                 status = "disabled";
 401                         };
 402                 };
 403
 404                 lptimer4: timer@58002c00 {
 405                         #address-cells = <1>;
 406                         #size-cells = <0>;
 407                         compatible = "st,stm32-lptimer";
 408                         reg = <0x58002c00 0x400>;
 409                         clocks = <&rcc LPTIM4_CK>;
 410                         clock-names = "mux";
 411                         status = "disabled";
 412
 413                         pwm {
 414                                 compatible = "st,stm32-pwm-lp";
 415                                 #pwm-cells = <3>;
 416                                 status = "disabled";
 417                         };
 418                 };
 419
 420                 lptimer5: timer@58003000 {
 421                         #address-cells = <1>;
 422                         #size-cells = <0>;
 423                         compatible = "st,stm32-lptimer";
 424                         reg = <0x58003000 0x400>;
 425                         clocks = <&rcc LPTIM5_CK>;
 426                         clock-names = "mux";
 427                         status = "disabled";
 428
 429                         pwm {
 430                                 compatible = "st,stm32-pwm-lp";
 431                                 #pwm-cells = <3>;
 432                                 status = "disabled";
 433                         };
 434                 };
 435
 436                 vrefbuf: regulator@58003c00 {
 437                         compatible = "st,stm32-vrefbuf";
 438                         reg = <0x58003C00 0x8>;
 439                         clocks = <&rcc VREF_CK>;
 440                         regulator-min-microvolt = <1500000>;
 441                         regulator-max-microvolt = <2500000>;
 442                         status = "disabled";
 443                 };
 444
 445                 rtc: rtc@58004000 {
 446                         compatible = "st,stm32h7-rtc";
 447                         reg = <0x58004000 0x400>;
 448                         clocks = <&rcc RTCAPB_CK>, <&rcc RTC_CK>;
 449                         clock-names = "pclk", "rtc_ck";
 450                         assigned-clocks = <&rcc RTC_CK>;
 451                         assigned-clock-parents = <&rcc LSE_CK>;
 452                         interrupt-parent = <&exti>;
 453                         interrupts = <17 IRQ_TYPE_EDGE_RISING>;
 454                         interrupt-names = "alarm";
 455                         st,syscfg = <&pwrcfg 0x00 0x100>;
 456                         status = "disabled";
 457                 };
 458
 459                 rcc: reset-clock-controller@58024400 {
 460                         compatible = "st,stm32h743-rcc", "st,stm32-rcc";
 461                         reg = <0x58024400 0x400>;
 462                         #clock-cells = <1>;
 463                         #reset-cells = <1>;
 464                         clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>;
 465                         st,syscfg = <&pwrcfg>;
 466                 };
 467
 468                 pwrcfg: power-config@58024800 {
 469                         compatible = "syscon";
 470                         reg = <0x58024800 0x400>;
 471                 };
 472
 473                 adc_3: adc@58026000 {
 474                         compatible = "st,stm32h7-adc-core";
 475                         reg = <0x58026000 0x400>;
 476                         interrupts = <127>;
 477                         clocks = <&rcc ADC3_CK>;
 478                         clock-names = "bus";
 479                         interrupt-controller;
 480                         #interrupt-cells = <1>;
 481                         #address-cells = <1>;
 482                         #size-cells = <0>;
 483                         status = "disabled";
 484
 485                         adc3: adc@0 {
 486                                 compatible = "st,stm32h7-adc";
 487                                 #io-channel-cells = <1>;
 488                                 reg = <0x0>;
 489                                 interrupt-parent = <&adc_3>;
 490                                 interrupts = <0>;
 491                                 status = "disabled";
 492                         };
 493                 };
 494
 495                 mac: ethernet@40028000 {
 496                         compatible = "st,stm32-dwmac", "snps,dwmac-4.10a";
 497                         reg = <0x40028000 0x8000>;
 498                         reg-names = "stmmaceth";
 499                         interrupts = <61>;
 500                         interrupt-names = "macirq";
 501                         clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
 502                         clocks = <&rcc ETH1MAC_CK>, <&rcc ETH1TX_CK>, <&rcc ETH1RX_CK>;
 503                         st,syscon = <&syscfg 0x4>;
 504                         snps,pbl = <8>;
 505                         status = "disabled";
 506                 };
 507         };
 508 };
 509
 510 &systick {
 511         clock-frequency = <250000000>;
 512         status = "okay";
 513 };