arch/arm/dts/stm32f769-disco-u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2
   3 #include <stm32f7-u-boot.dtsi>
   4 /{
   5         chosen {
   6                 bootargs = "root=/dev/ram rdinit=/linuxrc";
   7         };
   8
   9         aliases {
  10                 /* Aliases for gpios so as to use sequence */
  11                 gpio0 = &gpioa;
  12                 gpio1 = &gpiob;
  13                 gpio2 = &gpioc;
  14                 gpio3 = &gpiod;
  15                 gpio4 = &gpioe;
  16                 gpio5 = &gpiof;
  17                 gpio6 = &gpiog;
  18                 gpio7 = &gpioh;
  19                 gpio8 = &gpioi;
  20                 gpio9 = &gpioj;
  21                 gpio10 = &gpiok;
  22                 mmc0 = &sdio2;
  23                 spi0 = &qspi;
  24         };
  25
  26         button1 {
  27                 compatible = "st,button1";
  28                 button-gpio = <&gpioa 0 0>;
  29         };
  30
  31         dsi_host: dsi_host {
  32                 compatible = "synopsys,dw-mipi-dsi";
  33                 status = "okay";
  34         };
  35
  36         led1 {
  37                 compatible = "st,led1";
  38                 led-gpio = <&gpioj 5 0>;
  39         };
  40
  41         panel: panel {
  42                 compatible = "orisetech,otm8009a";
  43                 reset-gpios = <&gpioj 15 1>;
  44                 status = "okay";
  45
  46                 port {
  47                         panel_in: endpoint {
  48                                 remote-endpoint = <&dsi_out>;
  49                         };
  50                 };
  51         };
  52
  53         soc {
  54                 dsi: dsi@40016c00 {
  55                         compatible = "st,stm32-dsi";
  56                         reg = <0x40016C00 0x800>;
  57                         resets = <&rcc STM32F7_APB2_RESET(DSI)>;
  58                         clocks =  <&rcc 0 STM32F7_APB2_CLOCK(DSI)>,
  59                                   <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>,
  60                                   <&clk_hse>;
  61                         clock-names = "pclk", "px_clk", "ref";
  62                         u-boot,dm-pre-reloc;
  63                         status = "okay";
  64
  65                         ports {
  66                                 port@0 {
  67                                         dsi_out: endpoint {
  68                                                 remote-endpoint = <&panel_in>;
  69                                         };
  70                                 };
  71                                 port@1 {
  72                                         dsi_in: endpoint {
  73                                                 remote-endpoint = <&dp_out>;
  74                                         };
  75                                 };
  76                         };
  77                 };
  78
  79                 ltdc: display-controller@40016800 {
  80                         compatible = "st,stm32-ltdc";
  81                         reg = <0x40016800 0x200>;
  82                         resets = <&rcc STM32F7_APB2_RESET(LTDC)>;
  83                         clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>;
  84
  85                         status = "okay";
  86                         u-boot,dm-pre-reloc;
  87
  88                         ports {
  89                                 port@0 {
  90                                         dp_out: endpoint {
  91                                                 remote-endpoint = <&dsi_in>;
  92                                         };
  93                                 };
  94                         };
  95                 };
  96         };
  97 };
  98
  99 &fmc {
 100         /* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */
 101         bank1: bank@0 {
 102                 u-boot,dm-pre-reloc;
 103                 st,sdram-control = /bits/ 8 <NO_COL_8
 104                                              NO_ROW_12
 105                                              MWIDTH_32
 106                                              BANKS_4
 107                                              CAS_3
 108                                              SDCLK_2
 109                                              RD_BURST_EN
 110                                              RD_PIPE_DL_0>;
 111                 st,sdram-timing = /bits/ 8 <TMRD_2
 112                                             TXSR_6
 113                                             TRAS_4
 114                                             TRC_6
 115                                             TWR_2
 116                                             TRP_2
 117                                             TRCD_2>;
 118                 /* refcount = (64msec/total_row_sdram)*freq - 20 */
 119                 st,sdram-refcount = < 1542 >;
 120         };
 121 };
 122
 123 &pinctrl {
 124         ethernet_mii: mii@0 {
 125                 pins {
 126                         pinmux = <STM32_PINMUX('G',13, AF11)>, /* ETH_RMII_TXD0 */
 127                                  <STM32_PINMUX('G',14, AF11)>, /* ETH_RMII_TXD1 */
 128                                  <STM32_PINMUX('G',11, AF11)>, /* ETH_RMII_TX_EN */
 129                                  <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
 130                                  <STM32_PINMUX('C', 1, AF11)>, /* ETH_MDC */
 131                                  <STM32_PINMUX('A', 1, AF11)>, /* ETH_RMII_REF_CLK */
 132                                  <STM32_PINMUX('A', 7, AF11)>, /* ETH_RMII_CRS_DV */
 133                                  <STM32_PINMUX('C', 4, AF11)>, /* ETH_RMII_RXD0 */
 134                                  <STM32_PINMUX('C', 5, AF11)>; /* ETH_RMII_RXD1 */
 135                         slew-rate = <2>;
 136                 };
 137         };
 138
 139         fmc_pins: fmc@0 {
 140                 pins {
 141                         pinmux = <STM32_PINMUX('I',10, AF12)>, /* D31 */
 142                                  <STM32_PINMUX('I', 9, AF12)>, /* D30 */
 143                                  <STM32_PINMUX('I', 7, AF12)>, /* D29 */
 144                                  <STM32_PINMUX('I', 6, AF12)>, /* D28 */
 145                                  <STM32_PINMUX('I', 3, AF12)>, /* D27 */
 146                                  <STM32_PINMUX('I', 2, AF12)>, /* D26 */
 147                                  <STM32_PINMUX('I', 1, AF12)>, /* D25 */
 148                                  <STM32_PINMUX('I', 0, AF12)>, /* D24 */
 149                                  <STM32_PINMUX('H',15, AF12)>, /* D23 */
 150                                  <STM32_PINMUX('H',14, AF12)>, /* D22 */
 151                                  <STM32_PINMUX('H',13, AF12)>, /* D21 */
 152                                  <STM32_PINMUX('H',12, AF12)>, /* D20 */
 153                                  <STM32_PINMUX('H',11, AF12)>, /* D19 */
 154                                  <STM32_PINMUX('H',10, AF12)>, /* D18 */
 155                                  <STM32_PINMUX('H', 9, AF12)>, /* D17 */
 156                                  <STM32_PINMUX('H', 8, AF12)>, /* D16 */
 157
 158                                  <STM32_PINMUX('D',10, AF12)>, /* D15 */
 159                                  <STM32_PINMUX('D', 9, AF12)>, /* D14 */
 160                                  <STM32_PINMUX('D', 8, AF12)>, /* D13 */
 161                                  <STM32_PINMUX('E',15, AF12)>, /* D12 */
 162                                  <STM32_PINMUX('E',14, AF12)>, /* D11 */
 163                                  <STM32_PINMUX('E',13, AF12)>, /* D10 */
 164                                  <STM32_PINMUX('E',12, AF12)>, /* D9 */
 165                                  <STM32_PINMUX('E',11, AF12)>, /* D8 */
 166                                  <STM32_PINMUX('E',10, AF12)>, /* D7 */
 167                                  <STM32_PINMUX('E', 9, AF12)>, /* D6 */
 168                                  <STM32_PINMUX('E', 8, AF12)>, /* D5 */
 169                                  <STM32_PINMUX('E', 7, AF12)>, /* D4 */
 170                                  <STM32_PINMUX('D', 1, AF12)>, /* D3 */
 171                                  <STM32_PINMUX('D', 0, AF12)>, /* D2 */
 172                                  <STM32_PINMUX('D',15, AF12)>, /* D1 */
 173                                  <STM32_PINMUX('D',14, AF12)>, /* D0 */
 174
 175                                  <STM32_PINMUX('I', 5, AF12)>, /* NBL3 */
 176                                  <STM32_PINMUX('I', 4, AF12)>, /* NBL2 */
 177                                  <STM32_PINMUX('E', 1, AF12)>, /* NBL1 */
 178                                  <STM32_PINMUX('E', 0, AF12)>, /* NBL0 */
 179
 180                                  <STM32_PINMUX('G', 5, AF12)>, /* BA1 */
 181                                  <STM32_PINMUX('G', 4, AF12)>, /* BA0 */
 182
 183                                  <STM32_PINMUX('G', 1, AF12)>, /* A11 */
 184                                  <STM32_PINMUX('G', 0, AF12)>, /* A10 */
 185                                  <STM32_PINMUX('F',15, AF12)>, /* A9 */
 186                                  <STM32_PINMUX('F',14, AF12)>, /* A8 */
 187                                  <STM32_PINMUX('F',13, AF12)>, /* A7 */
 188                                  <STM32_PINMUX('F',12, AF12)>, /* A6 */
 189                                  <STM32_PINMUX('F', 5, AF12)>, /* A5 */
 190                                  <STM32_PINMUX('F', 4, AF12)>, /* A4 */
 191                                  <STM32_PINMUX('F', 3, AF12)>, /* A3 */
 192                                  <STM32_PINMUX('F', 2, AF12)>, /* A2 */
 193                                  <STM32_PINMUX('F', 1, AF12)>, /* A1 */
 194                                  <STM32_PINMUX('F', 0, AF12)>, /* A0 */
 195
 196                                  <STM32_PINMUX('H', 3, AF12)>, /* SDNE0 */
 197                                  <STM32_PINMUX('H', 5, AF12)>, /* SDNWE */
 198                                  <STM32_PINMUX('F',11, AF12)>, /* SDNRAS */
 199                                  <STM32_PINMUX('G',15, AF12)>, /* SDNCAS */
 200                                  <STM32_PINMUX('H', 2, AF12)>, /* SDCKE0 */
 201                                  <STM32_PINMUX('G', 8, AF12)>; /* SDCLK> */
 202                         slew-rate = <2>;
 203                 };
 204         };
 205
 206         qspi_pins: qspi@0 {
 207                 pins {
 208                         pinmux = <STM32_PINMUX('B', 2, AF9)>, /* CLK */
 209                                  <STM32_PINMUX('B', 6, AF10)>, /* BK1_NCS */
 210                                  <STM32_PINMUX('C', 9, AF9)>, /* BK1_IO0 */
 211                                  <STM32_PINMUX('C',10, AF9)>, /* BK1_IO1 */
 212                                  <STM32_PINMUX('D',13, AF9)>, /* BK1_IO3 */
 213                                  <STM32_PINMUX('E', 2, AF9)>; /* BK1_IO2 */
 214                         slew-rate = <2>;
 215                 };
 216         };
 217
 218         usart1_pins_a: usart1@0 {
 219                 u-boot,dm-pre-reloc;
 220                 pins1 {
 221                         u-boot,dm-pre-reloc;
 222                 };
 223                 pins2 {
 224                         u-boot,dm-pre-reloc;
 225                 };
 226         };
 227 };
 228
 229 &qspi {
 230         reg = <0xA0001000 0x1000>, <0x90000000 0x4000000>;
 231         flash0: mx66l51235l {
 232                 #address-cells = <1>;
 233                 #size-cells = <1>;
 234                 compatible = "jedec,spi-nor";
 235                 spi-max-frequency = <108000000>;
 236                 spi-tx-bus-width = <4>;
 237                 spi-rx-bus-width = <4>;
 238                 reg = <0>;
 239         };
 240 };