arch/arm/dts/stm32f746.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
   4  *
   5  */
   6
   7 #include "armv7-m.dtsi"
   8 #include <dt-bindings/clock/stm32fx-clock.h>
   9 #include <dt-bindings/mfd/stm32f7-rcc.h>
  10
  11 / {
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14
  15         clocks {
  16                 clk_hse: clk-hse {
  17                         #clock-cells = <0>;
  18                         compatible = "fixed-clock";
  19                         clock-frequency = <0>;
  20                 };
  21
  22                 clk-lse {
  23                         #clock-cells = <0>;
  24                         compatible = "fixed-clock";
  25                         clock-frequency = <32768>;
  26                 };
  27
  28                 clk-lsi {
  29                         #clock-cells = <0>;
  30                         compatible = "fixed-clock";
  31                         clock-frequency = <32000>;
  32                 };
  33
  34                 clk_i2s_ckin: clk-i2s-ckin {
  35                         #clock-cells = <0>;
  36                         compatible = "fixed-clock";
  37                         clock-frequency = <48000000>;
  38                 };
  39         };
  40
  41         soc {
  42                 timers2: timers@40000000 {
  43                         #address-cells = <1>;
  44                         #size-cells = <0>;
  45                         compatible = "st,stm32-timers";
  46                         reg = <0x40000000 0x400>;
  47                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
  48                         clock-names = "int";
  49                         status = "disabled";
  50
  51                         pwm {
  52                                 compatible = "st,stm32-pwm";
  53                                 #pwm-cells = <3>;
  54                                 status = "disabled";
  55                         };
  56
  57                         timer@1 {
  58                                 compatible = "st,stm32-timer-trigger";
  59                                 reg = <1>;
  60                                 status = "disabled";
  61                         };
  62                 };
  63
  64                 timers3: timers@40000400 {
  65                         #address-cells = <1>;
  66                         #size-cells = <0>;
  67                         compatible = "st,stm32-timers";
  68                         reg = <0x40000400 0x400>;
  69                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
  70                         clock-names = "int";
  71                         status = "disabled";
  72
  73                         pwm {
  74                                 compatible = "st,stm32-pwm";
  75                                 #pwm-cells = <3>;
  76                                 status = "disabled";
  77                         };
  78
  79                         timer@2 {
  80                                 compatible = "st,stm32-timer-trigger";
  81                                 reg = <2>;
  82                                 status = "disabled";
  83                         };
  84                 };
  85
  86                 timers4: timers@40000800 {
  87                         #address-cells = <1>;
  88                         #size-cells = <0>;
  89                         compatible = "st,stm32-timers";
  90                         reg = <0x40000800 0x400>;
  91                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
  92                         clock-names = "int";
  93                         status = "disabled";
  94
  95                         pwm {
  96                                 compatible = "st,stm32-pwm";
  97                                 #pwm-cells = <3>;
  98                                 status = "disabled";
  99                         };
 100
 101                         timer@3 {
 102                                 compatible = "st,stm32-timer-trigger";
 103                                 reg = <3>;
 104                                 status = "disabled";
 105                         };
 106                 };
 107
 108                 timers5: timers@40000c00 {
 109                         #address-cells = <1>;
 110                         #size-cells = <0>;
 111                         compatible = "st,stm32-timers";
 112                         reg = <0x40000C00 0x400>;
 113                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
 114                         clock-names = "int";
 115                         status = "disabled";
 116
 117                         pwm {
 118                                 compatible = "st,stm32-pwm";
 119                                 #pwm-cells = <3>;
 120                                 status = "disabled";
 121                         };
 122
 123                         timer@4 {
 124                                 compatible = "st,stm32-timer-trigger";
 125                                 reg = <4>;
 126                                 status = "disabled";
 127                         };
 128                 };
 129
 130                 timers6: timers@40001000 {
 131                         #address-cells = <1>;
 132                         #size-cells = <0>;
 133                         compatible = "st,stm32-timers";
 134                         reg = <0x40001000 0x400>;
 135                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
 136                         clock-names = "int";
 137                         status = "disabled";
 138
 139                         timer@5 {
 140                                 compatible = "st,stm32-timer-trigger";
 141                                 reg = <5>;
 142                                 status = "disabled";
 143                         };
 144                 };
 145
 146                 timers7: timers@40001400 {
 147                         #address-cells = <1>;
 148                         #size-cells = <0>;
 149                         compatible = "st,stm32-timers";
 150                         reg = <0x40001400 0x400>;
 151                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
 152                         clock-names = "int";
 153                         status = "disabled";
 154
 155                         timer@6 {
 156                                 compatible = "st,stm32-timer-trigger";
 157                                 reg = <6>;
 158                                 status = "disabled";
 159                         };
 160                 };
 161
 162                 timers12: timers@40001800 {
 163                         #address-cells = <1>;
 164                         #size-cells = <0>;
 165                         compatible = "st,stm32-timers";
 166                         reg = <0x40001800 0x400>;
 167                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>;
 168                         clock-names = "int";
 169                         status = "disabled";
 170
 171                         pwm {
 172                                 compatible = "st,stm32-pwm";
 173                                 #pwm-cells = <3>;
 174                                 status = "disabled";
 175                         };
 176
 177                         timer@11 {
 178                                 compatible = "st,stm32-timer-trigger";
 179                                 reg = <11>;
 180                                 status = "disabled";
 181                         };
 182                 };
 183
 184                 timers13: timers@40001c00 {
 185                         compatible = "st,stm32-timers";
 186                         reg = <0x40001C00 0x400>;
 187                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
 188                         clock-names = "int";
 189                         status = "disabled";
 190
 191                         pwm {
 192                                 compatible = "st,stm32-pwm";
 193                                 #pwm-cells = <3>;
 194                                 status = "disabled";
 195                         };
 196                 };
 197
 198                 timers14: timers@40002000 {
 199                         compatible = "st,stm32-timers";
 200                         reg = <0x40002000 0x400>;
 201                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
 202                         clock-names = "int";
 203                         status = "disabled";
 204
 205                         pwm {
 206                                 compatible = "st,stm32-pwm";
 207                                 #pwm-cells = <3>;
 208                                 status = "disabled";
 209                         };
 210                 };
 211
 212                 rtc: rtc@40002800 {
 213                         compatible = "st,stm32-rtc";
 214                         reg = <0x40002800 0x400>;
 215                         clocks = <&rcc 1 CLK_RTC>;
 216                         assigned-clocks = <&rcc 1 CLK_RTC>;
 217                         assigned-clock-parents = <&rcc 1 CLK_LSE>;
 218                         interrupt-parent = <&exti>;
 219                         interrupts = <17 1>;
 220                         st,syscfg = <&pwrcfg 0x00 0x100>;
 221                         status = "disabled";
 222                 };
 223
 224                 usart2: serial@40004400 {
 225                         compatible = "st,stm32f7-uart";
 226                         reg = <0x40004400 0x400>;
 227                         interrupts = <38>;
 228                         clocks = <&rcc 1 CLK_USART2>;
 229                         status = "disabled";
 230                 };
 231
 232                 usart3: serial@40004800 {
 233                         compatible = "st,stm32f7-uart";
 234                         reg = <0x40004800 0x400>;
 235                         interrupts = <39>;
 236                         clocks = <&rcc 1 CLK_USART3>;
 237                         status = "disabled";
 238                 };
 239
 240                 usart4: serial@40004c00 {
 241                         compatible = "st,stm32f7-uart";
 242                         reg = <0x40004c00 0x400>;
 243                         interrupts = <52>;
 244                         clocks = <&rcc 1 CLK_UART4>;
 245                         status = "disabled";
 246                 };
 247
 248                 usart5: serial@40005000 {
 249                         compatible = "st,stm32f7-uart";
 250                         reg = <0x40005000 0x400>;
 251                         interrupts = <53>;
 252                         clocks = <&rcc 1 CLK_UART5>;
 253                         status = "disabled";
 254                 };
 255
 256                 i2c1: i2c@40005400 {
 257                         compatible = "st,stm32f7-i2c";
 258                         reg = <0x40005400 0x400>;
 259                         interrupts = <31>,
 260                                      <32>;
 261                         resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
 262                         clocks = <&rcc 1 CLK_I2C1>;
 263                         #address-cells = <1>;
 264                         #size-cells = <0>;
 265                         status = "disabled";
 266                 };
 267
 268                 i2c2: i2c@40005800 {
 269                         compatible = "st,stm32f7-i2c";
 270                         reg = <0x40005800 0x400>;
 271                         interrupts = <33>,
 272                                      <34>;
 273                         resets = <&rcc STM32F7_APB1_RESET(I2C2)>;
 274                         clocks = <&rcc 1 CLK_I2C2>;
 275                         #address-cells = <1>;
 276                         #size-cells = <0>;
 277                         status = "disabled";
 278                 };
 279
 280                 i2c3: i2c@40005c00 {
 281                         compatible = "st,stm32f7-i2c";
 282                         reg = <0x40005c00 0x400>;
 283                         interrupts = <72>,
 284                                      <73>;
 285                         resets = <&rcc STM32F7_APB1_RESET(I2C3)>;
 286                         clocks = <&rcc 1 CLK_I2C3>;
 287                         #address-cells = <1>;
 288                         #size-cells = <0>;
 289                         status = "disabled";
 290                 };
 291
 292                 i2c4: i2c@40006000 {
 293                         compatible = "st,stm32f7-i2c";
 294                         reg = <0x40006000 0x400>;
 295                         interrupts = <95>,
 296                                      <96>;
 297                         resets = <&rcc STM32F7_APB1_RESET(I2C4)>;
 298                         clocks = <&rcc 1 CLK_I2C4>;
 299                         #address-cells = <1>;
 300                         #size-cells = <0>;
 301                         status = "disabled";
 302                 };
 303
 304                 cec: cec@40006c00 {
 305                         compatible = "st,stm32-cec";
 306                         reg = <0x40006C00 0x400>;
 307                         interrupts = <94>;
 308                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
 309                         clock-names = "cec", "hdmi-cec";
 310                         status = "disabled";
 311                 };
 312
 313                 usart7: serial@40007800 {
 314                         compatible = "st,stm32f7-uart";
 315                         reg = <0x40007800 0x400>;
 316                         interrupts = <82>;
 317                         clocks = <&rcc 1 CLK_UART7>;
 318                         status = "disabled";
 319                 };
 320
 321                 usart8: serial@40007c00 {
 322                         compatible = "st,stm32f7-uart";
 323                         reg = <0x40007c00 0x400>;
 324                         interrupts = <83>;
 325                         clocks = <&rcc 1 CLK_UART8>;
 326                         status = "disabled";
 327                 };
 328
 329                 timers1: timers@40010000 {
 330                         #address-cells = <1>;
 331                         #size-cells = <0>;
 332                         compatible = "st,stm32-timers";
 333                         reg = <0x40010000 0x400>;
 334                         clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>;
 335                         clock-names = "int";
 336                         status = "disabled";
 337
 338                         pwm {
 339                                 compatible = "st,stm32-pwm";
 340                                 #pwm-cells = <3>;
 341                                 status = "disabled";
 342                         };
 343
 344                         timer@0 {
 345                                 compatible = "st,stm32-timer-trigger";
 346                                 reg = <0>;
 347                                 status = "disabled";
 348                         };
 349                 };
 350
 351                 timers8: timers@40010400 {
 352                         #address-cells = <1>;
 353                         #size-cells = <0>;
 354                         compatible = "st,stm32-timers";
 355                         reg = <0x40010400 0x400>;
 356                         clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>;
 357                         clock-names = "int";
 358                         status = "disabled";
 359
 360                         pwm {
 361                                 compatible = "st,stm32-pwm";
 362                                 #pwm-cells = <3>;
 363                                 status = "disabled";
 364                         };
 365
 366                         timer@7 {
 367                                 compatible = "st,stm32-timer-trigger";
 368                                 reg = <7>;
 369                                 status = "disabled";
 370                         };
 371                 };
 372
 373                 usart1: serial@40011000 {
 374                         compatible = "st,stm32f7-uart";
 375                         reg = <0x40011000 0x400>;
 376                         interrupts = <37>;
 377                         clocks = <&rcc 1 CLK_USART1>;
 378                         status = "disabled";
 379                 };
 380
 381                 usart6: serial@40011400 {
 382                         compatible = "st,stm32f7-uart";
 383                         reg = <0x40011400 0x400>;
 384                         interrupts = <71>;
 385                         clocks = <&rcc 1 CLK_USART6>;
 386                         status = "disabled";
 387                 };
 388
 389                 sdio2: mmc@40011c00 {
 390                         compatible = "arm,pl180", "arm,primecell";
 391                         arm,primecell-periphid = <0x00880180>;
 392                         reg = <0x40011c00 0x400>;
 393                         clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>;
 394                         clock-names = "apb_pclk";
 395                         interrupts = <103>;
 396                         max-frequency = <48000000>;
 397                         status = "disabled";
 398                 };
 399
 400                 sdio1: mmc@40012c00 {
 401                         compatible = "arm,pl180", "arm,primecell";
 402                         arm,primecell-periphid = <0x00880180>;
 403                         reg = <0x40012c00 0x400>;
 404                         clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>;
 405                         clock-names = "apb_pclk";
 406                         interrupts = <49>;
 407                         max-frequency = <48000000>;
 408                         status = "disabled";
 409                 };
 410
 411                 syscfg: syscon@40013800 {
 412                         compatible = "st,stm32-syscfg", "syscon";
 413                         reg = <0x40013800 0x400>;
 414                 };
 415
 416                 exti: interrupt-controller@40013c00 {
 417                         compatible = "st,stm32-exti";
 418                         interrupt-controller;
 419                         #interrupt-cells = <2>;
 420                         reg = <0x40013C00 0x400>;
 421                         interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
 422                 };
 423
 424                 timers9: timers@40014000 {
 425                         #address-cells = <1>;
 426                         #size-cells = <0>;
 427                         compatible = "st,stm32-timers";
 428                         reg = <0x40014000 0x400>;
 429                         clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>;
 430                         clock-names = "int";
 431                         status = "disabled";
 432
 433                         pwm {
 434                                 compatible = "st,stm32-pwm";
 435                                 #pwm-cells = <3>;
 436                                 status = "disabled";
 437                         };
 438
 439                         timer@8 {
 440                                 compatible = "st,stm32-timer-trigger";
 441                                 reg = <8>;
 442                                 status = "disabled";
 443                         };
 444                 };
 445
 446                 timers10: timers@40014400 {
 447                         compatible = "st,stm32-timers";
 448                         reg = <0x40014400 0x400>;
 449                         clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>;
 450                         clock-names = "int";
 451                         status = "disabled";
 452
 453                         pwm {
 454                                 compatible = "st,stm32-pwm";
 455                                 #pwm-cells = <3>;
 456                                 status = "disabled";
 457                         };
 458                 };
 459
 460                 timers11: timers@40014800 {
 461                         compatible = "st,stm32-timers";
 462                         reg = <0x40014800 0x400>;
 463                         clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>;
 464                         clock-names = "int";
 465                         status = "disabled";
 466
 467                         pwm {
 468                                 compatible = "st,stm32-pwm";
 469                                 #pwm-cells = <3>;
 470                                 status = "disabled";
 471                         };
 472                 };
 473
 474                 pwrcfg: power-config@40007000 {
 475                         compatible = "st,stm32-power-config", "syscon";
 476                         reg = <0x40007000 0x400>;
 477                 };
 478
 479                 crc: crc@40023000 {
 480                         compatible = "st,stm32f7-crc";
 481                         reg = <0x40023000 0x400>;
 482                         clocks = <&rcc 0 12>;
 483                         status = "disabled";
 484                 };
 485
 486                 rcc: rcc@40023800 {
 487                         #reset-cells = <1>;
 488                         #clock-cells = <2>;
 489                         compatible = "st,stm32f746-rcc", "st,stm32-rcc";
 490                         reg = <0x40023800 0x400>;
 491                         clocks = <&clk_hse>, <&clk_i2s_ckin>;
 492                         st,syscfg = <&pwrcfg>;
 493                         assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
 494                         assigned-clock-rates = <1000000>;
 495                 };
 496
 497                 dma1: dma-controller@40026000 {
 498                         compatible = "st,stm32-dma";
 499                         reg = <0x40026000 0x400>;
 500                         interrupts = <11>,
 501                                      <12>,
 502                                      <13>,
 503                                      <14>,
 504                                      <15>,
 505                                      <16>,
 506                                      <17>,
 507                                      <47>;
 508                         clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>;
 509                         #dma-cells = <4>;
 510                         status = "disabled";
 511                 };
 512
 513                 dma2: dma-controller@40026400 {
 514                         compatible = "st,stm32-dma";
 515                         reg = <0x40026400 0x400>;
 516                         interrupts = <56>,
 517                                      <57>,
 518                                      <58>,
 519                                      <59>,
 520                                      <60>,
 521                                      <68>,
 522                                      <69>,
 523                                      <70>;
 524                         clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>;
 525                         #dma-cells = <4>;
 526                         st,mem2mem;
 527                         status = "disabled";
 528                 };
 529
 530                 usbotg_hs: usb@40040000 {
 531                         compatible = "st,stm32f7-hsotg";
 532                         reg = <0x40040000 0x40000>;
 533                         interrupts = <77>;
 534                         clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>;
 535                         clock-names = "otg";
 536                         g-rx-fifo-size = <256>;
 537                         g-np-tx-fifo-size = <32>;
 538                         g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
 539                         status = "disabled";
 540                 };
 541
 542                 usbotg_fs: usb@50000000 {
 543                         compatible = "st,stm32f4x9-fsotg";
 544                         reg = <0x50000000 0x40000>;
 545                         interrupts = <67>;
 546                         clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>;
 547                         clock-names = "otg";
 548                         status = "disabled";
 549                 };
 550         };
 551 };
 552
 553 &systick {
 554         clocks = <&rcc 1 0>;
 555         status = "okay";
 556 };