2 * Copyright 2016 - Michael Kurz <michi.kurz@gmail.com>
3 * Copyright 2016 - Vikas MANOCHA <vikas.manocha@st.com>
6 * stm32f429.dtsi from Linux
7 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
9 * This file is dual-licensed: you can use it either under the terms
10 * of the GPL or the X11 license, at your option. Note that this dual
11 * licensing only applies to this file, and not this project as a
14 * a) This file is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of the
17 * License, or (at your option) any later version.
19 * This file is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
48 #include "armv7-m.dtsi"
49 #include <dt-bindings/pinctrl/stm32f746-pinfunc.h>
50 #include <dt-bindings/clock/stm32fx-clock.h>
51 #include <dt-bindings/mfd/stm32f7-rcc.h>
57 compatible = "fixed-clock";
58 clock-frequency = <0>;
64 mac: ethernet@40028000 {
65 compatible = "st,stm32-dwmac";
66 reg = <0x40028000 0x8000>;
67 reg-names = "stmmaceth";
68 interrupts = <61>, <62>;
69 interrupt-names = "macirq", "eth_wake_irq";
77 compatible = "st,stm32-fmc";
78 reg = <0xA0000000 0x1000>;
79 clocks = <&rcc 0 STM32F7_AHB3_CLOCK(FMC)>;
83 qspi: quadspi@A0001000 {
84 compatible = "st,stm32-qspi";
87 reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>;
88 reg-names = "QuadSPI", "QuadSPI-memory";
90 spi-max-frequency = <108000000>;
91 clocks = <&rcc 0 STM32F7_AHB3_CLOCK(QSPI)>;
94 usart1: serial@40011000 {
95 compatible = "st,stm32f7-usart", "st,stm32f7-uart";
96 reg = <0x40011000 0x400>;
98 clocks = <&rcc 0 STM32F7_APB2_CLOCK(USART1)>;
103 pwrcfg: power-config@58024800 {
104 compatible = "syscon";
105 reg = <0x40007000 0x400>;
111 compatible = "st,stm32f746-rcc", "st,stm32-rcc";
112 reg = <0x40023800 0x400>;
114 st,syscfg = <&pwrcfg>;
118 pinctrl: pin-controller {
119 #address-cells = <1>;
121 compatible = "st,stm32f746-pinctrl";
122 ranges = <0 0x40020000 0x3000>;
126 gpioa: gpio@40020000 {
129 compatible = "st,stm32-gpio";
131 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
132 st,bank-name = "GPIOA";
136 gpiob: gpio@40020400 {
139 compatible = "st,stm32-gpio";
141 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
142 st,bank-name = "GPIOB";
147 gpioc: gpio@40020800 {
150 compatible = "st,stm32-gpio";
152 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
153 st,bank-name = "GPIOC";
157 gpiod: gpio@40020c00 {
160 compatible = "st,stm32-gpio";
162 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
163 st,bank-name = "GPIOD";
167 gpioe: gpio@40021000 {
170 compatible = "st,stm32-gpio";
171 reg = <0x1000 0x400>;
172 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
173 st,bank-name = "GPIOE";
177 gpiof: gpio@40021400 {
180 compatible = "st,stm32-gpio";
181 reg = <0x1400 0x400>;
182 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
183 st,bank-name = "GPIOF";
187 gpiog: gpio@40021800 {
190 compatible = "st,stm32-gpio";
191 reg = <0x1800 0x400>;
192 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
193 st,bank-name = "GPIOG";
197 gpioh: gpio@40021c00 {
200 compatible = "st,stm32-gpio";
201 reg = <0x1c00 0x400>;
202 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
203 st,bank-name = "GPIOH";
207 gpioi: gpio@40022000 {
210 compatible = "st,stm32-gpio";
211 reg = <0x2000 0x400>;
212 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
213 st,bank-name = "GPIOI";
217 gpioj: gpio@40022400 {
220 compatible = "st,stm32-gpio";
221 reg = <0x2400 0x400>;
222 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
223 st,bank-name = "GPIOJ";
227 gpiok: gpio@40022800 {
230 compatible = "st,stm32-gpio";
231 reg = <0x2800 0x400>;
232 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
233 st,bank-name = "GPIOK";
237 sdio_pins: sdio_pins@0 {
239 pinmux = <STM32F746_PC8_FUNC_SDMMC1_D0>,
240 <STM32F746_PC9_FUNC_SDMMC1_D1>,
241 <STM32F746_PC10_FUNC_SDMMC1_D2>,
242 <STM32F746_PC11_FUNC_SDMMC1_D3>,
243 <STM32F746_PC12_FUNC_SDMMC1_CK>,
244 <STM32F746_PD2_FUNC_SDMMC1_CMD>;
250 sdio_pins_od: sdio_pins_od@0 {
252 pinmux = <STM32F746_PC8_FUNC_SDMMC1_D0>,
253 <STM32F746_PC9_FUNC_SDMMC1_D1>,
254 <STM32F746_PC10_FUNC_SDMMC1_D2>,
255 <STM32F746_PC11_FUNC_SDMMC1_D3>,
256 <STM32F746_PC12_FUNC_SDMMC1_CK>;
262 pinmux = <STM32F746_PD2_FUNC_SDMMC1_CMD>;
268 sdio_pins_b: sdio_pins_b@0 {
270 pinmux = <STM32F769_PG9_FUNC_SDMMC2_D0>,
271 <STM32F769_PG10_FUNC_SDMMC2_D1>,
272 <STM32F769_PB3_FUNC_SDMMC2_D2>,
273 <STM32F769_PB4_FUNC_SDMMC2_D3>,
274 <STM32F769_PD6_FUNC_SDMMC2_CLK>,
275 <STM32F769_PD7_FUNC_SDMMC2_CMD>;
281 sdio_pins_od_b: sdio_pins_od_b@0 {
283 pinmux = <STM32F769_PG9_FUNC_SDMMC2_D0>,
284 <STM32F769_PG10_FUNC_SDMMC2_D1>,
285 <STM32F769_PB3_FUNC_SDMMC2_D2>,
286 <STM32F769_PB4_FUNC_SDMMC2_D3>,
287 <STM32F769_PD6_FUNC_SDMMC2_CLK>;
293 pinmux = <STM32F769_PD7_FUNC_SDMMC2_CMD>;
300 sdio: sdio@40012c00 {
301 compatible = "st,stm32f4xx-sdio";
302 reg = <0x40012c00 0x400>;
303 clocks = <&rcc 0 171>;
306 pinctrl-0 = <&sdio_pins>;
307 pinctrl-1 = <&sdio_pins_od>;
308 pinctrl-names = "default", "opendrain";
309 max-frequency = <48000000>;
312 sdio2: sdio2@40011c00 {
313 compatible = "st,stm32f4xx-sdio";
314 reg = <0x40011c00 0x400>;
315 clocks = <&rcc 0 167>;
318 pinctrl-0 = <&sdio_pins_b>;
319 pinctrl-1 = <&sdio_pins_od_b>;
320 pinctrl-names = "default", "opendrain";
321 max-frequency = <48000000>;