arch/arm/dts/stm32f746.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
   4  *
   5  */
   6
   7 #include "armv7-m.dtsi"
   8 #include <dt-bindings/clock/stm32fx-clock.h>
   9 #include <dt-bindings/mfd/stm32f7-rcc.h>
  10
  11 / {
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14
  15         clocks {
  16                 clk_hse: clk-hse {
  17                         #clock-cells = <0>;
  18                         compatible = "fixed-clock";
  19                         clock-frequency = <0>;
  20                 };
  21
  22                 clk-lse {
  23                         #clock-cells = <0>;
  24                         compatible = "fixed-clock";
  25                         clock-frequency = <32768>;
  26                 };
  27
  28                 clk-lsi {
  29                         #clock-cells = <0>;
  30                         compatible = "fixed-clock";
  31                         clock-frequency = <32000>;
  32                 };
  33
  34                 clk_i2s_ckin: clk-i2s-ckin {
  35                         #clock-cells = <0>;
  36                         compatible = "fixed-clock";
  37                         clock-frequency = <48000000>;
  38                 };
  39         };
  40
  41         soc {
  42                 timer2: timer@40000000 {
  43                         compatible = "st,stm32-timer";
  44                         reg = <0x40000000 0x400>;
  45                         interrupts = <28>;
  46                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
  47                         status = "disabled";
  48                 };
  49
  50                 timers2: timers@40000000 {
  51                         #address-cells = <1>;
  52                         #size-cells = <0>;
  53                         compatible = "st,stm32-timers";
  54                         reg = <0x40000000 0x400>;
  55                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
  56                         clock-names = "int";
  57                         status = "disabled";
  58
  59                         pwm {
  60                                 compatible = "st,stm32-pwm";
  61                                 #pwm-cells = <3>;
  62                                 status = "disabled";
  63                         };
  64
  65                         timer@1 {
  66                                 compatible = "st,stm32-timer-trigger";
  67                                 reg = <1>;
  68                                 status = "disabled";
  69                         };
  70                 };
  71
  72                 timer3: timer@40000400 {
  73                         compatible = "st,stm32-timer";
  74                         reg = <0x40000400 0x400>;
  75                         interrupts = <29>;
  76                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
  77                         status = "disabled";
  78                 };
  79
  80                 timers3: timers@40000400 {
  81                         #address-cells = <1>;
  82                         #size-cells = <0>;
  83                         compatible = "st,stm32-timers";
  84                         reg = <0x40000400 0x400>;
  85                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
  86                         clock-names = "int";
  87                         status = "disabled";
  88
  89                         pwm {
  90                                 compatible = "st,stm32-pwm";
  91                                 #pwm-cells = <3>;
  92                                 status = "disabled";
  93                         };
  94
  95                         timer@2 {
  96                                 compatible = "st,stm32-timer-trigger";
  97                                 reg = <2>;
  98                                 status = "disabled";
  99                         };
 100                 };
 101
 102                 timer4: timer@40000800 {
 103                         compatible = "st,stm32-timer";
 104                         reg = <0x40000800 0x400>;
 105                         interrupts = <30>;
 106                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
 107                         status = "disabled";
 108                 };
 109
 110                 timers4: timers@40000800 {
 111                         #address-cells = <1>;
 112                         #size-cells = <0>;
 113                         compatible = "st,stm32-timers";
 114                         reg = <0x40000800 0x400>;
 115                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
 116                         clock-names = "int";
 117                         status = "disabled";
 118
 119                         pwm {
 120                                 compatible = "st,stm32-pwm";
 121                                 #pwm-cells = <3>;
 122                                 status = "disabled";
 123                         };
 124
 125                         timer@3 {
 126                                 compatible = "st,stm32-timer-trigger";
 127                                 reg = <3>;
 128                                 status = "disabled";
 129                         };
 130                 };
 131
 132                 timer5: timer@40000c00 {
 133                         compatible = "st,stm32-timer";
 134                         reg = <0x40000c00 0x400>;
 135                         interrupts = <50>;
 136                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
 137                 };
 138
 139                 timers5: timers@40000c00 {
 140                         #address-cells = <1>;
 141                         #size-cells = <0>;
 142                         compatible = "st,stm32-timers";
 143                         reg = <0x40000C00 0x400>;
 144                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
 145                         clock-names = "int";
 146                         status = "disabled";
 147
 148                         pwm {
 149                                 compatible = "st,stm32-pwm";
 150                                 #pwm-cells = <3>;
 151                                 status = "disabled";
 152                         };
 153
 154                         timer@4 {
 155                                 compatible = "st,stm32-timer-trigger";
 156                                 reg = <4>;
 157                                 status = "disabled";
 158                         };
 159                 };
 160
 161                 timer6: timer@40001000 {
 162                         compatible = "st,stm32-timer";
 163                         reg = <0x40001000 0x400>;
 164                         interrupts = <54>;
 165                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
 166                         status = "disabled";
 167                 };
 168
 169                 timers6: timers@40001000 {
 170                         #address-cells = <1>;
 171                         #size-cells = <0>;
 172                         compatible = "st,stm32-timers";
 173                         reg = <0x40001000 0x400>;
 174                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
 175                         clock-names = "int";
 176                         status = "disabled";
 177
 178                         timer@5 {
 179                                 compatible = "st,stm32-timer-trigger";
 180                                 reg = <5>;
 181                                 status = "disabled";
 182                         };
 183                 };
 184
 185                 timer7: timer@40001400 {
 186                         compatible = "st,stm32-timer";
 187                         reg = <0x40001400 0x400>;
 188                         interrupts = <55>;
 189                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
 190                         status = "disabled";
 191                 };
 192
 193                 timers7: timers@40001400 {
 194                         #address-cells = <1>;
 195                         #size-cells = <0>;
 196                         compatible = "st,stm32-timers";
 197                         reg = <0x40001400 0x400>;
 198                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
 199                         clock-names = "int";
 200                         status = "disabled";
 201
 202                         timer@6 {
 203                                 compatible = "st,stm32-timer-trigger";
 204                                 reg = <6>;
 205                                 status = "disabled";
 206                         };
 207                 };
 208
 209                 timers12: timers@40001800 {
 210                         #address-cells = <1>;
 211                         #size-cells = <0>;
 212                         compatible = "st,stm32-timers";
 213                         reg = <0x40001800 0x400>;
 214                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>;
 215                         clock-names = "int";
 216                         status = "disabled";
 217
 218                         pwm {
 219                                 compatible = "st,stm32-pwm";
 220                                 #pwm-cells = <3>;
 221                                 status = "disabled";
 222                         };
 223
 224                         timer@11 {
 225                                 compatible = "st,stm32-timer-trigger";
 226                                 reg = <11>;
 227                                 status = "disabled";
 228                         };
 229                 };
 230
 231                 timers13: timers@40001c00 {
 232                         #address-cells = <1>;
 233                         #size-cells = <0>;
 234                         compatible = "st,stm32-timers";
 235                         reg = <0x40001C00 0x400>;
 236                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
 237                         clock-names = "int";
 238                         status = "disabled";
 239
 240                         pwm {
 241                                 compatible = "st,stm32-pwm";
 242                                 #pwm-cells = <3>;
 243                                 status = "disabled";
 244                         };
 245                 };
 246
 247                 timers14: timers@40002000 {
 248                         #address-cells = <1>;
 249                         #size-cells = <0>;
 250                         compatible = "st,stm32-timers";
 251                         reg = <0x40002000 0x400>;
 252                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
 253                         clock-names = "int";
 254                         status = "disabled";
 255
 256                         pwm {
 257                                 compatible = "st,stm32-pwm";
 258                                 #pwm-cells = <3>;
 259                                 status = "disabled";
 260                         };
 261                 };
 262
 263                 rtc: rtc@40002800 {
 264                         compatible = "st,stm32-rtc";
 265                         reg = <0x40002800 0x400>;
 266                         clocks = <&rcc 1 CLK_RTC>;
 267                         assigned-clocks = <&rcc 1 CLK_RTC>;
 268                         assigned-clock-parents = <&rcc 1 CLK_LSE>;
 269                         interrupt-parent = <&exti>;
 270                         interrupts = <17 1>;
 271                         st,syscfg = <&pwrcfg 0x00 0x100>;
 272                         status = "disabled";
 273                 };
 274
 275                 usart2: serial@40004400 {
 276                         compatible = "st,stm32f7-uart";
 277                         reg = <0x40004400 0x400>;
 278                         interrupts = <38>;
 279                         clocks = <&rcc 1 CLK_USART2>;
 280                         status = "disabled";
 281                 };
 282
 283                 usart3: serial@40004800 {
 284                         compatible = "st,stm32f7-uart";
 285                         reg = <0x40004800 0x400>;
 286                         interrupts = <39>;
 287                         clocks = <&rcc 1 CLK_USART3>;
 288                         status = "disabled";
 289                 };
 290
 291                 usart4: serial@40004c00 {
 292                         compatible = "st,stm32f7-uart";
 293                         reg = <0x40004c00 0x400>;
 294                         interrupts = <52>;
 295                         clocks = <&rcc 1 CLK_UART4>;
 296                         status = "disabled";
 297                 };
 298
 299                 usart5: serial@40005000 {
 300                         compatible = "st,stm32f7-uart";
 301                         reg = <0x40005000 0x400>;
 302                         interrupts = <53>;
 303                         clocks = <&rcc 1 CLK_UART5>;
 304                         status = "disabled";
 305                 };
 306
 307                 i2c1: i2c@40005400 {
 308                         compatible = "st,stm32f7-i2c";
 309                         reg = <0x40005400 0x400>;
 310                         interrupts = <31>,
 311                                      <32>;
 312                         resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
 313                         clocks = <&rcc 1 CLK_I2C1>;
 314                         #address-cells = <1>;
 315                         #size-cells = <0>;
 316                         status = "disabled";
 317                 };
 318
 319                 i2c2: i2c@40005800 {
 320                         compatible = "st,stm32f7-i2c";
 321                         reg = <0x40005800 0x400>;
 322                         interrupts = <33>,
 323                                      <34>;
 324                         resets = <&rcc STM32F7_APB1_RESET(I2C2)>;
 325                         clocks = <&rcc 1 CLK_I2C2>;
 326                         #address-cells = <1>;
 327                         #size-cells = <0>;
 328                         status = "disabled";
 329                 };
 330
 331                 i2c3: i2c@40005C00 {
 332                         compatible = "st,stm32f7-i2c";
 333                         reg = <0x40005C00 0x400>;
 334                         interrupts = <72>,
 335                                      <73>;
 336                         resets = <&rcc STM32F7_APB1_RESET(I2C3)>;
 337                         clocks = <&rcc 1 CLK_I2C3>;
 338                         #address-cells = <1>;
 339                         #size-cells = <0>;
 340                         status = "disabled";
 341                 };
 342
 343                 i2c4: i2c@40006000 {
 344                         compatible = "st,stm32f7-i2c";
 345                         reg = <0x40006000 0x400>;
 346                         interrupts = <95>,
 347                                      <96>;
 348                         resets = <&rcc STM32F7_APB1_RESET(I2C4)>;
 349                         clocks = <&rcc 1 CLK_I2C4>;
 350                         #address-cells = <1>;
 351                         #size-cells = <0>;
 352                         status = "disabled";
 353                 };
 354
 355                 cec: cec@40006c00 {
 356                         compatible = "st,stm32-cec";
 357                         reg = <0x40006C00 0x400>;
 358                         interrupts = <94>;
 359                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
 360                         clock-names = "cec", "hdmi-cec";
 361                         status = "disabled";
 362                 };
 363
 364                 usart7: serial@40007800 {
 365                         compatible = "st,stm32f7-uart";
 366                         reg = <0x40007800 0x400>;
 367                         interrupts = <82>;
 368                         clocks = <&rcc 1 CLK_UART7>;
 369                         status = "disabled";
 370                 };
 371
 372                 usart8: serial@40007c00 {
 373                         compatible = "st,stm32f7-uart";
 374                         reg = <0x40007c00 0x400>;
 375                         interrupts = <83>;
 376                         clocks = <&rcc 1 CLK_UART8>;
 377                         status = "disabled";
 378                 };
 379
 380                 timers1: timers@40010000 {
 381                         #address-cells = <1>;
 382                         #size-cells = <0>;
 383                         compatible = "st,stm32-timers";
 384                         reg = <0x40010000 0x400>;
 385                         clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>;
 386                         clock-names = "int";
 387                         status = "disabled";
 388
 389                         pwm {
 390                                 compatible = "st,stm32-pwm";
 391                                 #pwm-cells = <3>;
 392                                 status = "disabled";
 393                         };
 394
 395                         timer@0 {
 396                                 compatible = "st,stm32-timer-trigger";
 397                                 reg = <0>;
 398                                 status = "disabled";
 399                         };
 400                 };
 401
 402                 timers8: timers@40010400 {
 403                         #address-cells = <1>;
 404                         #size-cells = <0>;
 405                         compatible = "st,stm32-timers";
 406                         reg = <0x40010400 0x400>;
 407                         clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>;
 408                         clock-names = "int";
 409                         status = "disabled";
 410
 411                         pwm {
 412                                 compatible = "st,stm32-pwm";
 413                                 #pwm-cells = <3>;
 414                                 status = "disabled";
 415                         };
 416
 417                         timer@7 {
 418                                 compatible = "st,stm32-timer-trigger";
 419                                 reg = <7>;
 420                                 status = "disabled";
 421                         };
 422                 };
 423
 424                 usart1: serial@40011000 {
 425                         compatible = "st,stm32f7-uart";
 426                         reg = <0x40011000 0x400>;
 427                         interrupts = <37>;
 428                         clocks = <&rcc 1 CLK_USART1>;
 429                         status = "disabled";
 430                 };
 431
 432                 usart6: serial@40011400 {
 433                         compatible = "st,stm32f7-uart";
 434                         reg = <0x40011400 0x400>;
 435                         interrupts = <71>;
 436                         clocks = <&rcc 1 CLK_USART6>;
 437                         status = "disabled";
 438                 };
 439
 440                 sdio2: sdio2@40011c00 {
 441                         compatible = "arm,pl180", "arm,primecell";
 442                         arm,primecell-periphid = <0x00880180>;
 443                         reg = <0x40011c00 0x400>;
 444                         clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>;
 445                         clock-names = "apb_pclk";
 446                         interrupts = <103>;
 447                         max-frequency = <48000000>;
 448                         status = "disabled";
 449                 };
 450
 451                 sdio1: sdio1@40012c00 {
 452                         compatible = "arm,pl180", "arm,primecell";
 453                         arm,primecell-periphid = <0x00880180>;
 454                         reg = <0x40012c00 0x400>;
 455                         clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>;
 456                         clock-names = "apb_pclk";
 457                         interrupts = <49>;
 458                         max-frequency = <48000000>;
 459                         status = "disabled";
 460                 };
 461
 462                 syscfg: syscon@40013800 {
 463                         compatible = "st,stm32-syscfg", "syscon";
 464                         reg = <0x40013800 0x400>;
 465                 };
 466
 467                 exti: interrupt-controller@40013c00 {
 468                         compatible = "st,stm32-exti";
 469                         interrupt-controller;
 470                         #interrupt-cells = <2>;
 471                         reg = <0x40013C00 0x400>;
 472                         interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
 473                 };
 474
 475                 timers9: timers@40014000 {
 476                         #address-cells = <1>;
 477                         #size-cells = <0>;
 478                         compatible = "st,stm32-timers";
 479                         reg = <0x40014000 0x400>;
 480                         clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>;
 481                         clock-names = "int";
 482                         status = "disabled";
 483
 484                         pwm {
 485                                 compatible = "st,stm32-pwm";
 486                                 #pwm-cells = <3>;
 487                                 status = "disabled";
 488                         };
 489
 490                         timer@8 {
 491                                 compatible = "st,stm32-timer-trigger";
 492                                 reg = <8>;
 493                                 status = "disabled";
 494                         };
 495                 };
 496
 497                 timers10: timers@40014400 {
 498                         #address-cells = <1>;
 499                         #size-cells = <0>;
 500                         compatible = "st,stm32-timers";
 501                         reg = <0x40014400 0x400>;
 502                         clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>;
 503                         clock-names = "int";
 504                         status = "disabled";
 505
 506                         pwm {
 507                                 compatible = "st,stm32-pwm";
 508                                 #pwm-cells = <3>;
 509                                 status = "disabled";
 510                         };
 511                 };
 512
 513                 timers11: timers@40014800 {
 514                         #address-cells = <1>;
 515                         #size-cells = <0>;
 516                         compatible = "st,stm32-timers";
 517                         reg = <0x40014800 0x400>;
 518                         clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>;
 519                         clock-names = "int";
 520                         status = "disabled";
 521
 522                         pwm {
 523                                 compatible = "st,stm32-pwm";
 524                                 #pwm-cells = <3>;
 525                                 status = "disabled";
 526                         };
 527                 };
 528
 529                 pwrcfg: power-config@40007000 {
 530                         compatible = "st,stm32-power-config", "syscon";
 531                         reg = <0x40007000 0x400>;
 532                 };
 533
 534                 crc: crc@40023000 {
 535                         compatible = "st,stm32f7-crc";
 536                         reg = <0x40023000 0x400>;
 537                         clocks = <&rcc 0 12>;
 538                         status = "disabled";
 539                 };
 540
 541                 rcc: rcc@40023800 {
 542                         #reset-cells = <1>;
 543                         #clock-cells = <2>;
 544                         compatible = "st,stm32f746-rcc", "st,stm32-rcc";
 545                         reg = <0x40023800 0x400>;
 546                         clocks = <&clk_hse>, <&clk_i2s_ckin>;
 547                         st,syscfg = <&pwrcfg>;
 548                         assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
 549                         assigned-clock-rates = <1000000>;
 550                 };
 551
 552                 dma1: dma-controller@40026000 {
 553                         compatible = "st,stm32-dma";
 554                         reg = <0x40026000 0x400>;
 555                         interrupts = <11>,
 556                                      <12>,
 557                                      <13>,
 558                                      <14>,
 559                                      <15>,
 560                                      <16>,
 561                                      <17>,
 562                                      <47>;
 563                         clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>;
 564                         #dma-cells = <4>;
 565                         status = "disabled";
 566                 };
 567
 568                 dma2: dma-controller@40026400 {
 569                         compatible = "st,stm32-dma";
 570                         reg = <0x40026400 0x400>;
 571                         interrupts = <56>,
 572                                      <57>,
 573                                      <58>,
 574                                      <59>,
 575                                      <60>,
 576                                      <68>,
 577                                      <69>,
 578                                      <70>;
 579                         clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>;
 580                         #dma-cells = <4>;
 581                         st,mem2mem;
 582                         status = "disabled";
 583                 };
 584
 585                 usbotg_hs: usb@40040000 {
 586                         compatible = "st,stm32f7-hsotg";
 587                         reg = <0x40040000 0x40000>;
 588                         interrupts = <77>;
 589                         clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>;
 590                         clock-names = "otg";
 591                         g-rx-fifo-size = <256>;
 592                         g-np-tx-fifo-size = <32>;
 593                         g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
 594                         status = "disabled";
 595                 };
 596
 597                 usbotg_fs: usb@50000000 {
 598                         compatible = "st,stm32f4x9-fsotg";
 599                         reg = <0x50000000 0x40000>;
 600                         interrupts = <67>;
 601                         clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>;
 602                         clock-names = "otg";
 603                         status = "disabled";
 604                 };
 605         };
 606 };
 607
 608 &systick {
 609         clocks = <&rcc 1 0>;
 610         status = "okay";
 611 };