arch/arm/dts/stm32f746.dtsi

   1 /*
   2  * Copyright 2016 - Michael Kurz <michi.kurz@gmail.com>
   3  * Copyright 2016 - Vikas MANOCHA <vikas.manocha@st.com>
   4  *
   5  * Based on:
   6  * stm32f429.dtsi from Linux
   7  * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
   8  *
   9  * This file is dual-licensed: you can use it either under the terms
  10  * of the GPL or the X11 license, at your option. Note that this dual
  11  * licensing only applies to this file, and not this project as a
  12  * whole.
  13  *
  14  *  a) This file is free software; you can redistribute it and/or
  15  *     modify it under the terms of the GNU General Public License as
  16  *     published by the Free Software Foundation; either version 2 of the
  17  *     License, or (at your option) any later version.
  18  *
  19  *     This file is distributed in the hope that it will be useful,
  20  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  *     GNU General Public License for more details.
  23  *
  24  * Or, alternatively,
  25  *
  26  *  b) Permission is hereby granted, free of charge, to any person
  27  *     obtaining a copy of this software and associated documentation
  28  *     files (the "Software"), to deal in the Software without
  29  *     restriction, including without limitation the rights to use,
  30  *     copy, modify, merge, publish, distribute, sublicense, and/or
  31  *     sell copies of the Software, and to permit persons to whom the
  32  *     Software is furnished to do so, subject to the following
  33  *     conditions:
  34  *
  35  *     The above copyright notice and this permission notice shall be
  36  *     included in all copies or substantial portions of the Software.
  37  *
  38  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  39  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  40  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  41  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  42  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  43  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  44  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  45  *     OTHER DEALINGS IN THE SOFTWARE.
  46  */
  47
  48 #include "armv7-m.dtsi"
  49 #include <dt-bindings/pinctrl/stm32f746-pinfunc.h>
  50
  51 / {
  52         clocks {
  53                 clk_hse: clk-hse {
  54                         #clock-cells = <0>;
  55                         compatible = "fixed-clock";
  56                         clock-frequency = <0>;
  57                 };
  58 };
  59
  60         soc {
  61                 u-boot,dm-pre-reloc;
  62                 mac: ethernet@40028000 {
  63                         compatible = "st,stm32-dwmac";
  64                         reg = <0x40028000 0x8000>;
  65                         reg-names = "stmmaceth";
  66                         interrupts = <61>, <62>;
  67                         interrupt-names = "macirq", "eth_wake_irq";
  68                         snps,pbl = <8>;
  69                         snps,mixed-burst;
  70                         dma-ranges;
  71                         status = "disabled";
  72                 };
  73
  74                 fmc: fmc@A0000000 {
  75                         compatible = "st,stm32-fmc";
  76                         reg = <0xA0000000 0x1000>;
  77                         clocks = <&rcc 0 64>;
  78                         u-boot,dm-pre-reloc;
  79                 };
  80
  81                 qspi: quadspi@A0001000 {
  82                         compatible = "st,stm32-qspi";
  83                         #address-cells = <1>;
  84                         #size-cells = <0>;
  85                         reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>;
  86                         reg-names = "QuadSPI", "QuadSPI-memory";
  87                         interrupts = <92>;
  88                         spi-max-frequency = <108000000>;
  89                         clocks = <&rcc 0 65>;
  90                         status = "disabled";
  91                 };
  92                 usart1: serial@40011000 {
  93                         compatible = "st,stm32-usart", "st,stm32-uart";
  94                         reg = <0x40011000 0x400>;
  95                         interrupts = <37>;
  96                         clocks = <&rcc 0 164>;
  97                         status = "disabled";
  98                         u-boot,dm-pre-reloc;
  99                 };
 100                 rcc: rcc@40023810 {
 101                         #reset-cells = <1>;
 102                         #clock-cells = <2>;
 103                         compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
 104                         reg = <0x40023800 0x400>;
 105                         clocks = <&clk_hse>;
 106                         u-boot,dm-pre-reloc;
 107                 };
 108
 109                 pinctrl: pin-controller {
 110                         #address-cells = <1>;
 111                         #size-cells = <1>;
 112                         compatible = "st,stm32f746-pinctrl";
 113                         ranges = <0 0x40020000 0x3000>;
 114                         u-boot,dm-pre-reloc;
 115                         pins-are-numbered;
 116
 117                         gpioa: gpio@40020000 {
 118                                 gpio-controller;
 119                                 #gpio-cells = <2>;
 120                                 compatible = "st,stm32-gpio";
 121                                 reg = <0x0 0x400>;
 122                                 clocks = <&rcc 0 0>;
 123                                 st,bank-name = "GPIOA";
 124                                 u-boot,dm-pre-reloc;
 125                         };
 126
 127                         gpiob: gpio@40020400 {
 128                                 gpio-controller;
 129                                 #gpio-cells = <2>;
 130                                 compatible = "st,stm32-gpio";
 131                                 reg = <0x400 0x400>;
 132                                 clocks = <&rcc 0 1>;
 133                                 st,bank-name = "GPIOB";
 134                                 u-boot,dm-pre-reloc;
 135                         };
 136
 137
 138                         gpioc: gpio@40020800 {
 139                                 gpio-controller;
 140                                 #gpio-cells = <2>;
 141                                 compatible = "st,stm32-gpio";
 142                                 reg = <0x800 0x400>;
 143                                 clocks = <&rcc 0 2>;
 144                                 st,bank-name = "GPIOC";
 145                                 u-boot,dm-pre-reloc;
 146                         };
 147
 148                         gpiod: gpio@40020c00 {
 149                                 gpio-controller;
 150                                 #gpio-cells = <2>;
 151                                 compatible = "st,stm32-gpio";
 152                                 reg = <0xc00 0x400>;
 153                                 clocks = <&rcc 0 3>;
 154                                 st,bank-name = "GPIOD";
 155                                 u-boot,dm-pre-reloc;
 156                         };
 157
 158                         gpioe: gpio@40021000 {
 159                                 gpio-controller;
 160                                 #gpio-cells = <2>;
 161                                 compatible = "st,stm32-gpio";
 162                                 reg = <0x1000 0x400>;
 163                                 clocks = <&rcc 0 4>;
 164                                 st,bank-name = "GPIOE";
 165                                 u-boot,dm-pre-reloc;
 166                         };
 167
 168                         gpiof: gpio@40021400 {
 169                                 gpio-controller;
 170                                 #gpio-cells = <2>;
 171                                 compatible = "st,stm32-gpio";
 172                                 reg = <0x1400 0x400>;
 173                                 clocks = <&rcc 0 5>;
 174                                 st,bank-name = "GPIOF";
 175                                 u-boot,dm-pre-reloc;
 176                         };
 177
 178                         gpiog: gpio@40021800 {
 179                                 gpio-controller;
 180                                 #gpio-cells = <2>;
 181                                 compatible = "st,stm32-gpio";
 182                                 reg = <0x1800 0x400>;
 183                                 clocks = <&rcc 0 6>;
 184                                 st,bank-name = "GPIOG";
 185                                 u-boot,dm-pre-reloc;
 186                         };
 187
 188                         gpioh: gpio@40021c00 {
 189                                 gpio-controller;
 190                                 #gpio-cells = <2>;
 191                                 compatible = "st,stm32-gpio";
 192                                 reg = <0x1c00 0x400>;
 193                                 clocks = <&rcc 0 7>;
 194                                 st,bank-name = "GPIOH";
 195                                 u-boot,dm-pre-reloc;
 196                         };
 197
 198                         gpioi: gpio@40022000 {
 199                                 gpio-controller;
 200                                 #gpio-cells = <2>;
 201                                 compatible = "st,stm32-gpio";
 202                                 reg = <0x2000 0x400>;
 203                                 clocks = <&rcc 0 8>;
 204                                 st,bank-name = "GPIOI";
 205                                 u-boot,dm-pre-reloc;
 206                         };
 207
 208                         gpioj: gpio@40022400 {
 209                                 gpio-controller;
 210                                 #gpio-cells = <2>;
 211                                 compatible = "st,stm32-gpio";
 212                                 reg = <0x2400 0x400>;
 213                                 clocks = <&rcc 0 9>;
 214                                 st,bank-name = "GPIOJ";
 215                                 u-boot,dm-pre-reloc;
 216                         };
 217
 218                         gpiok: gpio@40022800 {
 219                                 gpio-controller;
 220                                 #gpio-cells = <2>;
 221                                 compatible = "st,stm32-gpio";
 222                                 reg = <0x2800 0x400>;
 223                                 clocks = <&rcc 0 10>;
 224                                 st,bank-name = "GPIOK";
 225                                 u-boot,dm-pre-reloc;
 226                         };
 227
 228                 };
 229         };
 230 };
 231
 232 &systick {
 233         status = "okay";
 234 };