2 * Copyright 2016 - Michael Kurz <michi.kurz@gmail.com>
3 * Copyright 2016 - Vikas MANOCHA <vikas.manocha@st.com>
6 * stm32f429.dtsi from Linux
7 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
9 * This file is dual-licensed: you can use it either under the terms
10 * of the GPL or the X11 license, at your option. Note that this dual
11 * licensing only applies to this file, and not this project as a
14 * a) This file is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of the
17 * License, or (at your option) any later version.
19 * This file is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
48 #include "armv7-m.dtsi"
49 #include <dt-bindings/pinctrl/stm32f746-pinfunc.h>
50 #include <dt-bindings/clock/stm32fx-clock.h>
51 #include <dt-bindings/mfd/stm32f7-rcc.h>
57 compatible = "fixed-clock";
58 clock-frequency = <0>;
64 mac: ethernet@40028000 {
65 compatible = "st,stm32-dwmac";
66 reg = <0x40028000 0x8000>;
67 reg-names = "stmmaceth";
68 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(ETHMAC)>,
69 <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACTX)>,
70 <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACRX)>;
71 interrupts = <61>, <62>;
72 interrupt-names = "macirq", "eth_wake_irq";
80 compatible = "st,stm32-fmc";
81 reg = <0xA0000000 0x1000>;
82 clocks = <&rcc 0 STM32F7_AHB3_CLOCK(FMC)>;
86 qspi: quadspi@A0001000 {
87 compatible = "st,stm32-qspi";
90 reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>;
91 reg-names = "QuadSPI", "QuadSPI-memory";
93 spi-max-frequency = <108000000>;
94 clocks = <&rcc 0 STM32F7_AHB3_CLOCK(QSPI)>;
95 resets = <&rcc STM32F7_AHB3_RESET(QSPI)>;
98 usart1: serial@40011000 {
99 compatible = "st,stm32f7-usart", "st,stm32f7-uart";
100 reg = <0x40011000 0x400>;
102 clocks = <&rcc 0 STM32F7_APB2_CLOCK(USART1)>;
107 pwrcfg: power-config@58024800 {
108 compatible = "syscon";
109 reg = <0x40007000 0x400>;
115 compatible = "st,stm32f746-rcc", "st,stm32-rcc";
116 reg = <0x40023800 0x400>;
118 st,syscfg = <&pwrcfg>;
122 pinctrl: pin-controller {
123 #address-cells = <1>;
125 compatible = "st,stm32f746-pinctrl";
126 ranges = <0 0x40020000 0x3000>;
130 gpioa: gpio@40020000 {
133 compatible = "st,stm32-gpio";
135 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
136 st,bank-name = "GPIOA";
140 gpiob: gpio@40020400 {
143 compatible = "st,stm32-gpio";
145 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
146 st,bank-name = "GPIOB";
151 gpioc: gpio@40020800 {
154 compatible = "st,stm32-gpio";
156 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
157 st,bank-name = "GPIOC";
161 gpiod: gpio@40020c00 {
164 compatible = "st,stm32-gpio";
166 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
167 st,bank-name = "GPIOD";
171 gpioe: gpio@40021000 {
174 compatible = "st,stm32-gpio";
175 reg = <0x1000 0x400>;
176 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
177 st,bank-name = "GPIOE";
181 gpiof: gpio@40021400 {
184 compatible = "st,stm32-gpio";
185 reg = <0x1400 0x400>;
186 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
187 st,bank-name = "GPIOF";
191 gpiog: gpio@40021800 {
194 compatible = "st,stm32-gpio";
195 reg = <0x1800 0x400>;
196 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
197 st,bank-name = "GPIOG";
201 gpioh: gpio@40021c00 {
204 compatible = "st,stm32-gpio";
205 reg = <0x1c00 0x400>;
206 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
207 st,bank-name = "GPIOH";
211 gpioi: gpio@40022000 {
214 compatible = "st,stm32-gpio";
215 reg = <0x2000 0x400>;
216 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
217 st,bank-name = "GPIOI";
221 gpioj: gpio@40022400 {
224 compatible = "st,stm32-gpio";
225 reg = <0x2400 0x400>;
226 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
227 st,bank-name = "GPIOJ";
231 gpiok: gpio@40022800 {
234 compatible = "st,stm32-gpio";
235 reg = <0x2800 0x400>;
236 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
237 st,bank-name = "GPIOK";
241 sdio_pins: sdio_pins@0 {
243 pinmux = <STM32F746_PC8_FUNC_SDMMC1_D0>,
244 <STM32F746_PC9_FUNC_SDMMC1_D1>,
245 <STM32F746_PC10_FUNC_SDMMC1_D2>,
246 <STM32F746_PC11_FUNC_SDMMC1_D3>,
247 <STM32F746_PC12_FUNC_SDMMC1_CK>,
248 <STM32F746_PD2_FUNC_SDMMC1_CMD>;
254 sdio_pins_od: sdio_pins_od@0 {
256 pinmux = <STM32F746_PC8_FUNC_SDMMC1_D0>,
257 <STM32F746_PC9_FUNC_SDMMC1_D1>,
258 <STM32F746_PC10_FUNC_SDMMC1_D2>,
259 <STM32F746_PC11_FUNC_SDMMC1_D3>,
260 <STM32F746_PC12_FUNC_SDMMC1_CK>;
266 pinmux = <STM32F746_PD2_FUNC_SDMMC1_CMD>;
272 sdio_pins_b: sdio_pins_b@0 {
274 pinmux = <STM32F769_PG9_FUNC_SDMMC2_D0>,
275 <STM32F769_PG10_FUNC_SDMMC2_D1>,
276 <STM32F769_PB3_FUNC_SDMMC2_D2>,
277 <STM32F769_PB4_FUNC_SDMMC2_D3>,
278 <STM32F769_PD6_FUNC_SDMMC2_CLK>,
279 <STM32F769_PD7_FUNC_SDMMC2_CMD>;
285 sdio_pins_od_b: sdio_pins_od_b@0 {
287 pinmux = <STM32F769_PG9_FUNC_SDMMC2_D0>,
288 <STM32F769_PG10_FUNC_SDMMC2_D1>,
289 <STM32F769_PB3_FUNC_SDMMC2_D2>,
290 <STM32F769_PB4_FUNC_SDMMC2_D3>,
291 <STM32F769_PD6_FUNC_SDMMC2_CLK>;
297 pinmux = <STM32F769_PD7_FUNC_SDMMC2_CMD>;
304 sdio: sdio@40012c00 {
305 compatible = "st,stm32f4xx-sdio";
306 reg = <0x40012c00 0x400>;
307 clocks = <&rcc 0 171>;
310 pinctrl-0 = <&sdio_pins>;
311 pinctrl-1 = <&sdio_pins_od>;
312 pinctrl-names = "default", "opendrain";
313 max-frequency = <48000000>;
316 sdio2: sdio2@40011c00 {
317 compatible = "st,stm32f4xx-sdio";
318 reg = <0x40011c00 0x400>;
319 clocks = <&rcc 0 167>;
322 pinctrl-0 = <&sdio_pins_b>;
323 pinctrl-1 = <&sdio_pins_od_b>;
324 pinctrl-names = "default", "opendrain";
325 max-frequency = <48000000>;
328 timer5: timer@40000c00 {
329 compatible = "st,stm32-timer";
330 reg = <0x40000c00 0x400>;
332 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
335 ltdc: display-controller@40016800 {
336 compatible = "st,stm32-ltdc";
337 reg = <0x40016800 0x200>;
338 resets = <&rcc STM32F7_APB2_RESET(LTDC)>;
339 clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>;