arch/arm/dts/stm32f746-disco-u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2
   3 #include <stm32f7-u-boot.dtsi>
   4 /{
   5         chosen {
   6                 bootargs = "root=/dev/ram rdinit=/linuxrc";
   7         };
   8
   9         aliases {
  10                 /* Aliases for gpios so as to use sequence */
  11                 gpio0 = &gpioa;
  12                 gpio1 = &gpiob;
  13                 gpio2 = &gpioc;
  14                 gpio3 = &gpiod;
  15                 gpio4 = &gpioe;
  16                 gpio5 = &gpiof;
  17                 gpio6 = &gpiog;
  18                 gpio7 = &gpioh;
  19                 gpio8 = &gpioi;
  20                 gpio9 = &gpioj;
  21                 gpio10 = &gpiok;
  22                 mmc0 = &sdio1;
  23                 spi0 = &qspi;
  24         };
  25
  26         backlight: backlight {
  27                 compatible = "gpio-backlight";
  28                 gpios = <&gpiok 3 0>;
  29                 status = "okay";
  30         };
  31
  32         button1 {
  33                 compatible = "st,button1";
  34                 button-gpio = <&gpioi 11 0>;
  35         };
  36
  37         led1 {
  38                 compatible = "st,led1";
  39                 led-gpio = <&gpioi 1 0>;
  40         };
  41
  42         panel-rgb@0 {
  43                 compatible = "simple-panel";
  44                 backlight = <&backlight>;
  45                 enable-gpios = <&gpioi 12 0>;
  46                 status = "okay";
  47
  48                 display-timings {
  49                         timing@0 {
  50                                 clock-frequency = <9000000>;
  51                                 hactive = <480>;
  52                                 vactive = <272>;
  53                                 hfront-porch = <2>;
  54                                 hback-porch = <2>;
  55                                 hsync-len = <41>;
  56                                 vfront-porch = <2>;
  57                                 vback-porch = <2>;
  58                                 vsync-len = <10>;
  59                                 hsync-active = <0>;
  60                                 vsync-active = <0>;
  61                                 de-active = <0>;
  62                                 pixelclk-active = <1>;
  63                         };
  64                 };
  65         };
  66
  67         soc {
  68                 ltdc: display-controller@40016800 {
  69                         compatible = "st,stm32-ltdc";
  70                         reg = <0x40016800 0x200>;
  71                         resets = <&rcc STM32F7_APB2_RESET(LTDC)>;
  72                         clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>;
  73                         pinctrl-0 = <&ltdc_pins>;
  74
  75                         status = "okay";
  76                         u-boot,dm-pre-reloc;
  77                 };
  78         };
  79 };
  80
  81 &clk_hse {
  82         u-boot,dm-pre-reloc;
  83 };
  84
  85 &fmc {
  86         /* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */
  87         bank1: bank@0 {
  88                 u-boot,dm-pre-reloc;
  89                 st,sdram-control = /bits/ 8 <NO_COL_8
  90                                              NO_ROW_12
  91                                              MWIDTH_16
  92                                              BANKS_4
  93                                              CAS_3
  94                                              SDCLK_2
  95                                              RD_BURST_EN
  96                                              RD_PIPE_DL_0>;
  97                 st,sdram-timing = /bits/ 8 <TMRD_2
  98                                             TXSR_6
  99                                             TRAS_4
 100                                             TRC_6
 101                                             TWR_2
 102                                             TRP_2
 103                                             TRCD_2>;
 104                 /* refcount = (64msec/total_row_sdram)*freq - 20 */
 105                 st,sdram-refcount = < 1542 >;
 106         };
 107 };
 108
 109 &pinctrl {
 110         ethernet_mii: mii@0 {
 111                 pins {
 112                         pinmux = <STM32_PINMUX('G',13, AF11)>, /* ETH_RMII_TXD0 */
 113                                  <STM32_PINMUX('G',14, AF11)>, /* ETH_RMII_TXD1 */
 114                                  <STM32_PINMUX('G',11, AF11)>, /* ETH_RMII_TX_EN */
 115                                  <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
 116                                  <STM32_PINMUX('C', 1, AF11)>, /* ETH_MDC */
 117                                  <STM32_PINMUX('A', 1, AF11)>, /* ETH_RMII_REF_CLK */
 118                                  <STM32_PINMUX('A', 7, AF11)>, /* ETH_RMII_CRS_DV */
 119                                  <STM32_PINMUX('C', 4, AF11)>, /* ETH_RMII_RXD0 */
 120                                  <STM32_PINMUX('C', 5, AF11)>; /* ETH_RMII_RXD1 */
 121                         slew-rate = <2>;
 122                 };
 123         };
 124
 125         fmc_pins: fmc@0 {
 126                 u-boot,dm-pre-reloc;
 127                 pins {
 128                         u-boot,dm-pre-reloc;
 129                         pinmux = <STM32_PINMUX('D',10, AF12)>, /* D15 */
 130                                  <STM32_PINMUX('D', 9, AF12)>, /* D14 */
 131                                  <STM32_PINMUX('D', 8, AF12)>, /* D13 */
 132                                  <STM32_PINMUX('E',15, AF12)>, /* D12 */
 133                                  <STM32_PINMUX('E',14, AF12)>, /* D11 */
 134                                  <STM32_PINMUX('E',13, AF12)>, /* D10 */
 135                                  <STM32_PINMUX('E',12, AF12)>, /* D9 */
 136                                  <STM32_PINMUX('E',11, AF12)>, /* D8 */
 137                                  <STM32_PINMUX('E',10, AF12)>, /* D7 */
 138                                  <STM32_PINMUX('E', 9, AF12)>, /* D6 */
 139                                  <STM32_PINMUX('E', 8, AF12)>, /* D5 */
 140                                  <STM32_PINMUX('E', 7, AF12)>, /* D4 */
 141                                  <STM32_PINMUX('D', 1, AF12)>, /* D3 */
 142                                  <STM32_PINMUX('D', 0, AF12)>, /* D2 */
 143                                  <STM32_PINMUX('D',15, AF12)>, /* D1 */
 144                                  <STM32_PINMUX('D',14, AF12)>, /* D0 */
 145
 146                                  <STM32_PINMUX('E', 1, AF12)>, /* NBL1 */
 147                                  <STM32_PINMUX('E', 0, AF12)>, /* NBL0 */
 148
 149                                  <STM32_PINMUX('G', 5, AF12)>, /* BA1 */
 150                                  <STM32_PINMUX('G', 4, AF12)>, /* BA0 */
 151
 152                                  <STM32_PINMUX('G', 1, AF12)>, /* A11 */
 153                                  <STM32_PINMUX('G', 0, AF12)>, /* A10 */
 154                                  <STM32_PINMUX('F',15, AF12)>, /* A9 */
 155                                  <STM32_PINMUX('F',14, AF12)>, /* A8 */
 156                                  <STM32_PINMUX('F',13, AF12)>, /* A7 */
 157                                  <STM32_PINMUX('F',12, AF12)>, /* A6 */
 158                                  <STM32_PINMUX('F', 5, AF12)>, /* A5 */
 159                                  <STM32_PINMUX('F', 4, AF12)>, /* A4 */
 160                                  <STM32_PINMUX('F', 3, AF12)>, /* A3 */
 161                                  <STM32_PINMUX('F', 2, AF12)>, /* A2 */
 162                                  <STM32_PINMUX('F', 1, AF12)>, /* A1 */
 163                                  <STM32_PINMUX('F', 0, AF12)>, /* A0 */
 164
 165                                  <STM32_PINMUX('H', 3, AF12)>, /* SDNE0 */
 166                                  <STM32_PINMUX('H', 5, AF12)>, /* SDNWE */
 167                                  <STM32_PINMUX('F',11, AF12)>, /* SDNRAS */
 168                                  <STM32_PINMUX('G',15, AF12)>, /* SDNCAS */
 169                                  <STM32_PINMUX('C', 3, AF12)>, /* SDCKE0 */
 170                                  <STM32_PINMUX('G', 8, AF12)>; /* SDCLK> */
 171                         slew-rate = <2>;
 172                 };
 173         };
 174
 175         ltdc_pins: ltdc@0 {
 176                 pins {
 177                         pinmux = <STM32_PINMUX('E', 4, AF14)>, /* B0 */
 178                                  <STM32_PINMUX('G',12, AF14)>, /* B4 */
 179                                  <STM32_PINMUX('I', 9, AF14)>, /* VSYNC */
 180                                  <STM32_PINMUX('I',10, AF14)>, /* HSYNC */
 181                                  <STM32_PINMUX('I',14, AF14)>, /* CLK */
 182                                  <STM32_PINMUX('I',15, AF14)>, /* R0 */
 183                                  <STM32_PINMUX('J', 0, AF14)>, /* R1 */
 184                                  <STM32_PINMUX('J', 1, AF14)>, /* R2 */
 185                                  <STM32_PINMUX('J', 2, AF14)>, /* R3 */
 186                                  <STM32_PINMUX('J', 3, AF14)>, /* R4 */
 187                                  <STM32_PINMUX('J', 4, AF14)>, /* R5 */
 188                                  <STM32_PINMUX('J', 5, AF14)>, /* R6 */
 189                                  <STM32_PINMUX('J', 6, AF14)>, /* R7 */
 190                                  <STM32_PINMUX('J', 7, AF14)>, /* G0 */
 191                                  <STM32_PINMUX('J', 8, AF14)>, /* G1 */
 192                                  <STM32_PINMUX('J', 9, AF14)>, /* G2 */
 193                                  <STM32_PINMUX('J',10, AF14)>, /* G3 */
 194                                  <STM32_PINMUX('J',11, AF14)>, /* G4 */
 195                                  <STM32_PINMUX('J',13, AF14)>, /* B1 */
 196                                  <STM32_PINMUX('J',14, AF14)>, /* B2 */
 197                                  <STM32_PINMUX('J',15, AF14)>, /* B3 */
 198                                  <STM32_PINMUX('K', 0, AF14)>, /* G5 */
 199                                  <STM32_PINMUX('K', 1, AF14)>, /* G6 */
 200                                  <STM32_PINMUX('K', 2, AF14)>, /* G7 */
 201                                  <STM32_PINMUX('K', 4, AF14)>, /* B5 */
 202                                  <STM32_PINMUX('K', 5, AF14)>, /* B6 */
 203                                  <STM32_PINMUX('K', 6, AF14)>, /* B7 */
 204                                  <STM32_PINMUX('K', 7, AF14)>; /* DE */
 205                         slew-rate = <2>;
 206                 };
 207         };
 208
 209         qspi_pins: qspi@0 {
 210                 pins {
 211                         pinmux = <STM32_PINMUX('B', 2, AF9)>, /* CLK */
 212                                  <STM32_PINMUX('B', 6, AF10)>, /* BK1_NCS */
 213                                  <STM32_PINMUX('D',11, AF9)>, /* BK1_IO0 */
 214                                  <STM32_PINMUX('D',12, AF9)>, /* BK1_IO1 */
 215                                  <STM32_PINMUX('D',13, AF9)>, /* BK1_IO3 */
 216                                  <STM32_PINMUX('E', 2, AF9)>; /* BK1_IO2 */
 217                         slew-rate = <2>;
 218                 };
 219         };
 220
 221         usart1_pins_b: usart1@1 {
 222                 u-boot,dm-pre-reloc;
 223                 pins1 {
 224                         u-boot,dm-pre-reloc;
 225                 };
 226                 pins2 {
 227                         u-boot,dm-pre-reloc;
 228                 };
 229         };
 230 };
 231
 232 &pwrcfg {
 233         u-boot,dm-pre-reloc;
 234 };
 235
 236 &qspi {
 237         reg = <0xA0001000 0x1000>, <0x90000000 0x1000000>;
 238         qflash0: n25q128a {
 239                 #address-cells = <1>;
 240                 #size-cells = <1>;
 241                 compatible = "micron,n25q128a13", "jedec,spi-nor";
 242                 spi-max-frequency = <108000000>;
 243                 spi-tx-bus-width = <4>;
 244                 spi-rx-bus-width = <4>;
 245                 reg = <0>;
 246         };
 247 };
 248
 249 &timer5 {
 250         u-boot,dm-pre-reloc;
 251 };