arch/arm/dts/stm32f7-u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2
   3 #include <dt-bindings/memory/stm32-sdram.h>
   4 /{
   5         soc {
   6                 u-boot,dm-pre-reloc;
   7
   8                 fmc: fmc@A0000000 {
   9                         compatible = "st,stm32-fmc";
  10                         reg = <0xA0000000 0x1000>;
  11                         clocks = <&rcc 0 STM32F7_AHB3_CLOCK(FMC)>;
  12                         pinctrl-0 = <&fmc_pins>;
  13                         pinctrl-names = "default";
  14                         status = "okay";
  15                         u-boot,dm-pre-reloc;
  16                 };
  17
  18                 mac: ethernet@40028000 {
  19                         compatible = "st,stm32-dwmac";
  20                         reg = <0x40028000 0x8000>;
  21                         reg-names = "stmmaceth";
  22                         clocks = <&rcc 0 STM32F7_AHB1_CLOCK(ETHMAC)>,
  23                                  <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACTX)>,
  24                                  <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACRX)>;
  25                         interrupts = <61>, <62>;
  26                         interrupt-names = "macirq", "eth_wake_irq";
  27                         snps,pbl = <8>;
  28                         snps,mixed-burst;
  29                         dma-ranges;
  30                         pinctrl-0 = <&ethernet_mii>;
  31                         phy-mode = "rmii";
  32                         phy-handle = <&phy0>;
  33
  34                         status = "okay";
  35
  36                         mdio0 {
  37                                 #address-cells = <1>;
  38                                 #size-cells = <0>;
  39                                 compatible = "snps,dwmac-mdio";
  40                                 phy0: ethernet-phy@0 {
  41                                         reg = <0>;
  42                                 };
  43                         };
  44                 };
  45
  46                 qspi: quadspi@A0001000 {
  47                         compatible = "st,stm32f469-qspi";
  48                         #address-cells = <1>;
  49                         #size-cells = <0>;
  50                         reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>;
  51                         reg-names = "qspi", "qspi_mm";
  52                         interrupts = <92>;
  53                         spi-max-frequency = <108000000>;
  54                         clocks = <&rcc 0 STM32F7_AHB3_CLOCK(QSPI)>;
  55                         resets = <&rcc STM32F7_AHB3_RESET(QSPI)>;
  56                         pinctrl-0 = <&qspi_pins>;
  57
  58                         status = "okay";
  59                 };
  60         };
  61 };
  62
  63 &clk_hse {
  64         u-boot,dm-pre-reloc;
  65 };
  66
  67 &gpioa {
  68         u-boot,dm-pre-reloc;
  69 };
  70
  71 &gpiob {
  72         u-boot,dm-pre-reloc;
  73 };
  74
  75 &gpioc {
  76         u-boot,dm-pre-reloc;
  77 };
  78
  79 &gpiod {
  80         u-boot,dm-pre-reloc;
  81 };
  82
  83 &gpioe {
  84         u-boot,dm-pre-reloc;
  85 };
  86
  87 &gpiof {
  88         u-boot,dm-pre-reloc;
  89 };
  90
  91 &gpiog {
  92         u-boot,dm-pre-reloc;
  93 };
  94
  95 &gpioh {
  96         u-boot,dm-pre-reloc;
  97 };
  98
  99 &gpioi {
 100         u-boot,dm-pre-reloc;
 101 };
 102
 103 &pinctrl {
 104         u-boot,dm-pre-reloc;
 105
 106         fmc_pins: fmc@0 {
 107                 u-boot,dm-pre-reloc;
 108                 pins
 109                 {
 110                  u-boot,dm-pre-reloc;
 111                 };
 112         };
 113 };
 114
 115 &pwrcfg {
 116         u-boot,dm-pre-reloc;
 117 };
 118
 119 &rcc {
 120         u-boot,dm-pre-reloc;
 121 };
 122
 123 &timer5 {
 124         u-boot,dm-pre-reloc;
 125 };
 126
 127 &usart1 {
 128         u-boot,dm-pre-reloc;
 129         clocks = <&rcc 0 STM32F7_APB2_CLOCK(USART1)>;
 130 };