arch/arm/dts/stm32f469-disco-u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
   4  * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
   5  */
   6
   7 #include <dt-bindings/memory/stm32-sdram.h>
   8 /{
   9         clocks {
  10                 u-boot,dm-pre-reloc;
  11         };
  12
  13         aliases {
  14                 /* Aliases for gpios so as to use sequence */
  15                 gpio0 = &gpioa;
  16                 gpio1 = &gpiob;
  17                 gpio2 = &gpioc;
  18                 gpio3 = &gpiod;
  19                 gpio4 = &gpioe;
  20                 gpio5 = &gpiof;
  21                 gpio6 = &gpiog;
  22                 gpio7 = &gpioh;
  23                 gpio8 = &gpioi;
  24                 gpio9 = &gpioj;
  25                 gpio10 = &gpiok;
  26                 spi0 = &qspi;
  27         };
  28
  29         soc {
  30                 u-boot,dm-pre-reloc;
  31                 pin-controller {
  32                         u-boot,dm-pre-reloc;
  33                 };
  34
  35                 fmc: fmc@A0000000 {
  36                         compatible = "st,stm32-fmc";
  37                         reg = <0xA0000000 0x1000>;
  38                         clocks = <&rcc 0 STM32F4_AHB3_CLOCK(FMC)>;
  39                         st,syscfg = <&syscfg>;
  40                         pinctrl-0 = <&fmc_pins_d32>;
  41                         pinctrl-names = "default";
  42                         st,mem_remap = <4>;
  43                         u-boot,dm-pre-reloc;
  44
  45                         /*
  46                          * Memory configuration from sdram
  47                          * MICRON MT48LC4M32B2B5-6A
  48                          */
  49                         bank0: bank@0 {
  50                                st,sdram-control = /bits/ 8 <NO_COL_8
  51                                                             NO_ROW_12
  52                                                             MWIDTH_32
  53                                                             BANKS_4
  54                                                             CAS_3
  55                                                             SDCLK_2
  56                                                             RD_BURST_EN
  57                                                             RD_PIPE_DL_0>;
  58                                st,sdram-timing = /bits/ 8 <TMRD_2
  59                                                            TXSR_6
  60                                                            TRAS_4
  61                                                            TRC_6
  62                                                            TWR_2
  63                                                            TRP_2
  64                                                            TRCD_2>;
  65                                st,sdram-refcount = < 1292 >;
  66                        };
  67                 };
  68
  69                 qspi: quadspi@A0001000 {
  70                         compatible = "st,stm32-qspi";
  71                         #address-cells = <1>;
  72                         #size-cells = <0>;
  73                         reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>;
  74                         reg-names = "qspi", "qspi_mm";
  75                         interrupts = <91>;
  76                         spi-max-frequency = <108000000>;
  77                         clocks = <&rcc 0 STM32F4_AHB3_CLOCK(QSPI)>;
  78                         resets = <&rcc STM32F4_AHB3_RESET(QSPI)>;
  79                         pinctrl-0 = <&qspi_pins>;
  80                 };
  81         };
  82 };
  83
  84 &clk_hse {
  85         u-boot,dm-pre-reloc;
  86 };
  87
  88 &clk_i2s_ckin {
  89         u-boot,dm-pre-reloc;
  90 };
  91
  92 &clk_lse {
  93         u-boot,dm-pre-reloc;
  94 };
  95
  96 &gpioa {
  97         compatible = "st,stm32-gpio";
  98         u-boot,dm-pre-reloc;
  99 };
 100
 101 &gpiob {
 102         compatible = "st,stm32-gpio";
 103         u-boot,dm-pre-reloc;
 104 };
 105
 106 &gpioc {
 107         compatible = "st,stm32-gpio";
 108         u-boot,dm-pre-reloc;
 109 };
 110
 111 &gpiod {
 112         compatible = "st,stm32-gpio";
 113         u-boot,dm-pre-reloc;
 114 };
 115
 116 &gpioe {
 117         compatible = "st,stm32-gpio";
 118         u-boot,dm-pre-reloc;
 119 };
 120
 121 &gpiof {
 122         compatible = "st,stm32-gpio";
 123         u-boot,dm-pre-reloc;
 124 };
 125
 126 &gpiog {
 127         compatible = "st,stm32-gpio";
 128         u-boot,dm-pre-reloc;
 129 };
 130
 131 &gpioh {
 132         compatible = "st,stm32-gpio";
 133         u-boot,dm-pre-reloc;
 134 };
 135
 136 &gpioi {
 137         compatible = "st,stm32-gpio";
 138         u-boot,dm-pre-reloc;
 139 };
 140
 141 &gpioj {
 142         compatible = "st,stm32-gpio";
 143         u-boot,dm-pre-reloc;
 144 };
 145
 146 &gpiok {
 147         compatible = "st,stm32-gpio";
 148         u-boot,dm-pre-reloc;
 149 };
 150
 151 &pinctrl {
 152         fmc_pins_d32: fmc_d32@0 {
 153                 u-boot,dm-pre-reloc;
 154                 pins
 155                 {
 156                         pinmux = <STM32_PINMUX('I',10, AF12)>, /* D31 */
 157                                  <STM32_PINMUX('I', 9, AF12)>, /* D30 */
 158                                  <STM32_PINMUX('I', 7, AF12)>, /* D29 */
 159                                  <STM32_PINMUX('I', 6, AF12)>, /* D28 */
 160                                  <STM32_PINMUX('I', 3, AF12)>, /* D27 */
 161                                  <STM32_PINMUX('I', 2, AF12)>, /* D26 */
 162                                  <STM32_PINMUX('I', 1, AF12)>, /* D25 */
 163                                  <STM32_PINMUX('I', 0, AF12)>, /* D24 */
 164                                  <STM32_PINMUX('H',15, AF12)>, /* D23 */
 165                                  <STM32_PINMUX('H',14, AF12)>, /* D22 */
 166                                  <STM32_PINMUX('H',13, AF12)>, /* D21 */
 167                                  <STM32_PINMUX('H',12, AF12)>, /* D20 */
 168                                  <STM32_PINMUX('H',11, AF12)>, /* D19 */
 169                                  <STM32_PINMUX('H',10, AF12)>, /* D18 */
 170                                  <STM32_PINMUX('H', 9, AF12)>, /* D17 */
 171                                  <STM32_PINMUX('H', 8, AF12)>, /* D16 */
 172
 173                                  <STM32_PINMUX('D',10, AF12)>, /* D15 */
 174                                  <STM32_PINMUX('D', 9, AF12)>, /* D14 */
 175                                  <STM32_PINMUX('D', 8, AF12)>, /* D13 */
 176                                  <STM32_PINMUX('E',15, AF12)>, /* D12 */
 177                                  <STM32_PINMUX('E',14, AF12)>, /* D11 */
 178                                  <STM32_PINMUX('E',13, AF12)>, /* D10 */
 179                                  <STM32_PINMUX('E',12, AF12)>, /* D09 */
 180                                  <STM32_PINMUX('E',11, AF12)>, /* D08 */
 181                                  <STM32_PINMUX('E',10, AF12)>, /* D07 */
 182                                  <STM32_PINMUX('E', 9, AF12)>, /* D06 */
 183                                  <STM32_PINMUX('E', 8, AF12)>, /* D05 */
 184                                  <STM32_PINMUX('E', 7, AF12)>, /* D04 */
 185                                  <STM32_PINMUX('D', 1, AF12)>, /* D03 */
 186                                  <STM32_PINMUX('D', 0, AF12)>, /* D02 */
 187                                  <STM32_PINMUX('D',15, AF12)>, /* D01 */
 188                                  <STM32_PINMUX('D',14, AF12)>, /* D00 */
 189
 190                                  <STM32_PINMUX('E', 0, AF12)>, /* NBL0 */
 191                                  <STM32_PINMUX('E', 1, AF12)>, /* NBL1 */
 192                                  <STM32_PINMUX('I', 4, AF12)>, /* NBL2 */
 193                                  <STM32_PINMUX('I', 5, AF12)>, /* NBL3 */
 194
 195                                  <STM32_PINMUX('G', 5, AF12)>, /* BA1 */
 196                                  <STM32_PINMUX('G', 4, AF12)>, /* BA0 */
 197
 198                                  <STM32_PINMUX('G', 1, AF12)>, /* A11 */
 199                                  <STM32_PINMUX('G', 0, AF12)>, /* A10 */
 200                                  <STM32_PINMUX('F',15, AF12)>, /* A09 */
 201                                  <STM32_PINMUX('F',14, AF12)>, /* A08 */
 202                                  <STM32_PINMUX('F',13, AF12)>, /* A07 */
 203                                  <STM32_PINMUX('F',12, AF12)>, /* A06 */
 204                                  <STM32_PINMUX('F', 5, AF12)>, /* A05 */
 205                                  <STM32_PINMUX('F', 4, AF12)>, /* A04 */
 206                                  <STM32_PINMUX('F', 3, AF12)>, /* A03 */
 207                                  <STM32_PINMUX('F', 2, AF12)>, /* A02 */
 208                                  <STM32_PINMUX('F', 1, AF12)>, /* A01 */
 209                                  <STM32_PINMUX('F', 0, AF12)>, /* A00 */
 210
 211                                  <STM32_PINMUX('H', 3, AF12)>, /* SDNE0 */
 212                                  <STM32_PINMUX('C', 0, AF12)>, /* SDNWE */
 213                                  <STM32_PINMUX('F',11, AF12)>, /* SDNRAS */
 214                                  <STM32_PINMUX('G',15, AF12)>, /* SDNCAS */
 215                                  <STM32_PINMUX('H', 2, AF12)>, /* SDCKE0 */
 216                                  <STM32_PINMUX('G', 8, AF12)>; /* SDCLK> */
 217                         slew-rate = <2>;
 218                         u-boot,dm-pre-reloc;
 219                 };
 220         };
 221
 222         qspi_pins: qspi@0 {
 223                 pins {
 224                         pinmux = <STM32_PINMUX('F',10, AF9)>, /* CLK */
 225                                  <STM32_PINMUX('B', 6, AF10)>, /* BK1_NCS */
 226                                  <STM32_PINMUX('F', 8, AF10)>, /* BK1_IO0 */
 227                                  <STM32_PINMUX('F', 9, AF10)>, /* BK1_IO1 */
 228                                  <STM32_PINMUX('F', 7, AF9)>, /* BK1_IO2 */
 229                                  <STM32_PINMUX('F', 6, AF9)>; /* BK1_IO3 */
 230                         slew-rate = <2>;
 231                 };
 232         };
 233
 234         usart3_pins_a: usart3@0 {
 235                 u-boot,dm-pre-reloc;
 236                 pins1 {
 237                         u-boot,dm-pre-reloc;
 238                 };
 239                 pins2 {
 240                         u-boot,dm-pre-reloc;
 241                 };
 242         };
 243 };
 244
 245 &pwrcfg {
 246         u-boot,dm-pre-reloc;
 247 };
 248
 249 &rcc {
 250         u-boot,dm-pre-reloc;
 251 };
 252
 253 &syscfg {
 254         u-boot,dm-pre-reloc;
 255 };
 256
 257 &qspi {
 258         reg = <0xA0001000 0x1000>, <0x90000000 0x1000000>;
 259         flash0: n25q128a {
 260                 #address-cells = <1>;
 261                 #size-cells = <1>;
 262                 compatible = "jedec,spi-nor";
 263                 spi-max-frequency = <108000000>;
 264                 spi-tx-bus-width = <4>;
 265                 spi-rx-bus-width = <4>;
 266                 reg = <0>;
 267         };
 268 };